Current backflow prevention circuit for electric energy meter

Abstract

The utility model discloses a current backflow prevention circuit for an electric energy meter. The current backflow prevention circuit comprises a PMOS transistor V1, a PNP triode V2, a diode D1, a resistor R5 and a resistor R6. The voltage input end VIN is connected with the drain electrode of the PMOS tube V1, and the source electrode of the PMOS tube V1 is connected with the voltage output end VOUT. The current backflow prevention circuit for the electric energy meter further comprises a voltage sampling circuit and a voltage comparison circuit. The utility model solves the problem of high tube voltage drop when the super capacitor is charged, improves the utilization rate of the super capacitor, and has the advantages of timely response, strong anti-interference capability and the like.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of protection circuit, specifically relates to a current anti-inrush circuit of electric energy meter. BACKGROUND

[0002] In the current electric power measurement field, the newly installed electric energy meter generally adopts the replaceable battery design scheme, and in order to ensure the continuous operation of the electric energy meter under the condition of power failure, a backup power supply system is specially provided. As an important backup power supply, the super capacitor functions to ensure that the accuracy of the internal clock of the electric energy meter is not affected by the fluctuation of external power supply. Figure 2 In the traditional electric energy meter design scheme, in order to prevent current from inrush when the power supply is reversed, a diode is generally used as a protection element. This scheme is based on the unidirectional conduction characteristic of the diode, and theoretically can effectively prevent the reverse current.

[0003] However, the traditional scheme has exposed some technical defects in practical application: first, the diode inevitably produces a certain voltage drop in the forward conduction state, which directly leads to the voltage drop of about 0.6V across the super capacitor, affecting the energy storage efficiency of the super capacitor. Secondly, when the super capacitor fails due to various reasons, the existing protection scheme cannot respond in time and cut off the load, which causes the power supply system of the electric energy meter to have to bear a long-term high load working state. Long-term high-load operation not only accelerates the aging of the power supply components, but also greatly increases the risk of power supply burning out, which may eventually lead to the overall failure of the electric energy meter, affecting the accuracy and reliability of electric power measurement. UTILITY MODEL CONTENTS

[0004] The utility model provides a current anti-inrush circuit for electric energy meter, and the purpose is: 1, solve the problem that the voltage drop of current anti-inrush circuit affects the energy storage efficiency;2, solve the problem that the super capacitor cannot cut off the load in time when it fails.

[0005] The utility model technical scheme is as follows:

[0006] A current anti-inrush circuit for electric energy meter, comprising a voltage input end VIN and a voltage output end VOUT, further comprising a PMOS tube V1, a PNP triode V2, a diode D1, a resistor R5 and a resistor R6;

[0007] The voltage input end VIN is connected with the drain of the PMOS transistor V1, the source of the PMOS transistor V1 is connected with the voltage output end VOUT; the source of the PMOS transistor V1 is also connected with the anode of the diode D1, the cathode of the diode D1 is connected with the emitter of the PNP transistor V2, the collector of the PNP transistor V2 is connected with the ground through the resistor R6, the collector of the PNP transistor V2 is also connected with the gate of the PMOS transistor V1; the base of the PNP transistor V2 is connected with the source of the PMOS transistor V1 through the resistor R5;

[0008] The electric energy meter anti-current backflow circuit further comprises a voltage sampling circuit and a voltage comparison circuit; the voltage sampling circuit is used for detecting the voltage value of the voltage input end VIN; the voltage comparison circuit is used for comparing the voltage value collected by the voltage sampling circuit with an upper limit voltage and a lower limit voltage, and the output end of the voltage comparison circuit is connected with the base of the PNP transistor V2.

[0009] As a further improvement of the electric energy meter anti-current backflow circuit, the voltage sampling circuit comprises the resistor R1 and the variable resistor VR1 connected in series between the voltage input end VIN and the ground end, and the voltage output end of the voltage sampling circuit is connected with the moving piece pin and one of the fixed piece pins of the variable resistor VR1.

[0010] As a further improvement of the electric energy meter anti-current backflow circuit, the voltage comparison circuit comprises the comparator D2A and the comparator D2B; the non-inverting input end of the comparator D2A is used for inputting the upper limit voltage, the non-inverting input end of the comparator D2B is used for inputting the lower limit voltage, the inverting input end of the comparator D2A and the inverting input end of the comparator D2B are simultaneously connected with the voltage output end of the voltage sampling circuit; the output end of the comparator D2A and the output end of the comparator D2B are connected and serve as the output end of the voltage comparison circuit.

[0011] As a further improvement of the electric energy meter anti-current backflow circuit, the voltage comparison circuit further comprises the resistor R2, the resistor R3 and the resistor R4 connected in series between the power supply end VCC and the ground end, the connection end between the resistor R2 and the resistor R3 is used for outputting the upper limit voltage and is connected with the non-inverting input end of the comparator D2A, and the connection end between the resistor R3 and the resistor R4 is used for outputting the lower limit voltage and is connected with the non-inverting input end of the comparator D2B.

[0012] As a further improvement of the electric energy meter anti-current backflow circuit, the electric energy meter anti-current backflow circuit further comprises the capacitor C5 connected between the source and the gate of the PMOS transistor V1.

[0013] As a further improvement of the electric energy meter anti-current backflow circuit, the electric energy meter anti-current backflow circuit further comprises the current sampling circuit and the overcurrent protection control circuit.

[0014] The current sampling circuit is used for collecting the current between the voltage input end VIN and the voltage output end VOUT.

[0015] The output end of the overcurrent protection control circuit is connected with the gate of the PMOS tube V1, and is used for controlling the PMOS tube V1 to be cut off according to the sampling value of the current sampling circuit.

[0016] As a further improvement of the anti-current backflow circuit for the electric energy meter, the current sampling circuit comprises a resistor R7 connected between the voltage input end VIN and the drain of the PMOS tube V1.

[0017] As a further improvement of the anti-current backflow circuit for the electric energy meter, the overcurrent protection control circuit comprises an overcurrent protection chip D3, a resistor R8, a resistor R9, a resistor R10, a PNP triode V3, an NPN triode V4 and a diode D4.

[0018] The positive input end and the negative input end of the overcurrent protection chip D3 are respectively connected with two ends of the resistor R7, the output end is connected with the ground through the resistor R8 and is further connected with the anode of the diode D4 through the resistor R10, the cathode of the diode D4 is connected with the base of the NPN triode V4; the emitter of the NPN triode V4 is connected with the ground, the collector is connected with the drain of the PMOS tube V1 through the resistor R9, and the collector of the NPN triode V4 is further connected with the base of the PNP triode V3; the emitter of the PNP triode V3 is connected with the drain of the PMOS tube V1, and the collector is connected with the gate of the PMOS tube V1.

[0019] Compared with the prior art, the utility model has following positive effects:

[0020] 1, the PMOS tube in this circuit is reversely arranged, the drain is connected with the voltage input end, the voltage drop when conducting can be ignored, thereby making the output voltage close to the input voltage, the problem that the tube voltage drop is high when the super capacitor is charging is solved, and the utilization rate of the super capacitor is improved.

[0021] 2, the circuit adopts double comparators to judge the range of input voltage, and when the input voltage exceeds the preset voltage range, the load can be immediately cut off through V2 and V1.

[0022] 3, the circuit also has an overcurrent protection function, and can immediately cut off the load when the current exceeds the preset value. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is the circuit diagram of the utility model;

[0024] Figure 2 It is the circuit diagram of the traditional scheme. DETAILED DESCRIPTION

[0025] The technical solutions of the utility model will be described below in detail with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the utility model, not all of the embodiments.

[0026] As Figure 1 The anti-current backflow circuit for electric energy meter comprises a voltage input end VIN and a voltage output end VOUT, and further comprises a PMOS transistor V1, a PNP transistor V2, a diode D1, a resistor R5 and a resistor R6.

[0027] The voltage input end VIN is connected with the drain of the PMOS transistor V1, and the source of the PMOS transistor V1 is connected with the voltage output end VOUT. The source of the PMOS transistor V1 is further connected with the anode of the diode D1, the cathode of the diode D1 is connected with the emitter of the PNP transistor V2, the collector of the PNP transistor V2 is connected with the ground through the resistor R6, and the collector of the PNP transistor V2 is further connected with the gate of the PMOS transistor V1; the base of the PNP transistor V2 is connected with the source of the PMOS transistor V1 through the resistor R5. The anti-current backflow circuit for electric energy meter further comprises a capacitor C5 connected between the source and the gate of the PMOS transistor V1.

[0028] The anti-current backflow circuit for electric energy meter further comprises a voltage sampling circuit and a voltage comparison circuit.

[0029] The voltage sampling circuit is used for detecting the voltage value of the voltage input end VIN. In the embodiment, the voltage sampling circuit comprises a resistor R1 and a variable resistor VR1 connected in series between the voltage input end VIN and the ground, and the voltage output end of the voltage sampling circuit is connected with the moving tab pin and one of the fixed tab pins of the variable resistor VR1.

[0030] The voltage comparison circuit is used for comparing the voltage value collected by the voltage sampling circuit with an upper limit voltage and a lower limit voltage, and the output end of the voltage comparison circuit is connected with the base of the PNP transistor V2. Specifically, the voltage comparison circuit comprises a comparator D2A and a comparator D2B. The non-inverting input end of the comparator D2A is used for inputting the upper limit voltage, the non-inverting input end of the comparator D2B is used for inputting the lower limit voltage, the inverting input end of the comparator D2A and the inverting input end of the comparator D2B are simultaneously connected with the voltage output end of the voltage sampling circuit; the output end of the comparator D2A and the output end of the comparator D2B are connected and serve as the output end of the voltage comparison circuit.

[0031] Furthermore, the voltage comparison circuit also includes a resistor R2, a resistor R3, and a resistor R4 connected in series between the power supply terminal VCC and the ground terminal, the connection terminal between the resistor R2 and the resistor R3 is used to output the upper limit voltage and is connected to the non-inverting input terminal of the comparator D2A, and the connection terminal between the resistor R3 and the resistor R4 is used to output the lower limit voltage and is connected to the non-inverting input terminal of the comparator D2B.

[0032] The anti-current backflow circuit for the electric energy meter also includes a current sampling circuit and an overcurrent protection control circuit.

[0033] The current sampling circuit is used to collect the current between the voltage input terminal VIN and the voltage output terminal VOUT. In this embodiment, the current sampling circuit includes a resistor R7 connected between the voltage input terminal VIN and the drain of the PMOS transistor V1.

[0034] The output end of the overcurrent protection control circuit is connected to the gate of the PMOS tube V1 and is used to control the PMOS tube V1 to be cut off according to the sampling value of the current sampling circuit.

[0035] Specifically, the overcurrent protection control circuit includes an overcurrent protection chip D3, a resistor R8, a resistor R9, a resistor R10, a PNP transistor V3, an NPN transistor V4 and a diode D4.

[0036] The positive and negative input terminals of overcurrent protection chip D3 are connected to the two ends of resistor R7, respectively. The output terminal is grounded via resistor R8 and connected to the anode of diode D4 via resistor R10. The cathode of diode D4 is connected to the base of NPN transistor V4. The emitter of NPN transistor V4 is grounded, and its collector is connected to the drain of PMOS transistor V1 via resistor R9. The collector of NPN transistor V4 is also connected to the base of PNP transistor V3. The emitter of PNP transistor V3 is connected to the drain of PMOS transistor V1, and its collector is connected to the gate of PMOS transistor V1.

[0037] Assume that initially VIN has a voltage of 5V and VOUT has a voltage of 0V. After high-frequency and low-frequency filtering of the power supply by C1 and C2, VIN is input to the drain of V1 through R7, and the voltage drop of the internal parasitic diode of V1 is generally 0.6V. VIN is input to the output VOUT through the internal parasitic diode of V1, and at this time VOUT = 5-0.6-R7*Is. Since the voltage drop on R7 can be ignored within the set current range, it can be considered that at this time VOUT ≈ 4.4V. The voltage drop of diode D1 is generally 0.6V, so the emitter voltage Ve of V2 = 4.4-0.6 = 3.8V, and at this time the base voltage Vb of V2 = 4.4V, so Vbe of V2 = Vb-Ve = 0.6V, that is, V2 is in the off state. At this time, the gate of V1 is grounded through resistor R6, that is, Vg = 0V, so V1 is saturated and conducts and the internal parasitic diode is short-circuited, so that the output voltage VOUT ≈ VIN = 5V, thereby reducing the voltage drop and improving the energy storage efficiency.

[0038] The anti-backflow mechanism of the circuit is as follows: assume that the voltage at pin 2 of D2 is Vi, the voltage at pin 3 of D2 is VTH, and the voltage at pin 5 of D2 is VTL. VIN is input to pin 2 of chip 2 through resistors R1 and VR1, and the voltage Vi = VIN*VR1 / (R1+VR1). VR1 is a variable resistor, and the conversion ratio of Vi to VIN is changed by adjusting the resistance value of VR1. VTH = VCC*(R3+R4) / (R2+R3+R4), and VTH = VCC*R4 / (R2+R3+R4). D2A and D2B constitute a double-voltage comparison circuit. When the power supply is normally working, the input voltage Vi is within the set range, that is, VTL < Vi < VTH, and at this time D2 outputs an open-drain. In order to avoid the problem of V2 being mis-conducted by interference, a bias resistor R5 is added to the base of V2, and the base of V2 is pulled up to the power supply VOUT through R5, so that V2 remains off. The gate of V1 is pulled down to ground through resistor R6, that is, Vg = 0V, at this time V1 is saturated and conducts, and normal power supply is provided. When the input voltage Vi > VTH or Vi < VTL, the output of D2 chip is low, the transistor V2 is turned on, the gate voltage Vg of V1 becomes high, and V1 is in the off state, so that the input and output are disconnected to achieve anti-backflow.

[0039] The load overcurrent protection mechanism of the circuit is as follows: the output voltage of pin 1 of chip D3 is Vo = Is*R7*gm*R8, wherein Is is the current flowing through R7. By setting the resistance values, when the current is overloaded, that is, Vo > 1.4V, the transistor V4 is turned on, at this time the base voltage of the transistor V3 is 0V, the transistor V3 is saturated and conducts, the gate voltage of V1 is high, V1 is in the off state, and the faulty load is cut off. When the fault disappears, the output voltage Vo is designed to be less than 0.7V, the transistor V4 is cut off, the base of V3 is pulled up by the bias resistor R9, V3 is cut off, and then V1 is turned on to restore the power supply.

[0040] It should be noted that, for those skilled in the art, it is obvious that the utility model is not limited to the details of the above exemplary embodiments, and the utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the utility model. The scope of the utility model is defined by the claims rather than the above description.

Claims

1. A current reverse flow prevention circuit for an electric energy meter, comprising a voltage input terminal VIN and a voltage output terminal VOUT, characterized in that: Also include PMOS V1, PNP transistor V2, diode D1, resistor R5 and resistor R6; The voltage input end VIN is connected with the drain of the PMOS V1, the source of the PMOS V1 is connected with the voltage output end VOUT, the source of the PMOS V1 is also connected with the positive electrode of the diode D1, the negative electrode of the diode D1 is connected with the emitter of the PNP transistor V2, the collector of the PNP transistor V2 is connected with the ground through the resistor R6, the collector of the PNP transistor V2 is also connected with the gate of the PMOS V1, the base of the PNP transistor V2 is connected with the source of the PMOS V1 through the resistor R5; The anti-current backflow circuit for the electric energy meter further comprises a voltage sampling circuit and a voltage comparison circuit; the voltage sampling circuit is used for detecting the voltage value of the voltage input end VIN; The voltage comparison circuit is used for comparing the voltage value collected by the voltage sampling circuit with an upper limit voltage and a lower limit voltage, and the output end of the voltage comparison circuit is connected with the base of the PNP transistor V2.

2. The circuit for preventing reverse current flow of an electric energy meter according to claim 1, characterized by: The voltage sampling circuit comprises a resistor R1 and a variable resistor VR1 connected in series between the voltage input end VIN and the ground end, and the voltage output end of the voltage sampling circuit is connected with the moving piece pin and one of the fixed piece pins of the variable resistor VR1.

3. The circuit for preventing reverse current flow of an electric energy meter according to claim 1, characterized by: The voltage comparison circuit comprises a comparator D2A and a comparator D2B; the non-inverting input end of the comparator D2A is used for inputting the upper limit voltage, the non-inverting input end of the comparator D2B is used for inputting the lower limit voltage, the inverting input end of the comparator D2A and the inverting input end of the comparator D2B are simultaneously connected with the voltage output end of the voltage sampling circuit; the output end of the comparator D2A and the output end of the comparator D2B are connected and serve as the output end of the voltage comparison circuit.

4. The circuit for preventing reverse current flow of an electric energy meter according to claim 3, characterized by: The voltage comparison circuit further comprises a resistor R2, a resistor R3 and a resistor R4 connected in series between the power supply end VCC and the ground end, the connection end between the resistor R2 and the resistor R3 is used for outputting the upper limit voltage and is connected with the non-inverting input end of the comparator D2A, and the connection end between the resistor R3 and the resistor R4 is used for outputting the lower limit voltage and is connected with the non-inverting input end of the comparator D2B.

5. The reverse current prevention circuit for an electric energy meter according to claim 1, wherein: Further comprising a capacitor C5 connected between the source and the gate of the PMOS V1.

6. The circuit for preventing reverse current flow of an electric energy meter according to any one of claims 1 to 5, characterized in that: Further comprising a current sampling circuit and an overcurrent protection control circuit; The current sampling circuit is used for collecting the current between the voltage input end VIN and the voltage output end VOUT; The output end of the overcurrent protection control circuit is connected with the gate of the PMOS V1, and is used for controlling the PMOS V1 to be cut off according to the sampling value of the current sampling circuit.

7. The reverse current prevention circuit for an electric energy meter according to claim 6, wherein: The current sampling circuit comprises a resistor R7 connected between the voltage input end VIN and the drain of the PMOS V1.

8. The electric current reverse flow prevention circuit for an electric energy meter according to claim 7, characterized by: The overcurrent protection control circuit comprises an overcurrent protection chip D3, a resistor R8, a resistor R9, a resistor R10, a PNP transistor V3, an NPN transistor V4 and a diode D4; The positive input end and the negative input end of the over-current protection chip D3 are connected with the two ends of the resistor R7 respectively, the output end is connected with the ground through the resistor R8 and is also connected with the anode of the diode D4 through the resistor R10, the cathode of the diode D4 is connected with the base of the NPN triode V4; the emitter of the NPN triode V4 is connected with the ground, the collector is connected with the drain of the PMOS tube V1 through the resistor R9, the collector of the NPN triode V4 is also connected with the base of the PNP triode V3; the emitter of the PNP triode V3 is connected with the drain of the PMOS tube V1, the collector is connected with the gate of the PMOS tube V1.

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