Fan-out wafer level packaging unit
By filling the dielectric layer grooves with metal paste and grinding it into conductive lines, combined with the outer sheath design, the problems of high cost and environmental unfriendliness of conductive lines in the prior art are solved, achieving a thin, light, and compact packaging effect with high efficiency and reliability.
Patent Information
- Application Number
- CN202422457859.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-10-11
AI Technical Summary
Existing fan-out wafer-level packaging technologies have high manufacturing costs and are not environmentally friendly, and lack packaging solutions tailored to chip designs.
By filling the grooves of the dielectric layer with metal paste and grinding it into conductive lines, combined with the design of the outer sheath, a thin and small package structure is formed. The chip is then fabricated using redistribution layer technology, avoiding chemical plating or electroplating processes.
It reduces the manufacturing cost of conductive lines, simplifies the process, reduces pollution, achieves a thin and compact packaging effect, and improves product versatility and reliability.
Smart Images
Figure CN223471600U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer level packaging unit. BACKGROUND
[0002] Light, thin, short and small packaging technology with high efficiency and high reliability is the development trend of semiconductor industry, and the fan-out wafer level packaging (FOWLP) is an existing packaging technology.
[0003] In the advanced FOWLP, the redistribution layer (RDL) is the most critical, because the various interconnection lines in the RDL can make the multiple pads on the die XY plane electrical extension and interconnection effect for the formation of a more dispersed multiple pads around the die, so as to effectively improve the design space and reliability of the interconnection lines, but how to make the various interconnection lines in the RDL in the XY plane electrical extension and interconnection effect at the same time also can maintain or achieve a certain degree of light, thin, short and small effect, the production of the various interconnection lines in the RDL is the most critical.
[0004] However, the various interconnection lines in the RDL technology applied in the existing FOWLP packaging technology are formed by using plating forming technique or electroplating forming technique, so that in addition to the relatively high material cost and manufacturing cost, the process in the existing technology also does not meet or is not conducive to the requirements of environmental protection.
[0005] In addition, the existing fan-out wafer level packaging unit technology is mainly designed for die (Die), and lacks design for chip (Die on wafer after RDL is completed). UTILITY MODEL CONTENTS
[0006] The main purpose of the utility model is to provide a fan-out wafer level packaging unit, which comprises a carrier plate, at least one chip, a dielectric layer, at least one interconnection line and an outer protective layer; wherein each chip has a die, a plurality of chip interconnection lines, a chip dielectric layer, a plurality of chip pads, a chip first surface and a chip second surface, and each die can be electrically connected to the outside through the chip pads; wherein each interconnection line is formed by filling metal paste into at least one groove of the dielectric layer and then grinding the metal paste, and each interconnection line forms a pad in each opening of the outer protective layer; wherein each chip can be electrically connected to the outside through the pads around the chip area on the chip second surface, effectively solving the problem of high manufacturing cost and environmental pollution in the existing fan-out packaging technology in the production of various interconnection lines.
[0007] To achieve the above object, the utility model provides a fan -out wafer level package unit, this fan -out wafer level package unit includes a carrier plate, at least one chip, a dielectric layer, at least one lead -through circuit and a protective layer, wherein the carrier plate has a first surface and opposite second surface, wherein each chip has a bare chip, a plurality of chip lead -through circuit, a chip dielectric layer, a plurality of chip pads, a chip first surface and a chip second surface, wherein each chip is set on the carrier plate through the chip first surface, wherein each chip pad is set on the chip second surface, and the vertical chip area of chip second surface is defined as a chip area, wherein the bare chip has at least one pad, and the bare chip can be electrically connected to the outside through the at least one pad, the plurality of chip lead -through circuit and the plurality of chip pads, wherein the dielectric layer is set on the second surface of the carrier plate and covers each chip, and the dielectric layer has at least one groove extending horizontally, and each groove can expose the plurality of chip pads, wherein each lead -through circuit is composed of metal paste filled in each groove, and each lead -through circuit is electrically connected to the plurality of chip pads, wherein the protective layer is set on the dielectric layer and each lead -through circuit, and the protective layer has a plurality of openings, and at least one opening is located around the chip area on the chip second surface of the chip, wherein each lead -through circuit is exposed through each opening to form a pad in each opening, and each chip can be electrically connected to the outside through each chip pad, each lead -through circuit and each pad around the chip area on the chip second surface of the chip to form the fan -out wafer level package unit.
[0008] In a preferred embodiment of the utility model, each opening further has a bump, and each bump is arranged on each pad.
[0009] In a preferred embodiment of the utility model, each bump further has a tin ball.
[0010] In a preferred embodiment of the utility model, the fan -out wafer level package unit can be electrically connected to a printed circuit board (PCB) through each tin ball.
[0011] In a preferred embodiment of the present application, each of the chips is further made by a packaging technology of redistribution layer (RDL, Redistribution Layer); wherein each of the chip lead lines is further composed of a plurality of first lead lines and a plurality of second lead lines; wherein the chip dielectric layer is further composed of a first dielectric layer and a second dielectric layer; wherein each of the first lead lines is composed of metal paste filled in at least one groove of the first dielectric layer, and each of the first lead lines is electrically connected with each of the die pads of the bare dies; wherein each of the second lead lines is composed of metal paste filled in at least one groove of the second dielectric layer, and each of the second lead lines is electrically connected with each of the first lead lines.
[0012] In a preferred embodiment of the present application, the metal paste constituting each of the first lead lines comprises silver paste, nano-silver paste, copper paste or nano-copper paste; wherein the metal paste constituting each of the second lead lines comprises silver paste, nano-silver paste, copper paste or nano-copper paste.
[0013] In a preferred embodiment of the present application, the carrier plate comprises a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate.
[0014] In a preferred embodiment of the present application, the metal paste constituting each of the lead lines comprises silver paste, nano-silver paste, copper paste or nano-copper paste.
[0015] In a preferred embodiment of the present application, the first surface of each of the chips is further arranged on the second surface of the carrier plate by a die attach film (DAF, Die Attach Film). BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a plane schematic diagram of a side view section of an application embodiment of the fan-out wafer level packaging unit of the present application.
[0017] Figure 2 is a plane schematic diagram of a side view section of a carrier plate of the present application.
[0018] Figure 3 is a plane schematic diagram of a side view section of a carrier plate in Figure 2 arranged with a chip.
[0019] Figure 4 is a plane schematic diagram of a side view section of a carrier plate and a chip in Figure 3 arranged with a dielectric layer.
[0020] Figure 5 is a plane schematic diagram of a side view section of a groove in Figure 4 filled with metal paste.
[0021] Figure 6 is a plan view of a side sectional view of the metal paste in the Figure 5 being grinded to form a side sectional view of a first via.
[0022] Figure 7 is a plan view of a side sectional view of the first via in the Figure 6 being coated with a first dielectric layer.
[0023] Figure 8 is a plan view of a side sectional view of the first dielectric layer in the Figure 7 being coated with a first metal paste.
[0024] Figure 9 is a plan view of a side sectional view of the first metal paste in the Figure 8 being grinded to form a first via.
[0025] Figure 10 is a plan view of a side sectional view of the chip of the present application.
[0026] Figure 11 is a plan view of a side sectional view of the bare die in the chip of the present application.
[0027] Figure 12 is a plan view of a side sectional view of the bare die in the Figure 11 being coated with a first dielectric layer.
[0028] Figure 13 is a plan view of a side sectional view of the first dielectric layer in the Figure 12 being coated with a first metal paste.
[0029] Figure 14 is a plan view of a side sectional view of the first metal paste in the Figure 13 being grinded to form a first via.
[0030] Figure 15 is a plan view of a side sectional view of the first dielectric layer in the Figure 14 being coated with a second dielectric layer.
[0031] Figure 16 is a plan view of a side sectional view of the second dielectric layer in the Figure 15 being coated with a first metal paste.
[0032] Explanation of the accompanying reference numerals: 1-fan-out wafer-level packaging unit; 1a-chip area; 10-carrier; 11-first side; 12-second side; 20-chip; 21-bare die; 211-crystal pad; 22-chip conductive line; 221-first conductive line; 221a-metal paste; 222-second conductive line; 222a-metal paste; 23-chip dielectric layer; 231-first dielectric layer; 2311-groove; 232-second dielectric layer; 2321-groove; 24-chip bonding pad; 25-chip first side; 26-chip second side; 30-dielectric layer; 31-groove; 40-conductive line; 40a-metal paste; 41-bonding pad; 50-outer protective layer; 51-opening; 60-bump; 70-solder ball; 80-chip bonding film; 2-printed circuit board. DETAILED DESCRIPTION
[0033] The structure and technical features of the present invention are described in detail below with reference to the accompanying drawings. Each drawing is only used to illustrate the structural relationship and related functions of the present invention. Therefore, the size of each component in each drawing is not drawn according to the actual scale and is not intended to limit the present invention.
[0034] refer to Figure 1 The present invention provides a fan-out wafer-level packaging unit 1 , which includes a carrier 10 , at least one chip 20 , a dielectric layer 30 , at least one conductive circuit 40 and an outer protective layer 50 .
[0035] The carrier board 10 has a first surface 11 and an opposite second surface 12. Figure 2 shown.
[0036] Each chip 20 comprises a die 21, a plurality of chip conducting lines 22, a chip dielectric layer 23, a plurality of chip bonding pads 24, a chip first surface 25 and a chip second surface 26. Figure 3 wherein each chip 20 is disposed on the carrier 10 via the first surface 25 of the chip, as shown Figure 3 wherein each chip pad 24 is disposed on the second surface 26 of the chip, and the vertical chip region of the second surface 26 of the chip is defined as a chip region 1a, such as Figure 3 wherein the bare die 21 has at least one crystal pad 211, each bare die 21 is able to sequentially connect to the external electrical connection via each crystal pad 211, each chip conductive line 22 and each chip bonding pad 24, such as Figure 3 shown.
[0037] The dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and covers each chip 20. The dielectric layer 30 has at least one groove 31 extending horizontally. Each groove 31 is configured to allow each chip pad 24 to be exposed to the outside. Figure 4 shown.
[0038] Each of the conductive lines 40 is formed by a metal paste 40a filled in each of the grooves 31, as shown in FIG. 4; wherein each of the conductive lines 40 is electrically connected with each of the chip pads 24, as shown in FIG. 4. Figure 6 Figure 6
[0039] The outer protective layer 50 is disposed on the dielectric layer 30 and each of the conductive lines 40, the outer protective layer 50 has a plurality of openings 51 and at least one of the openings 51 is located around the chip region 1a on the chip second surface 26 of the chip 20, as shown in FIG. 5; wherein each of the conductive lines 40 is exposed by each of the openings 51 to form a pad 41 in each of the openings 51, as shown in FIG. 5. In the embodiment shown in FIG. 5, the fan-out wafer level package unit 1 has five pads 41, but this is not used to limit the present application. Figure 7 Figure 7 Figure 7
[0040] Each of the chips 20 can be electrically connected externally in sequence through each of the chip pads 24, each of the conductive lines 40 and each of the pads 41 located around the chip region 1a on the chip second surface 26 of the chip 20, so as to form the fan-out wafer level package unit 1, as shown in FIG. 6. Figure 7
[0041] The process of manufacturing the fan-out wafer level package unit 1 can include the following steps, but is not limited thereto:
[0042] Step S1: providing a carrier plate 10, as shown in FIG. 7; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12, as shown in FIG. 7. Figure 2 Figure 2 Step S2: spacing a plurality of chips 20 on the second surface 12 of the carrier plate 10, as shown in FIG. 8; wherein each of the chips 20 has a die 21, a chip conductive line 22, a chip dielectric layer 23, a plurality of chip pads 24, a chip first surface 25 and a chip second surface 26, as shown in FIG. 8; wherein each of the chips 20 is disposed on the carrier plate 10 through the chip first surface 25, as shown in FIG. 8; wherein each of the chip pads 24 is disposed on the chip second surface 26, and the vertical chip region of the chip second surface 26 is defined as a chip region 1a, as shown in FIG. 8; wherein the die 21 has at least one die pad 211, and each of the dies 21 can be electrically connected externally in sequence through each of the die pads 211, the chip conductive line 22 and each of the chip pads 24, as shown in FIG. 8.
[0043] Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
[0044] Step S3: disposing a dielectric layer 30 on the second surface 12 of the carrier 10 and covering the dies 20 with the dielectric layer 30, as shown in Figure 4 ; wherein the dielectric layer 30 has at least one groove 31 formed horizontally, and each groove 31 is capable of exposing the die pad 24, as shown in Figure 4 .
[0045] Step S4: filling the metal paste 40a into each groove 31 of the dielectric layer 30, and the thickness of the metal paste 40a is higher than the surface of the dielectric layer 30, as shown in Figure 5 .
[0046] Step S5: grinding the metal paste 40a higher than the surface of the dielectric layer 30 to make the surface of the metal paste 40a flush with the surface of the dielectric layer 30 to form a plurality of conductive lines 40, as shown in Figure 6 .
[0047] Step S6: disposing an outer protective layer 50 on the dielectric layer 30, as shown in Figure 7 .
[0048] Step S7: forming a plurality of openings 51 in the outer protective layer 50, and at least one of the openings 51 is formed around the die region 1a on the second surface 22 of each die 20, so that each conductive line 40 can be exposed outside through each opening 51 to form a solder pad 41 in each opening 51, as shown in Figure 7 .
[0049] Step S8: performing a separation operation to separate a plurality of fan-out wafer level packaging units 1, as shown in Figure 7 .
[0050] The processes of steps S3 to S5 in the process of manufacturing the above-mentioned fan-out wafer level packaging unit 1 can be regarded as the key steps of making the redistribution layer (RDL) of the fan-out wafer level packaging unit 1, wherein step S3 is to dispose a dielectric layer 30 on the second surface 12 of the carrier 10 and make the dielectric layer 30 have at least one groove 31 formed horizontally, step S4 is to fill the metal paste 40a into each groove 31 of the dielectric layer 30, and step S5 is to make the surface of the metal paste 40a flush with the surface of the dielectric layer 30 to form a plurality of conductive lines 40. Since steps S3 to S5 are all easy-to-precisely-implement processes, the processes are relatively simple, and each conductive line in the redistribution layer (RDL) can be in the state of XY plane electrical extension and interconnection, and at the same time, the finished fan-out wafer level packaging unit 1 can still maintain or achieve a certain degree of lightness, thinness and smallness.
[0051] Referring to Figure 8 Further, each opening 51 has a bump 60, but not limited, and each bump 60 is disposed on each pad 41, which is advantageous to protect the pad and increase the yield of the product.
[0052] Referring to Figure 9 Further, each bump 60 has a solder ball 70, but not limited.
[0053] Referring to Figure 1 The fan-out wafer level package unit 1 can be disposed on a printed circuit board (PCB) 2 by using each solder ball 70, but not limited, which is advantageous to increase the versatility of the product.
[0054] Referring to Figure 10 Further, each chip 20 is made by using a redistribution layer (RDL) packaging technology, but not limited, and is not made by using the existing plating or electroplating technology, which can reduce the cost and pollution caused by the process; wherein each chip via line 22 is further composed of a plurality of first via lines 221 and a plurality of second via lines 222, as shown in Figure 10 ; wherein the chip dielectric layer 23 is further composed of a first dielectric layer 231 and a second dielectric layer 232, as shown in Figure 10 ; wherein each first via line 221 is composed of a metal paste 221a filled in at least one recess 2311 of the first dielectric layer 231, and each first via line 221 is electrically connected to each pad 211 of the die 21, as shown in Figure 10 ; wherein each second via line 222 is composed of a metal paste 222a filled in at least one recess 2321 of the second dielectric layer 232, and each second via line 222 is electrically connected to each first via line 221, as shown in Figure 10 .
[0055] The following steps can be used to manufacture each chip 20, but not limited:
[0056] Step S11: providing a wafer 3 having a plurality of dies 21, as shown in Figure 11 ; wherein each die 21 has at least one pad 211, as shown in Figure 11 .
[0057] Step S12: laying a first dielectric layer 231 on each die 21, and forming at least one recess 2311 on the first dielectric layer 231, as shown in Figure 12 .
[0058] Step S13: filling metal paste 221a into each recess 2311 of the first dielectric layer 231, and the thickness of the metal paste 221a is higher than the surface of the first dielectric layer 231, as shown in Figure 13 .
[0059] Step S14: grinding the metal paste 221a which is higher than the surface of the first dielectric layer 231, so that the surface of the metal paste 221a is flush with the surface of the first dielectric layer 231 to form a plurality of first conductive lines 221, as shown in Figure 14 . Figure 14
[0060] Step S15: laying a second dielectric layer 232 on the first dielectric layer 231, and forming at least one recess 2321 on the second dielectric layer 232, as shown in Figure 15 .
[0061] Step S16: filling metal paste 222a into each recess 2321 of the second dielectric layer 232, and the thickness of the metal paste 222a is higher than the surface of the second dielectric layer 232, as shown in Figure 16 .
[0062] Step S17: grinding the metal paste 222a which is higher than the surface of the second dielectric layer 232, so that the surface of the metal paste 222a is flush with the surface of the second dielectric layer 232 to form a plurality of second conductive lines 222, as shown in Figure 10 . Figure 10
[0063] Step S18: performing a separation operation to separate the wafer 3 to form a plurality of chips 20, as shown in Figure 10 . Figure 10 Figure 10
[0064] Referring to Figure 10 , the metal paste 221a constituting each first conductive line 221 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity and low-temperature sintering, but since the nano-silver paste material is a common material, further description is omitted.
[0065] Referring to Figure 10 The metal paste 222a constituting each second via line 222 comprises silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited.
[0066] Referring to Figure 2 The carrier plate 10 comprises a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate, but is not limited, so as to increase the diversity of products.
[0067] Referring to Figure 6 The metal paste 40a constituting each via line 40 comprises silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited.
[0068] Referring to Figure 3 The first face 25 of each chip 20 is further disposed on the second face 12 of the carrier plate 10 by a die attach film (DAF) 80, but is not limited.
[0069] Compared with the prior fan-out wafer level packaging unit, the fan-out wafer level packaging unit 1 has the following advantages:
[0070] (1) The fan-out wafer level packaging unit 1 of the utility model can be manufactured through the above-mentioned steps S3 to S5. Compared with the related manufacturing technology of the prior fan-out wafer level packaging unit, the fan-out wafer level packaging unit 1 of the utility model can make each via line in the RDL in the state of XY plane electrical extension and interconnection, and also can maintain or achieve a certain degree of lightness, thinness and smallness. The process is simple and easy to implement, especially beneficial to reducing the thickness of the packaging unit. Therefore, the process of manufacturing the utility model is not only simple and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer level packaging unit 1.
[0071] (2) The steps S3 to S5 of manufacturing the fan-out wafer level packaging unit 1 of the utility model are all technologies of filling metal paste into grooves and then grinding and forming via lines to form multiple via lines on the dielectric layer, rather than using the plating or electroplating technology adopted by the prior fan-out wafer level packaging unit. The technology can reduce the cost and pollution generated in the process, so that the manufacturing of the utility model can effectively solve the problem of high manufacturing cost and environmental pollution in the process of manufacturing via lines by the fan-out packaging technology adopted by the prior fan-out wafer level packaging unit.
[0072] (3) the fan-out wafer level packaging unit 1 in the utility model further can be made by RDL technology, can effectively solve the problem that the existing fan-out wafer level packaging unit's technology is designed for bare die (Die), and lacks the design for chip (the segmentation of the bare die on wafer after RDL is completed), and it is favorable to increase the diversity of product.
[0073] The above is only the preferred embodiment of the utility model, which is only illustrative but not restrictive for the utility model; the ordinary skilled in the art understands that many changes, modifications or even equivalent changes can be made within the spirit and range defined by the utility model claims, but all will fall within the protection scope of the utility model.
Claims
1. A fan-out wafer level package unit, characterized by, Comprising: a carrier plate having a first surface and an opposite second surface; at least one chip, each of the chip having a die, a plurality of chip conductive lines, a chip dielectric layer, a plurality of chip pads, a chip first surface and a chip second surface; wherein each of the chip is disposed on the carrier plate through the chip first surface; wherein each of the chip pad is disposed on the chip second surface, and a vertical chip region of the chip second surface is defined as a chip region; wherein the die has at least one die pad, and each of the die is capable of being electrically connected to the outside sequentially through the at least one die pad, the plurality of chip conductive lines and the plurality of chip pads; a dielectric layer disposed on the second surface of the carrier plate and covering each of the chip, the dielectric layer having at least one groove formed in a horizontal direction, each of the groove is capable of exposing the plurality of chip pads to the outside; at least one conductive line, each of the conductive line is composed of metal paste filled in each of the groove; wherein each of the conductive line is electrically connected to the plurality of chip pads; and an outer protective layer disposed on the dielectric layer and each of the conductive line, the outer protective layer has a plurality of openings and at least one of the openings is located around the chip region on the chip second surface of the chip; wherein each of the conductive line is exposed to the outside through the plurality of openings to form a pad in each of the opening; wherein each of the chip is capable of being electrically connected to the outside sequentially through the plurality of chip pads, the at least one conductive line and the plurality of pads located around the chip region on the chip second surface of the chip, thereby forming the fan-out wafer level package unit.
2. The fan-out wafer level package unit of claim 1, wherein, Each of the opening further has a bump, and each of the bump is disposed on each of the pad.
3. The fan-out wafer level packaging unit of claim 2, wherein, Each of the bump further has a solder ball.
4. The fan-out wafer level packaging unit of claim 3, wherein, The fan-out wafer level package unit is capable of being electrically connected to a printed circuit board through each of the solder ball.
5. The fan-out wafer level packaging unit of claim 1, wherein, Each of the chip is made by a redistribution layer packaging technology; wherein each of the chip conductive line is composed of a plurality of first conductive lines and a plurality of second conductive lines; wherein the chip dielectric layer is composed of a first dielectric layer and a second dielectric layer; wherein each of the first conductive line is composed of metal paste filled in at least one groove of the first dielectric layer, and each of the first conductive line is electrically connected to each of the die pad of the die; wherein each of the second conductive line is composed of metal paste filled in at least one groove of the second dielectric layer, and each of the second conductive line is electrically connected to each of the first conductive line.
6. The fan-out wafer level packaging unit of claim 5, wherein, The metal paste composing each of the first conductive line includes silver paste, nano-silver paste, copper paste or nano-copper paste; wherein the metal paste composing each of the second conductive line includes silver paste, nano-silver paste, copper paste or nano-copper paste.
7. The fan-out wafer level packaging unit of claim 1, wherein, The carrier plate includes a silicon carrier plate, a glass carrier plate or a ceramic carrier plate.
8. The fan-out wafer level package unit of claim 1, wherein, The metal paste composing each of the conductive line includes silver paste, nano-silver paste, copper paste or nano-copper paste.
9. The fan-out wafer level package unit of claim 1, wherein, The chip first surface of each of the chip is disposed on the second surface of the carrier plate through a chip adhesive film.