Efficient trigger logic circuit based on feedback control mechanism

Abstract

The utility model relates to an efficient trigger logic circuit based on a feedback control mechanism, belongs to the technical field of trigger logic circuits, and solves the problem of lack of self-calibration and feedback regulation in the prior art. Comprising a logic arithmetic unit, a trigger logic device and a feedback and self-calibrator, wherein the logic arithmetic unit is used for performing logic operation on an input signal to obtain a logic operation result signal; the two input ends of the trigger logic device input the logic operation result signal and the feedback control signal output by the feedback and self-calibration circuit respectively, and the output end outputs a trigger signal through logic judgment; the feedback and self-calibration device is used for generating a feedback control signal based on the trigger signal and comprises a comparator and a self-calibration chip; the non-inverting input end of the comparator inputs a device power supply, the inverting input end of the comparator inputs the trigger signal, and the output end of the comparator is connected with the input end of the self-calibration chip; and the output end of the self-calibration chip outputs a feedback control signal. The trigger logic circuit with self-calibration and feedback regulation functions is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to trigger logic circuit technical field especially relates to a high -efficient trigger logic circuit based on feedback control mechanism. BACKGROUND

[0002] In modern electronic system, especially in industrial control, automotive electronics and communication system, the detection and processing of input signal is an important link to guarantee the timing accuracy of system. The traditional trigger logic module, such as commonly used 74LS00 integrated circuit, although can realize basic logic judgment function, but has great limitation in self-calibration and feedback regulation, cannot satisfy the requirement of high precision, real-time feedback.

[0003] In order to improve the overall performance of system, modern equipment gradually adopts logic processing circuit with feedback control function to dynamically adjust the logic output of system. However, there lacks a trigger logic circuit which can effectively combine feedback self-calibration and logic control in prior art. The existing optical coupling detection module, such as TLP2355, also has limitation, and cannot satisfy the requirement of rapid response and real-time regulation in feedback mechanism. SUMMARY

[0004] In view of the above analysis, the utility model aims at providing a kind of high -efficient trigger logic circuit based on feedback control mechanism to solve the problem that existing trigger logic circuit lacks self-calibration and feedback regulation function.

[0005] The utility model mainly aims at realizing the following technical scheme including logic operator, trigger logic ware and feedback and self-calibrator;Among them,

[0006] The logic operator obtains logic operation result signal by logic operation to input signal;

[0007] The trigger logic ware, two input ends respectively input logic operation result signal and feedback control signal output by feedback and self-calibrator, and output trigger signal by logic judgment in output end;

[0008] The feedback and self-calibrator are used to generate feedback control signal based on the trigger signal, and include comparator and self-calibration chip;Wherein, the same phase input end of comparator inputs device power supply, and opposite phase input end inputs trigger signal, and output end is connected with the input end of self-calibration chip;The output end of self-calibration chip outputs feedback control signal.

[0009] Further improvement based on the above scheme also includes signal preprocessor;

[0010] The signal preprocessor comprises multiple sets of filter circuits; multiple original input signals are input into corresponding filter circuits respectively, and the output ends of the filter circuits output filtered input signals to the input ends of the logic operator.

[0011] Based on the further improvement of the above scheme, the filter circuit is an RC filter circuit.

[0012] Based on the further improvement of the above scheme, the logic operator comprises an AND gate 74HC08, an XOR gate 74HC86 and an OR gate 74HC32; wherein,

[0013] The two input ends of the AND gate 74HC08 and the two input ends of the XOR gate 74HC86 are connected to different input signals respectively; the output end of the AND gate 74HC08 is connected to one input end of the OR gate 74HC32; the output end of the XOR gate 74HC86 is connected to the other input end of the OR gate 74HC32; and the output end of the OR gate 74HC32 outputs a logic operation result signal.

[0014] Based on the further improvement of the above scheme, the logic operator comprises a first AND gate 74HC08, a second AND gate 74HC08, a third AND gate 74HC08, a fourth AND gate 74HC08, a first XOR gate 74HC86, a second XOR gate 74HC86, a third XOR gate 74HC86, a first OR gate 74HC32, a second OR gate 74HC32, a third OR gate 74HC32 and a fourth OR gate 74HC32; wherein,

[0015] The input ends of the first AND gate 74HC08 are connected to a first input signal and a second input signal, and the output end is connected to one input end of the second AND gate 74HC08; the other input end of the second AND gate 74HC08 is connected to a third input signal, and the output end is connected to one input end of the first OR gate 74HC32; the input ends of the third AND gate 74HC08 are connected to a fourth input signal and a fifth input signal, and the output end is connected to one input end of the fourth AND gate 74HC08; the other input end of the fourth AND gate 74HC08 is connected to a sixth input signal, and the output end is connected to the other input end of the first OR gate 74HC32; and the output end of the first OR gate 74HC32 is connected to one input end of the third OR gate 74HC32.

[0016] The input end of the first exclusive-OR gate 74HC86 is connected with the first input signal and the fourth input signal, and the output end is connected with one input end of the second OR gate 74HC32; the input end of the second exclusive-OR gate 74HC86 is connected with the second input signal and the fifth input signal, and the output end is connected with the other input end of the second OR gate 74HC32; the input end of the third exclusive-OR gate 74HC86 is connected with the third input signal and the sixth input signal, and the output end is connected with the other input end of the third OR gate 74HC32; the output end of the second OR gate 74HC32 is connected with one input end of the fourth OR gate 74HC32;

[0017] The output end of the third OR gate 74HC32 is connected with the other input end of the fourth OR gate 74HC32, and the output end of the fourth OR gate 74HC32 outputs the logic operation result signal.

[0018] Based on the further improvement of the above scheme, the trigger logic is an NAND gate 74HC00.

[0019] Based on the further improvement of the above scheme, the comparator comprises a chip LM393.

[0020] The 1 pin of the chip LM393 is an output end, the 2 pin is an inverse input end, and the 3 pin is a same-phase input end.

[0021] Based on the further improvement of the above scheme, the self-calibration chip comprises a chip MAX14745.

[0022] The B3 pin of the chip MAX14745 is an input end, and the D2 pin is an output end.

[0023] Compared with the prior art, the utility model at least can realize following beneficial effect one:

[0024] 1、Circuit has self -adaptation and feedback regulation function, through the adjustment of feedback control signal, the trigger signal of circuit output can with the change of input signal and self -calibration mechanism carries out dynamic adjustment, ensures that the output signal has high precision and high reliability;

[0025] 2、Adopt the logic operation of hardware level, make signal processing not depend on software, therefore avoid the delay of program execution and the complexity of interruption processing, reduce the power consumption simultaneously;

[0026] In the utility model, the above-mentioned each technical scheme can also be combined with each other to realize more preferred combination scheme.The other features and advantages of the utility model will be described in the following content, and part of the advantages can become apparent from the description, or be understood by implementing the utility model.The purpose and other advantages of the utility model can be realized and obtained by the content specially pointed out in the text and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the description serve to explain the principles of the present application, and should not be taken as limiting the present application in its scope.

[0028] Figure 1 A high-efficiency trigger logic circuit based on a feedback control mechanism is disclosed in one of the embodiments of the present application.

[0029] Figure 2 A high-efficiency trigger logic circuit based on a feedback control mechanism is disclosed in another embodiment of the present application.

[0030] Reference signs:

[0031] 1 - signal preprocessor; 2 - logic operator; 3 - trigger logic; 4 - feedback and self-calibration device DETAILED DESCRIPTION

[0032] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, which form a part of this application. The accompanying drawings together with the description serve to explain the principles of the present application, and should not be considered as limiting the scope of the present application.

[0033] One of the embodiments of the present application discloses a high-efficiency trigger logic circuit based on a feedback control mechanism, as shown in the figure, comprising: a logic operator 2, a trigger logic 3 and a feedback and self-calibration device 4; wherein, Figure 1

[0034] The logic operator obtains a logic operation result signal by logically operating on an input signal.

[0035] The trigger logic has two input ends respectively inputting the logic operation result signal and the feedback control signal output by the feedback and self-calibration device, and outputs a trigger signal at the output end after logical judgment.

[0036] The feedback and self-calibration device is used to generate a feedback control signal based on the trigger signal, and comprises a comparator and a self-calibration chip; wherein, the same-phase input end of the comparator inputs a device power supply, the opposite-phase input end inputs the trigger signal, and the output end is connected to the input end of the self-calibration chip; the output end of the self-calibration chip outputs the feedback control signal.

[0037] ​Further, the embodiment further comprises a signal preprocessor 1; the signal preprocessor comprises a plurality of sets of filter circuits; a plurality of original input signals are input into corresponding filter circuits respectively, and the output ends of the filter circuits output filtered input signals to the input ends of a logic operator.

[0038] In a possible implementation, the logic operator comprises an AND gate 74HC08, an XOR gate 74HC86, and an OR gate 74HC32; wherein,

[0039] The two input ends of the AND gate 74HC08 and the two input ends of the XOR gate 74HC86 are respectively connected to different input signals; the output end of the AND gate 74HC08 is connected to one input end of the OR gate 74HC32; the output end of the XOR gate 74HC86 is connected to the other input end of the OR gate 74HC32; and the output end of the OR gate 74HC32 outputs a logic operation result signal.

[0040] Specifically, the AND gate 74HC08 is used to make consistency judgment of two input signals, the XOR gate 74HC86 is used to make exclusivity judgment of two input signals, and the OR gate 74HC32 is used to make parallel condition judgment of two input signals. Through corresponding logic judgment of the input signals by the logic operator, when the judgment condition is met, a trigger signal is triggered and output by the logic operator as a starting signal of other devices. The other devices can be an external display module, a driving circuit, or other devices that need to be controlled.

[0041] It is worth noting that the trigger logic operator is an NAND gate 74HC00 instead of a conventional 74LS00, so as to enhance the flexibility and speed of logic judgment.

[0042] Specifically, the comparator in the feedback and self-calibrator comprises a chip LM393; the 1 pin of the chip LM393 is an output terminal, the 2 pin is an inverting input terminal, and the 3 pin is a non-inverting input terminal. In addition, the self-calibration chip in the feedback and self-calibrator comprises a chip MAX14745; the B3 pin of the chip MAX14745 is an input terminal, and the D2 pin is an output terminal. When the comparator detects that the voltage level of the trigger signal is abnormal, such as exceeding the power supply voltage, the output terminal of the comparator changes in state, indicating that an abnormality is detected, and is transmitted to the self-calibration chip; after the self-calibration chip receives the indication signal, self-calibration is realized by adjusting the internal compensation capacitor, reference voltage or bias current of the chip, and a feedback control signal is output, so as to compensate for the abnormality of the input signal of the trigger logic device caused by interference and ensure the correctness of the logic judgment; after feedback adjustment, the output of the trigger logic device restores to the correct logic level, ensuring the normal function of the system.

[0043] Specifically, the comparator and the self-calibration chip complement each other and can together realize more accurate system adjustment. The self-calibration chip itself has an automatic adjustment function and can optimize the time response of the system by adjusting the internal capacitor of the chip in different working environments; the comparator is used for monitoring the trigger signal in real time, comparing the trigger signal with the reference power supply voltage, and triggering the self-calibration mechanism; through the feedback of the comparator, the self-calibration chip adjusts the delay or distortion in the signal path by adjusting the internal compensation capacitor, reference voltage or bias current of the chip to ensure high-precision processing of the signal. The feedback control signal output by the feedback and self-calibrator is input to the trigger logic device to form a closed-loop control, so as to dynamically adjust the logic output of the system and ensure more flexible and accurate logic judgment and signal processing.

[0044] Another specific embodiment of the utility model discloses a kind of efficient trigger logic circuit based on feedback control mechanism, as shown in Figure 2 As shown in

[0045] The circuit includes six original input signals, and its logic operator includes first AND gate 74HC08, second AND gate 74HC08, third AND gate 74HC08, fourth AND gate 74HC08, first XOR gate 74HC86, second XOR gate 74HC86, third XOR gate 74HC86, first OR gate 74HC32, second OR gate 74HC32, third OR gate 74HC32, fourth OR gate 74HC32; wherein,

[0046] The input end of the first AND gate 74HC08 is connected with the first input signal and the second input signal, and the output end is connected with one input end of the second AND gate 74HC08; the other input end of the second AND gate 74HC08 is connected with the third input signal, and the output end is connected with one input end of the first OR gate 74HC32; the input end of the third AND gate 74HC08 is connected with the fourth input signal and the fifth input signal, and the output end is connected with one input end of the fourth AND gate 74HC08; the other input end of the fourth AND gate 74HC08 is connected with the sixth input signal, and the output end is connected with the other input end of the first OR gate 74HC32; the output end of the first OR gate 74HC32 is connected with one input end of the third OR gate 74HC32;

[0047] The input end of the first XOR gate 74HC86 is connected with the first input signal and the fourth input signal, and the output end is connected with one input end of the second OR gate 74HC32; the input end of the second XOR gate 74HC86 is connected with the second input signal and the fifth input signal, and the output end is connected with the other input end of the second OR gate 74HC32; the input end of the third XOR gate 74HC86 is connected with the third input signal and the sixth input signal, and the output end is connected with the other input end of the third OR gate 74HC32; the output end of the second OR gate 74HC32 is connected with one input end of the fourth OR gate 74HC32;

[0048] The output end of the third OR gate 74HC32 is connected with the other input end of the fourth OR gate 74HC32, and the output end of the fourth OR gate 74HC32 outputs the logic operation result signal.

[0049] Exemplarily, the six original input signals IN1-IN6 correspond to the time stamps of the six devices, and the logic processor is used to judge whether the synchronization requirements among the devices are met. IN1 and IN2 represent the network synchronization signals, which are sent by the sensors and control modules of the devices, and represent the clock state inside the system; IN3 and IN4 represent the external GPS clock or satellite signal, which is used as the external reference clock source; IN5 and IN6 represent the state signals of the network system, wherein IN5 represents whether the system has completed synchronization last time, and IN6 represents whether there is an error or conflict in the clock at present; in combination, in the synchronization starting state, if the IN1-IN4 signals are relatively synchronized, and IN5 represents that the synchronization has been completed and IN6 has no error, the trigger signal is output, indicating that the synchronization is completed; when entering the clock detection state, if IN1-IN4 does not meet the synchronization requirements, or IN6 detects the clock conflict or deviation, the trigger signal is output, indicating that the calibration is started; when reaching the specified time, if IN5 shows that the synchronization is not completed, or IN6 represents that there is a clock conflict, the trigger signal is output, indicating that the system enters the error processing state.

[0050] The structure and connection relationship of other circuit parts of the embodiment are the same as those of the previous embodiment.

[0051] Compared with the prior art, the trigger logic circuit provided by the embodiment has self-adaption and feedback adjustment functions, through adjustment of the feedback control signal, the trigger signal output by the circuit can be dynamically adjusted along with the change of the input signal and the self-calibration mechanism, ensuring that the output signal has high precision and high reliability; in addition, compared with the traditional microprocessor control scheme which usually involves complex software control and interrupt processing and introduces higher delay, the embodiment adopts hardware-level logic operation, so that the signal processing is independent of software, thus avoiding the delay of program execution and the complexity of interrupt processing, and reducing power consumption.

[0052] Those skilled in the art can understand that the utility model only needs to connect various devices with corresponding functions through the connection relationship given in the embodiment of the utility model, and does not involve any improvement in program software. As for the connection mode between various hardware devices with corresponding functions, it can be realized by using the prior art, and detailed description is not given here.

[0053] The above is only the preferred specific implementation of the utility model, but the protection scope of the utility model is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the utility model, which should be covered in the protection scope of the utility model.

Claims

1. An efficient trigger logic circuit based on a feedback control mechanism, characterized by, Logic operator, trigger logic and feedback and self-calibrator are included; wherein, The logic operator, logic operation result signal is obtained by logic operation on input signal; The trigger logic, two input terminals input the logic operation result signal and the feedback control signal output by the feedback and self-calibrator respectively, and the output terminal outputs the trigger signal after logic judgment; The feedback and self-calibrator is used for generating feedback control signal based on the trigger signal, including comparator and self-calibration chip; wherein, the same phase input terminal of the comparator inputs device power supply, the opposite phase input terminal inputs the trigger signal, and the output terminal is connected with the input terminal of the self-calibration chip; the output terminal of the self-calibration chip outputs the feedback control signal.

2. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, It also includes signal preprocessor; The signal preprocessor includes multiple sets of filter circuits; multiple original input signals are input into corresponding filter circuits respectively, and the output terminal of the filter circuit outputs the filtered input signal to the input terminal of the logic operator.

3. The efficient flip-flop based on feedback control mechanism as claimed in claim 2, wherein, The filter circuit is RC filter circuit.

4. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, The logic operator includes AND gate 74HC08, XOR gate 74HC86 and OR gate 74HC32; wherein, The two input terminals of the AND gate 74HC08 and the two input terminals of the XOR gate 74HC86 are connected with different input signals respectively; the output terminal of the AND gate 74HC08 is connected with one input terminal of the OR gate 74HC32; the output terminal of the XOR gate 74HC86 is connected with another input terminal of the OR gate 74HC32; the output terminal of the OR gate 74HC32 outputs the logic operation result signal.

5. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, The logic operator includes first AND gate 74HC08, second AND gate 74HC08, third AND gate 74HC08, fourth AND gate 74HC08, first XOR gate 74HC86, second XOR gate 74HC86, third XOR gate 74HC86, first OR gate 74HC32, second OR gate 74HC32, third OR gate 74HC32 and fourth OR gate 74HC32; wherein, The input terminal of the first AND gate 74HC08 is connected with first input signal and second input signal, and the output terminal is connected with one input terminal of the second AND gate 74HC08; the other input terminal of the second AND gate 74HC08 is connected with third input signal, and the output terminal is connected with one input terminal of the first OR gate 74HC32; the input terminal of the third AND gate 74HC08 is connected with fourth input signal and fifth input signal, and the output terminal is connected with one input terminal of the fourth AND gate 74HC08; the other input terminal of the fourth AND gate 74HC08 is connected with sixth input signal, and the output terminal is connected with another input terminal of the first OR gate 74HC32; the output terminal of the first OR gate 74HC32 is connected with one input terminal of the third OR gate 74HC32; An input end of a first exclusive-OR gate 74HC86 is connected with the first input signal and the fourth input signal, and an output end of the first exclusive-OR gate 74HC86 is connected with one input end of a second OR gate 74HC32; an input end of a second exclusive-OR gate 74HC86 is connected with the second input signal and the fifth input signal, and an output end of the second exclusive-OR gate 74HC86 is connected with another input end of the second OR gate 74HC32; an input end of a third exclusive-OR gate 74HC86 is connected with the third input signal and the sixth input signal, and an output end of the third exclusive-OR gate 74HC86 is connected with another input end of a third OR gate 74HC32; an output end of the second OR gate 74HC32 is connected with one input end of a fourth OR gate 74HC32; An output end of the third OR gate 74HC32 is connected with another input end of the fourth OR gate 74HC32, and an output end of the fourth OR gate 74HC32 outputs the logic operation result signal.

6. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, The trigger logic is a NAND gate 74HC00.

7. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, The comparator comprises a chip LM393; A 1 pin of the chip LM393 is an output end, a 2 pin is an inverting input end, and a 3 pin is a non-inverting input end.

8. The efficient flip-flop based on feedback control mechanism as claimed in claim 1, wherein, The self-calibration chip comprises a chip MAX14745; A B3 pin of the chip MAX14745 is an input end, and a D2 pin is an output end.

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