Anti-interference test board
Through the main and auxiliary board structures and test circuit design, the problem of misjudgment of defective products caused by CS pin interference in the Toff-power off test of the switch chip is solved, efficient signal isolation and accurate test results are achieved, and production costs are reduced.
Patent Information
- Application Number
- CN202422678576.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-11-04
AI Technical Summary
During the Toff-power-off test, the switch chip is easily affected by the high voltage interference near the CS pin, which can lead to misjudgment of the DRAIN pin output waveform, causing good products to be mistakenly judged as defective.
An anti-interference test board is designed. The main and auxiliary board structures are used to make the positions of the gold finger PADs independent. A test circuit composed of multiple relays and operational amplifiers is used to reduce signal interference. In particular, the CS pin is located on the outer edge of the auxiliary board, and a relay is provided at the boundary between the main and auxiliary boards to shorten the grounding distance and enhance signal isolation.
It significantly reduces the signal interference of the pins of the chip to be tested, improves the yield rate, reduces the false positive rate of defective products, and reduces production costs.
Smart Images
Figure CN223486119U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to an anti-interference test board. Background Art
[0002] Before leaving the factory, switching chips need to undergo a Toff-power-off (turn-off time) test. According to the control commands of the testing machine, the switching chip switches between on and off to output a corresponding waveform. The turn-off performance of the chip is evaluated through this waveform. Internally, the current at the DRAIN pin flows back to GND via the CS pin, forming a loop. When there is high-voltage interference near the CS pin, a certain voltage may exist between the CS pin and ground, leading to errors in the output waveform of the DRAIN pin. This poses a risk of a good chip being mistakenly identified as a defective one. Therefore, when laying out the test circuit, the placement position corresponding to the CS pin should be avoided as much as possible from high-voltage signal lines. Utility Model Content
[0003] This utility model proposes an anti-interference test board, which aims to overcome the problem of misjudging defective products due to signal interference on the pins of the switching chip during the testing process. It adopts the following technical means:
[0004] An anti-interference test board includes a circuit board on which a test circuit is mounted. The circuit board has terminals for connecting to a host computer and gold finger PADs for pressing and contacting the chip under test. The circuit board includes a main board for mounting the test circuit and the terminals, and a secondary board extending from the edge of the main board for mounting the gold finger PADs. The gold finger PADs are connected to the test circuit via traces connecting the main board and the secondary board.
[0005] In one or more embodiments of the present invention, the test circuit includes a first relay, a second relay, a third relay, a fourth relay, a fifth relay, and a first operational amplifier;
[0006] The first relay connects the HV pin of the gold finger PAD to the OVI 1 pin of the terminal block, and is used to connect the first test voltage output by the host computer to the HV pin;
[0007] The second relay connects the DRAIN pin of the gold finger PAD to the OVI2 pin of the terminal block, and is used to connect the second test voltage output by the host computer to the DRAIN pin;
[0008] The third relay connects the CS pin of the gold finger PAD to the GND of the circuit board, and is used to control the host computer to ground the CS pin during testing. A filter capacitor is connected between the CS pin and the GND of the circuit board.
[0009] The fourth relay connects the DRAIN pin of the gold finger PAD to the non-inverting pin of the first operational amplifier, the fifth relay connects the OVI4 pin of the terminal block to the inverting pin of the first operational amplifier, and the output pin of the first operational amplifier is connected to the TMU1 pin of the terminal block to output a test signal to the tester.
[0010] In one or more embodiments of this utility model, the third relay is located at the junction of the main board and the sub-board.
[0011] In one or more embodiments of the present invention, the CS pin of the gold finger PAD is located on the outer edge of the sub-plate.
[0012] In one or more embodiments of the present invention, the test circuit further includes a sixth relay and a second operational amplifier; the sixth relay is connected to the non-inverting pin of the second operational amplifier and the CS pin of the gold finger PAD, the output pin of the second operational amplifier is connected to the OVI 3 pin of the terminal block, and the output pin is connected to the inverting pin.
[0013] In one or more embodiments of this utility model, the test circuit further includes an eighth relay, a ninth relay, a tenth relay, a first resistor, and a second resistor; one end of the eighth relay is connected to the CS pin of the gold finger PAD, and the other end is connected to GND via the first resistor; one end of the ninth relay is connected to the OVI 3 pin of the terminal block, and the other end is connected to the CS pin of the gold finger PAD via the second resistor; the tenth relay is connected in parallel across the two ends of the second resistor.
[0014] In one or more embodiments of this utility model, the test circuit further includes an eleventh relay, a twelfth relay, a thirteenth relay, a fourteenth relay, and a third resistor; the common terminal of the eleventh relay is connected to the DRAIN pin of the gold finger PAD via the twelfth relay, and the normally open and normally closed terminals of the eleventh relay are respectively connected to an inductor branch, with different inductance values for each inductor branch; the third resistor is connected in series with each inductor branch after parallel connection, and the thirteenth and fourteenth relays are respectively connected to the two ends of the third resistor to connect the OVI4 pin of the terminal block.
[0015] In one or more embodiments of the present invention, the test circuit further includes an indicator light, which is powered by connecting to pin OVI 1 of the terminal block via a fifteenth relay.
[0016] Compared with existing technologies, the advantages of this invention are as follows: The test circuit of this test board achieves circuit switching of the gold finger PAD under different test items through the on / off control of multiple relays, meeting the needs of multi-category testing. In particular, the main and sub-board design of this test board allows the position of the gold finger PAD to be relatively independent, so that the pins of the gold finger PAD can be far away from the high-voltage lines on the motherboard, significantly reducing the signal interference received by the pins of the chip under test. At the same time, considering the grounding travel of the CS pin and its sensitivity to high-voltage line interference, the CS pin of the gold finger PAD is set on the outer edge of the sub-board, as far away from the lines on the motherboard as possible, and the third relay for grounding the CS pin is placed at the junction of the motherboard and the sub-board, minimizing the grounding travel of the CS pin, making the grounding of the CS pin infinitely close to the real ground, thereby greatly reducing false judgments, improving yield, and indirectly reducing costs. Attached Figure Description
[0017] Figure 1 This is the schematic diagram of the test circuit.
[0018] Figure 2 Schematic diagram of a relay power supply circuit.
[0019] Figure 3 This is a pin definition diagram for the test machine.
[0020] Figure 4 This is a schematic diagram of the anti-interference test board.
[0021] Figure 5 This is a waveform diagram of the voltage at the DRAIN pin of the chip when subjected to high voltage interference.
[0022] Figure 6 This is the voltage waveform of the chip DRAI N pin detected under normal conditions (no high voltage interference).
[0023] Explanation of reference numerals in the attached diagram: The first relay is relay K1A; the second relays are relays K2A and K2B; the third relay is relay K6A; the fourth relay is relay K9A; the fifth relay is relay K9B; the sixth relay is relay K5A; the eighth relay is relay K12B; the ninth relay is relay K3A; the tenth relay is relay K4A; the eleventh relay is relay K14A; the twelfth relay is relay K12A; the thirteenth relay is relay K10A; the fourteenth relay is relay K11A; the fifteenth relay is relay K13A; the first resistor is resistor R8; the second resistor is resistor R... CS The third resistor is resistor R9, the first operational amplifier is operational amplifier U1, and the second operational amplifier is operational amplifier U2. Detailed Implementation
[0024] The following is in conjunction with the appendix Figures 1 to 6 The following is a further description of the proposed solution:
[0025] When performing Toff-power-off (turn-off time) tests on switching chips, high-voltage interference near the CS pin can easily cause a certain voltage to exist between the CS pin and ground, leading to errors in the output waveform of the DRAI N pin (as shown in the attached figure). Figure 5 As shown in the figure, there is a risk that good chips may be mistakenly identified as defective.
[0026] In response to this, the present invention has made targeted optimizations and designs, see appendix. Figures 1 to 4 The anti-interference test board includes a circuit board 1 housing a test circuit 2. The circuit board 1 has terminals 3 for connecting to a host computer and gold finger PADs (Kelvin soldered PADs) 4 for pressing and contacting the chip under test. The circuit board 1 includes a main board 11 for housing the test circuit 2 and terminals 3, and a secondary board 12 extending from the edge of the main board 11 for housing the gold finger PADs 4. The gold finger PADs 4 are connected to the test circuit 2 via traces connecting the main board 11 and the secondary board 12. The CS pin of the gold finger PADs 4 is located on the outer edge of the secondary board 12. This main and secondary board design allows the gold finger PADs to be positioned relatively independently, keeping them away from the high-voltage lines on the main board and significantly reducing signal interference to the pins of the chip under test.
[0027] Specifically, the test circuit 2 includes relays K1A, K2A, K2B, K6A, K9A, K9B, K5A, K12B, K3A, K4A, K14A, K12A, K10A, K11A, K13A, resistor R8, and resistor R. CS The terminal block 3 is defined as follows: resistor R9, operational amplifier U1, operational amplifier U2; the terminal block 3 is defined as having an OVI 1 pin for outputting a first test voltage (30V), an OVI 2 pin for outputting a second test voltage (5V), and a TMU 1 pin for receiving test signals.
[0028] Relay K1A connects the HV pin of the gold finger PAD 4 to the OVI 1 pin of terminal 3, and is used to connect the HV pin to the first test voltage (30V) output by the host computer; Relays K2A and K2B are connected in series and then connected to the DRAIN pin of the gold finger PAD 4 and the OVI 2 pin of terminal 3, and are used to connect the DRAIN pin to the second test voltage (5V) output by the host computer; Relay K6A connects the CS pin of the gold finger PAD 4 to the GND of the circuit board, and is used to control the CS pin to be grounded by the host computer during testing, and a filter capacitor C5 is connected between the CS pin and the GND of the circuit board; The comparator is implemented by the operational amplifier U1, Relay K9A connects the DRAIN pin of the gold finger PAD 4 to the non-inverting pin of the operational amplifier U1, Relay K9B connects the OVI 4 pin of terminal 3 to the inverting pin of the operational amplifier U1, and the output pin of the operational amplifier U1 is connected to the TMU1 pin of the terminal to output a test signal to the tester.
[0029] During testing, the host computer executes the following control actions:
[0030] 1) The OVI 1 source of the test machine (host computer) outputs 30V voltage to the OVI 1 pin, which passes through the relay K1A to the HV pin of the gold finger PAD 4, then returns to the GND pin of the switch IC, and finally returns to the AGND cable through the gold finger (grounding pin) of the switch IC to form a power supply circuit.
[0031] 2) The OVI2 power supply of the tester outputs 5V voltage to the OVI2 pin, which flows through relay K2A, resistor Rsw and relay K2B to the DRAIN pin of the gold finger PAD 4, then through the internal switch IC to the CS pin, and finally back to the GND pin to form a circuit.
[0032] 3) The voltage at the DRAIN pin of the gold finger PAD is connected to the non-inverting pin of operational amplifier U1 via relay K9A. The 2V output voltage from the OVI4 source of the tester is connected to the inverting pin of operational amplifier U1 via relay K9B. The signals from the non-inverting and inverting pins are then compared, and finally output to the TMU1 pin of the terminal block via resistor R5, so that the tester can read and calculate the waveform. The waveform at the DRAIN pin is isolated and impedance matched to the tester by a comparator implemented by operational amplifier U1 to prevent waveform distortion and interference, thus obtaining a normal waveform (as shown in the attached diagram). Figure 6 (As shown), to ensure the accuracy of defective product detection.
[0033] This invention takes into account the grounding travel of the CS pin and its sensitivity to interference from high-voltage lines KVI and HVI. In addition to the spatial isolation achieved by the main and sub boards, the relay K6A is placed at the junction of the main board 11 and the sub board 12. This shortens the grounding travel of the CS pin, making the grounding of the CS pin as close to the real ground as possible, thereby greatly reducing misjudgment, improving the yield rate, and indirectly reducing costs.
[0034] Furthermore, to meet the testing requirements of various categories, the test circuit is also designed as follows: the host computer controls the on / off state of multiple relays to switch the circuit of the gold finger PAD under different test items, thus changing the test circuit configuration in various ways:
[0035] Relay K5A connects the non-inverting pin of the operational amplifier U2 and the CS pin of the gold finger PAD 4. The output pin of the operational amplifier U2 is connected to the OVI 3 pin of the terminal block 3, and the output pin and the inverting pin are connected to form a voltage follower.
[0036] One end of relay K12B is connected to the CS pin of gold finger PAD 4, and the other end is connected to GND via resistor R8; one end of relay K3A is connected to pin 3 of OVI of the terminal 3, and the other end is connected to the CS pin of gold finger PAD 4 via resistor Rcs; relay K4A is connected in parallel across resistor Rcs to short-circuit resistor Rcs as needed.
[0037] The common terminal of relay K14A is connected to the DRAIN pin of the gold finger PAD 4 via relay K12A. The normally open and normally closed terminals of relay K14A are respectively connected to an inductor branch (L1 and L2), and the inductance values of each inductor branch are different. The resistor R9 is connected in series with each inductor branch after parallel connection. Relays K10A and K11A are respectively connected to the two ends of resistor R9 to connect the OVI4 pin of the terminal 4 so that the OVI4 pin can measure the voltage across resistor R9.
[0038] The test circuit also includes indicator lights D1-D9, which are powered by connecting to pin 1 of terminal 3 via relay K13A.
[0039] The above preferred embodiments should be regarded as illustrative examples of the embodiments of the present application. Any technical deductions, substitutions, improvements, etc. that are similar to or based on the present application should be considered within the scope of protection of this patent.
Claims
1. An anti-interference test board, comprising a circuit board carrying test circuitry, the circuit board having terminals for connecting to a host computer, and gold finger PADs for pressing and contacting the chip under test, characterized in that, The circuit board includes a main board for mounting the test circuit and terminals, and a secondary board extending from the edge of the main board for mounting the gold finger PAD. The gold finger PAD is connected to the test circuit via a trace connecting the main board and the secondary board.
2. The anti-interference test board according to claim 1, characterized in that, The test circuit includes a first relay, a second relay, a third relay, a fourth relay, a fifth relay, and a first operational amplifier; The first relay connects the HV pin of the gold finger PAD to the OVI 1 pin of the terminal block, and is used to connect the first test voltage output by the host computer to the HV pin; The second relay connects the DRAIN pin of the gold finger PAD to the OVI2 pin of the terminal block, and is used to connect the second test voltage output by the host computer to the DRAIN pin; The third relay connects the CS pin of the gold finger PAD to the GND of the circuit board, and is used to control the host computer to ground the CS pin during testing. A filter capacitor is connected between the CS pin and the GND of the circuit board. The fourth relay connects the DRAIN pin of the gold finger PAD to the non-inverting pin of the first operational amplifier, the fifth relay connects the OVI4 pin of the terminal block to the inverting pin of the first operational amplifier, and the output pin of the first operational amplifier is connected to the TMU1 pin of the terminal block to output a test signal to the tester.
3. The anti-interference test board according to claim 2, characterized in that, The third relay is located at the junction of the main board and the sub-board.
4. The anti-interference test board according to claim 3, characterized in that, The CS pin of the gold finger PAD is located on the outer edge of the sub-plate.
5. The anti-interference test board according to claim 2, characterized in that, The test circuit also includes a sixth relay and a second operational amplifier; the sixth relay is connected to the non-inverting pin of the second operational amplifier and the CS pin of the gold finger PAD, the output pin of the second operational amplifier is connected to the OVI 3 pin of the terminal block, and the output pin is connected to the inverting pin.
6. The anti-interference test board according to claim 2, characterized in that, The test circuit also includes an eighth relay, a ninth relay, a tenth relay, a first resistor, and a second resistor; one end of the eighth relay is connected to the CS pin of the gold finger PAD, and the other end is connected to GND via the first resistor; one end of the ninth relay is connected to the OVI 3 pin of the terminal block, and the other end is connected to the CS pin of the gold finger PAD via the second resistor; the tenth relay is connected in parallel across the two ends of the second resistor.
7. The anti-interference test board according to claim 2, characterized in that, The test circuit also includes an eleventh relay, a twelfth relay, a thirteenth relay, a fourteenth relay, and a third resistor. The common terminal of the eleventh relay is connected to the DRAIN pin of the gold finger PAD via the twelfth relay. The normally open and normally closed terminals of the eleventh relay are each connected to an inductor branch with different inductance values. The third resistor is connected in series with each of the parallel inductor branches. The thirteenth and fourteenth relays are connected to the two ends of the third resistor to connect the OVI4 pin of the terminal block.
8. The anti-interference test board according to claim 2, characterized in that, The test circuit also includes an indicator light, which is powered via the fifteenth relay connected to pin 1 of the terminal block OVI.
9. The anti-interference test board according to claim 1, characterized in that, The gold finger PAD is a Kelvin gold finger soldered PAD.