Circuit structure, circuit system and integrated circuit chip
By combining the circuit structures of the first logic array and the second logic array, the problem of insufficient driving capability in small and medium-scale integrated circuits is solved, realizing a multi-functional circuit design that is applicable to multiple process platforms and reduces the use of redundant devices.
Patent Information
- Application Number
- CN202423145193.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-12-19
AI Technical Summary
In small and medium-scale integrated circuits, the small saturation current of the device results in weak driving capability, making it difficult to drive multiple input signals. Furthermore, existing technologies can only increase chip area and improve driving capability by adding more devices.
By combining the first logic array and the second logic array, a circuit structure is realized that can realize both full adder function and decoder function, and the connection mode of NMOS and PMOS transistors is utilized to optimize the circuit structure and reduce redundant devices.
This allows the circuit structure to perform multiple functions simultaneously without increasing chip area, making it suitable for different process platforms and improving driving capability and circuit practicality.
Smart Images
Figure CN223486493U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of electronic circuit technology. Specifically, it relates to a circuit structure, a circuit system, and an integrated circuit chip. Background Technology
[0002] In conventional small- and medium-scale integrated circuits, when using gate circuits to form digital circuits, there are situations where one output signal drives multiple input signals. For process platforms with low device saturation current, the driving capability is often weak, making it difficult to realize the circuit function. To meet the requirement of one output signal driving multiple input signals, an even number of inverters are usually added after the output signal, leading to increased redundant devices and chip area, and the driving capability cannot be significantly improved. Therefore, there is a need to combine logic circuit devices so that the circuit structure can realize the circuit function by driving only a single transistor.
[0003] A circuit structure can generally only perform one specific function. However, as the requirements for integrated circuit design and manufacturing costs become increasingly stringent, it is necessary to implement multiple functions in a single circuit structure to achieve multiple uses, enhance its practicality, and reduce costs. Utility Model Content
[0004] To solve the above-mentioned technical problems, this utility model proposes a circuit structure that can realize different functions through the combination of logic arrays. Specifically, the circuit structure can realize both full adder and decoder functions.
[0005] This utility model provides a circuit structure, including a first logic array and a second logic array. The first logic array is an AND logic array, including a first signal input port and a first signal output port. The second logic array is an OR logic array, including a second signal input port and a second signal output port. The first signal output port and the second signal input port are connected to each other.
[0006] The circuit structure also includes at least one input port, a first output port and a second output port, wherein the input port is connected to the first signal input port, the first signal output port is connected to the first output port, and the second signal output port is connected to the second output port;
[0007] The circuit input port is configured to input a logic input signal to the circuit structure, and the circuit structure is configured to output a signal through at least one of the first output port and the second output port according to the logic input signal, so as to realize at least one of the functions of a decoder and a full adder, respectively.
[0008] Alternatively, the circuit structure can function as either a full adder or a decoder.
[0009] Optionally, each circuit input port is directly connected to a first signal input port and connected to another first signal input port through an odd-numbered inverter; each first signal output port is connected to a first output port through an odd-numbered inverter, and each second signal output port is connected to a second output port through an odd-numbered inverter.
[0010] Optionally, each column of the first logic array corresponds to a first signal input port, each row of the first logic array corresponds to a first signal output port, each row of the second logic array corresponds to a second signal input port, and each column of the second logic array corresponds to a second signal output port.
[0011] Optionally, the first logic array has an even number of columns, with each input port directly connected to one column of the first logic array and connected to the other column via an odd number of inverters;
[0012] Each row of the first logic array is connected to a first output port via an odd-numbered stage of inverters;
[0013] Each column of the second logic array is connected to a second output port via an odd-numbered series of inverters.
[0014] Optionally, each column of the first logic array corresponds to a first signal input port, and each row corresponds to a first signal output port;
[0015] Each row of the second logic array corresponds to a second signal input port, and each column corresponds to a second signal output port.
[0016] Optionally, the rows and columns in the first logic array are connected by NMOS transistors, the drains of the NMOS transistors in each row are connected to each other and connected to the drains of the PMOS transistors, and the gates of the NMOS transistors in each column are connected to each other.
[0017] Optionally, rows and columns in the second logic array are connected by NMOS transistors, and the drains of the NMOS transistors in each column are connected to each other and to the drains of the PMOS transistors.
[0018] Optionally, the first logic array and the second logic array are composed of logic devices.
[0019] Optionally, the first logic array and the second logic array are fixed logic arrays. Each row of the first logic array is connected to the drain of the PMOS transistor, and each column of the second logic array is connected to the drain of the PMOS transistor. The gate of the PMOS transistor is connected to a low level, and the source and substrate are connected to a high level, so that the PMOS transistor remains in the on state.
[0020] Optionally, the first logic array comprises 8 rows and 6 columns, wherein each row includes 3 drain-connected NMOS transistors and each column includes 4 gate-connected NMOS transistors, and the second logic array comprises 8 rows and 2 columns, wherein each column includes 4 drain-connected NMOS transistors.
[0021] This invention also provides a circuit system including at least one circuit structure according to the above embodiments. The circuit system inputs logic input signals to the circuit structure, and the circuit structure outputs signals through a first output port and a second output port according to the logic input signals, thereby realizing different circuit functions.
[0022] Optionally, the circuit system includes multiple interconnected circuit structures according to the above embodiments, wherein every two interconnected circuit structures are connected to each other through the input port of one circuit structure and the second output port of the other circuit structure.
[0023] This utility model also provides an integrated circuit chip, including the circuit system according to the above embodiments.
[0024] The circuit structure, circuit system, and integrated circuit chip provided by the embodiments of this utility model can simultaneously realize multiple functions, are applicable to different process platforms, and reduce the use of redundant devices.
[0025] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model or the background art, the accompanying drawings used in the embodiments of this utility model or the background art will be described below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A schematic diagram of the circuit structure in one embodiment of the present invention is shown;
[0028] Figure 2 A schematic diagram of the logic function of the circuit structure in one embodiment of the present invention is shown.
[0029] Figure 3 A schematic diagram of the circuit structure in a circuit system according to one embodiment of the present invention is shown.
[0030] List of reference numerals in the attached diagram: 100 - First logic array; 110 - First signal input port; 120 - First signal output port; 200 - Second logic array; 210 - Second signal input port; 220 - Second signal output port; 300 - Circuit input port; 410 - First output port; 420 - Second output port. Detailed Implementation
[0031] In the description of this utility model, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0032] In the description of the embodiments of this utility model, those skilled in the art should understand that the embodiments of this utility model can be implemented as devices and electronic devices. Therefore, the embodiments of this utility model can be specifically implemented in hardware form or in a combination of hardware and software.
[0033] In related technologies, when designing circuits on process platforms with weak device driving capabilities, circuit functions are typically achieved by adding components, which is difficult to effectively improve driving capabilities and increases chip area. The circuit structure adopted in this invention can simultaneously realize multiple functions, making the circuit applicable to more process platforms.
[0034] like Figure 1 As shown, the circuit structure includes a first logic array 100, a second logic array 200, at least one circuit input port 300, at least one first output port 410, and at least one second output port 420. The first logic array 100 is an AND logic array, including at least one first signal input port 110 and at least one first signal output port 120; the second logic array 200 is an OR logic array, including at least one second signal input port 210 and at least one second signal output port 220.
[0035] In an optional embodiment, the rows and columns of the first logic array 100 correspond completely to the first signal output port 120 and the first signal input port 110, respectively, and the rows and columns of the second logic array 200 correspond completely to the second signal input port 210 and the second signal output port 220, respectively. Specifically, each column of the first logic array 100 corresponds to one first signal input port 110, each row of the first logic array 100 corresponds to one first signal output port 120, each row of the second logic array 200 corresponds to one second signal input port 210, and each column of the second logic array 200 corresponds to one second signal output port 220.
[0036] In various optional embodiments of this utility model, each first signal output port 120 is connected to each second signal input port 210, so that the output signal of the first logic array 100 is input to the second logic array 200 as an input signal.
[0037] In various optional embodiments of this utility model, the first logic array 100 and / or the second logic array 200 are composed of logic devices. A circuit input port 300 is connected to a first signal input port 110 for inputting a logic input signal into the circuit structure. The logic input signal passes through the circuit structure to obtain a logic result signal, which is output through at least one of the first output port 410 and the second output port 420. When the logic input signal is output through at least one of the first output port 410 and the second output port 420, the circuit structure can respectively implement at least one of the functions of a decoder and a full adder. When the logic input signal is output as a decoded output signal only from the first output port 410, the circuit structure implements a decoder function. When the logic input signal is output as a full adder output signal only from the second output port 420, the circuit structure implements a full adder function. When the logic input signal is output through both the first output port 410 and the second output port 420, the circuit structure implements both a decoder function and a full adder function.
[0038] In an optional embodiment, the first logic array 100 is an AND logic array, and the second logic array 200 is an OR logic array.
[0039] In an optional embodiment, the circuit input port 300 is connected to the first signal input port 110. During the operation of the circuit, the logic input signal is input into the circuit structure through the first signal input port 110.
[0040] The first signal output port 120 is connected to the first output port 410, and the second signal output port 220 is connected to the second output port 420.
[0041] In an optional embodiment, each circuit input port 300 is directly connected to a first signal input port 110 and connected to another first signal input port 110 via an odd-stage inverter. Each first signal output port 120 is connected to a first output port 410 via an odd-stage inverter, and each second signal output port 220 is connected to a second output port 420 via an odd-stage inverter.
[0042] In an optional embodiment, each row of the first logic array 100 is connected to the drain of a PMOS transistor, and each column of the second logic array 200 is connected to the drain of a PMOS transistor. Taking the first logic array 100 as an example, by connecting the gate of the PMOS transistor to a low level and the source and substrate to a high level, the PMOS transistor is kept in the on state, thereby enabling the PMOS transistor to cooperate with the NMOS transistors in each row of the first logic array 100 to jointly determine the level (high level or low level) of the logic output signal in the row of the first logic array 100.
[0043] In an alternative embodiment, the circuit structure can implement both full adder and decoder functions.
[0044] Furthermore, such as Figure 1 As shown, the first logic array 100 is an 8-row, 6-column AND logic array, and the second logic array 200 is an 8-row, 2-column OR logic array. Each row of the first logic array 100 includes 3 NMOS transistors with their drains connected, and each column includes 4 NMOS transistors with their gates connected. Each column of the second logic array 200 includes 4 NMOS transistors with their drains connected.
[0045] The circuit structure according to this embodiment can at least realize the functions of a 1-bit binary full adder, a 2-to-4 decoder, and a 3-to-8 decoder. To further describe the features of the circuit structure provided in this embodiment, the following description is in conjunction with the accompanying drawings. Figure 2 An exemplary circuit structure that meets the usage requirements is described.
[0046] like Figure 2 As shown, in the first logic array 100 and the second logic array 200 of this embodiment, rows and columns are fixedly connected using NMOS transistors, and each row of the first logic array 100 and each column of the second logic array 200 are connected to the drain of a PMOS transistor. Preferably, each row of the first logic array 100 and each column of the second logic array 200 are connected to the drain of a PMOS transistor. In this embodiment, the sources and substrates of all NMOS transistors are connected to a fixed low level, and the gates of all PMOS transistors are connected to a fixed low level.
[0047] The first logic array 100 is an AND logic array, comprising 8 rows and 6 columns. The 6 columns of the first logic array 100 are divided into 3 groups, corresponding to the 3 input signals A, B, and C respectively. i-1In each group, two columns and each row are connected by disconnection and fixed connection using NMOS transistors, respectively, so that the 12 NMOS transistors in the 8x6 AND logic array are arranged in a configuration of 4 NMOS transistors per column and 3 NMOS transistors per row. The two columns in each group are directly connected to the input signal and connected through an odd-numbered stage inverter, respectively, forming the input signal for the AND logic array. The gates of the 4 NMOS transistors in each column are connected together, and the drains of the 3 NMOS transistors in each row are connected together and connected to the drain of a PMOS transistor. The 8 rows in the first logic array 100 correspond to the 8 output signals of the AND logic array. The output signals of the AND logic array are input as input signals to the second logic array 200. Specifically, as... Figure 2 As shown, the first logic array 100 is in the first column (from) in the first direction. Figure 2 (as shown, counting from left to right) and rows 5, 6, 7, and 8 in the second direction (from...) Figure 2 (As shown, counting from bottom to top) is connected via NMOS transistors. The 2nd column in the first direction is connected to the 1st, 2nd, 3rd, and 4th rows in the second direction via NMOS transistors. The 3rd column in the first direction is connected to the 3rd, 4th, 7th, and 8th rows in the second direction via NMOS transistors. The 4th column in the first direction is connected to the 1st, 2nd, 5th, and 6th rows in the second direction via NMOS transistors. The 5th column in the first direction is connected to the 2nd, 4th, 6th, and 8th rows in the second direction via NMOS transistors. The 6th column in the first direction is connected to the 1st, 3rd, 5th, and 7th rows in the second direction via NMOS transistors.
[0048] The second logic array 200 is an OR logic array, comprising 8 rows and 2 columns. The gate of each row's NMOS transistor is connected to the output signal of the corresponding row's AND logic array, corresponding to the 8 input signals of the OR logic array. The drains of each column's 4 NMOS transistors are connected to the drains of PMOS transistors, forming the 2 output signals of the OR logic array. These output signals are then passed through an odd-numbered stage of inverters and output from the second output port. Specifically, as shown... Figure 2 As shown, the first column of the second logic array 200 in the first direction is connected to the first, second, third, and fifth rows in the second direction via NMOS transistors, and the second column in the first direction is connected to the first, fourth, sixth, and seventh rows in the second direction via NMOS transistors.
[0049] Specifically, the process by which the circuit structure in this embodiment implements the logic function of a 1-bit binary full adder is as follows: Figure 2 As shown, addend A, addend B, and carry C from the lower bit. i-1The values are input to the circuit structure through the circuit input port 300. For the first logic array 100, when all NMOS transistors in a row are off, its output value is high; when at least one NMOS transistor is on, its output value is low. The output value of the first logic array 100 is further input to the second logic array 200. When all NMOS transistors in a column are off, the output value of that column is high. After being inverted by an odd-stage inverter, the output value of the second output port 420 is low. When at least one NMOS transistor is on, its output value is low. After being inverted by an odd-stage inverter, the output value of the second output port 420 is high. For example: when addend A, addend B, and carry C from the lower bit... i-1 When all are low, in the second direction, only all NMOS transistors in the 8th row of the first logic array 100 are off. Therefore, the output ports corresponding to the 1st row, 2nd row, 3rd row, 4th row, 5th row, 6th row, and 7th row of the first logic array 100 are low, and the output ports corresponding to the 8th row are high. This causes the NMOS transistors in the 1st and 2nd columns of the second logic array 200 to be off, resulting in the output ports corresponding to the 1st column being high (low after inversion) and the output ports corresponding to the 2nd column being high (low after inversion). Therefore, as shown in Table 1, the logic input signals for addend A, addend B, and carry C are... i-1 The values determine the final output sum S and the carry C from the sum of the original position and the original position addition. i The value of is determined so that the circuit structure can realize the logic function of a 1-bit binary full adder.
[0050] Table 1. Level correspondence of a one-bit binary full adder
[0051] Addend A Addend B <![CDATA[Low-order carry C i-1 > Output local sum S <![CDATA[Carry C for本位 addition i > Low Low Low Low Low Low Low high high Low Low high Low high Low Low high high Low high high Low Low high Low high Low high Low high high high Low Low high high high high high high
[0052] The process by which the circuit structure in this embodiment implements the logic function of the 3-to-8 decoder is as follows: Figure 2As shown, the circuit input port 300 includes the input terminals A2, A1, and A0 of the 3-to-8 decoder circuit, and the first output port 410 includes the output terminals Q0 to Q7 of the 3-to-8 decoder circuit. The eight output values of the eight rows of the first logic array 100, after passing through an odd-numbered stage of inverters, sequentially correspond to the output terminals Q0 to Q7 of the 3-to-8 decoder circuit and are output through the first output port 410, thus realizing the logic function of the 3-to-8 decoder. When all NMOS transistors in a row are off, its output value is high; when at least one NMOS transistor is on, its output value is low. For example: When inputs A2, A1, and A0 are all low, only all NMOS transistors in row 8 of the first logic array 100 are off in the second direction. Therefore, the output port corresponding to row 8 of the first logic array 100 in the second direction is high, and after inversion, the output Q0 is low; the output port corresponding to row 7 is low, and after inversion, the output Q1 is high; the output port corresponding to row 6 is low, and after inversion, the output Q2 is high; the output port corresponding to row 5 is low, and after inversion, the output Q3 is high; the output port corresponding to row 4 is low, and after inversion, the output Q4 is high; the output port corresponding to row 3 is low, and after inversion, the output Q5 is high; the output port corresponding to row 2 is low, and after inversion, the output Q6 is high; the output port corresponding to row 1 is low, and after inversion, the output Q7 is high. Therefore, as shown in Table 2, the values of input terminals A2, A1, and A0 determine the final output terminal values Q0 to Q7, thus enabling the circuit structure to realize the logic function of a 3-to-8 decoder.
[0053] Table 2.3-8 Level correspondence of decoders
[0054]
[0055]
[0056] When the circuit structure in this embodiment implements the logic function of a 2-to-4 decoder, such as Figure 2 As shown, the circuit input port 300 includes the input terminals A1 and A0 of the 2-4 decoder circuit. When A2 is connected to a fixed low level, the first output port 410 includes the output terminals Q0 to Q3 of the 3-8 decoder circuit. When A2 is connected to a fixed high level, the first output port 410 includes the output terminals Q4 to Q7 of the 3-8 decoder circuit.
[0057] This utility model embodiment also provides a circuit system, including at least one circuit structure provided in any of the above embodiments, wherein a logic input signal can be input to the circuit structure through the circuit system, and different logic functions can be obtained at different output ports.
[0058] In an optional embodiment, the circuit system includes multiple interconnected circuit structures. Two interconnected circuit structures are connected to each other by means of a circuit input port 300 of one circuit structure and a second output port 420 of another circuit structure, so as to expand the logic function of the circuit structure, which is conducive to the modularization of integrated circuits and makes the circuit system more flexible, efficient and easy to maintain.
[0059] In various optional embodiments of this utility model, the connection between circuit structures is a fixed connection.
[0060] To further describe the structural features of the circuit system provided in the embodiments of this utility model, the following example uses a circuit system including at least one binary full adder, in conjunction with the attached diagram. Figure 3 The circuit system provided by the embodiments of the utility model is described by way of example.
[0061] Figure 3 The diagram illustrates a circuit system in which four circuit structures are connected to implement a 4-bit binary full adder. Four 1-bit binary full adders can be cascaded, as shown below. Figure 3 As shown, the carry C of the first 1-bit binary full adder is the carry-in of the local addition. i Connect to the low-order carry input C of the next 1-bit binary full adder i-1 This process is repeated to implement the function of a 4-bit binary full adder, with the last 1-bit binary full adder having a carry C for its local addition. OUT This is the final carry-out output.
[0062] This design method can also be used to design full adders or half adders with other bit depths.
[0063] This utility model embodiment also provides an integrated circuit chip, including the circuit system provided in any of the above embodiments.
[0064] The circuit structure, circuit system, and integrated circuit chip provided by this utility model can simultaneously realize multiple logic functions, are applicable to different process platforms, and reduce the use of redundant devices.
[0065] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.
Claims
1. A circuit structure, characterized in that, The circuit structure includes a first logic array (100), a second logic array (200), at least one circuit input port (300), at least one first output port (410), and at least one second output port (420); wherein The first logic array (100) is an AND logic array, including at least one first signal input port (110) and at least one first signal output port (120), and the second logic array (200) is an OR logic array, including at least one second signal input port (210) and at least one second signal output port (220), and each first signal output port (120) is correspondingly connected to each second signal input port (210); The circuit input port (300) is connected to the first signal input port (110), the first signal output port (120) is connected to the first output port (410), and the second signal output port (220) is connected to the second output port (420). The circuit input port (300) is configured to input a logic input signal to the circuit structure, which is configured to perform at least one of a decoder function and a full adder function respectively when the logic input signal is output through at least one of the first output port (410) and the second output port (420).
2. The circuit structure according to claim 1, characterized in that, Each of the circuit input ports (300) is directly connected to one of the first signal input ports (110) and connected to another of the first signal input ports (110) through an odd-stage inverter; Each of the first signal output ports (120) is connected to a first output port (410) via an odd-stage inverter, and each of the second signal output ports (220) is connected to a second output port (420) via an odd-stage inverter.
3. The circuit structure according to claim 1 or 2, characterized in that, The first logic array (100) and / or the second logic array (200) are composed of logic devices.
4. The circuit structure according to claim 1 or 2, characterized in that, Each column of the first logic array (100) corresponds to a first signal input port (110), each row of the first logic array (100) corresponds to a first signal output port (120), each row of the second logic array (200) corresponds to a second signal input port (210), and each column of the second logic array (200) corresponds to a second signal output port (220).
5. The circuit structure according to claim 4, characterized in that, The rows and columns of the first logic array (100) are connected by NMOS transistors. The drains of the NMOS transistors in each row are connected to each other and to the drains of the PMOS transistors. The gates of the NMOS transistors in each column are connected. The rows and columns of the second logic array (200) are connected by NMOS transistors, wherein the drains of the NMOS transistors in each column are connected to each other and connected to the drains of the PMOS transistors.
6. The circuit structure according to claim 5, characterized in that, The first logic array (100) comprises 8 rows and 6 columns, wherein each row includes 3 NMOS transistors and each column includes 4 NMOS transistors; The second logic array (200) comprises 8 rows and 2 columns, with each column containing 4 NMOS transistors.
7. A circuit system, characterized in that, The circuit system includes at least one circuit structure according to any one of claims 1-6; The circuit system is configured to input the logic input signal into the circuit structure.
8. The circuit system according to claim 7, characterized in that, The circuit system includes multiple interconnected circuit structures; wherein The two connected circuit structures are configured to be connected to the second output port (420) of the other circuit structure via the circuit input port (300) of one circuit structure.
9. An integrated circuit chip, characterized in that, The integrated circuit chip includes the circuit system according to claim 7 or 8.