Aviation airborne hardware universal platform based on AI calculation

Abstract

The utility model belongs to the technical field of avionics computing, and particularly relates to an aviation airborne hardware universal platform based on AI computing. The universal platform comprises a core SoC minimum system circuit, an acquisition communication interface, an external storage circuit and an intelligent computing circuit; the core SoC minimum system circuit is connected with the acquisition communication interface, the external storage circuit and the intelligent computing circuit hardware. Collection, data processing and intelligent calculation are integrated, and a basic hardware platform is provided for intelligentization of aviation airborne products; a core SoC minimum system circuit and an intelligent calculation circuit form a basic core circuit of the aviation airborne hardware universal platform for AI calculation, and the basic core circuit has universality and can not be changed in subsequent board card design; the acquisition communication interface and the external storage circuit can be used for selecting and reconstructing different functional circuits according to the requirements of users, and the expandability is realized. The design mode of the basic core circuit and the extensible circuit greatly reduces the development cycle and development cost, and reduces the debugging difficulty.

Description

Technical Field

[0001] This utility model belongs to the field of avionics computing technology, and in particular relates to a general-purpose airborne hardware platform based on AI computing. Background Technology

[0002] With the development and increasing maturity of artificial intelligence technology, it has been widely applied in more and more fields. In airborne products, there is often a large amount of data transmission and flow. To enable AI technology to be better applied to airborne products, data can be fully utilized and ultimately serve users. Realizing intelligent aviation data is a major trend at present. Utility Model Content

[0003] To address the problems in the background technology, this utility model provides a general-purpose airborne hardware platform for AI computing, enabling the intelligentization of airborne equipment. This hardware platform integrates data acquisition, processing, and computation, providing a foundation for the subsequent development of intelligent software and AI algorithms. The platform hardware is scalable, supports diverse interface options, and saves time and manpower costs for the development of subsequent circuit boards.

[0004] To achieve the above objectives, the present invention adopts the following technical solution.

[0005] A general-purpose airborne hardware platform based on AI computing, the general-purpose platform includes a core SoC minimum system circuit, a data acquisition and communication interface, an external storage circuit, and an intelligent computing circuit;

[0006] The core SoC minimum system circuit is hardware connected to the data acquisition and communication interface, external storage circuit, and intelligent computing circuit, respectively.

[0007] Furthermore,

[0008] The core SoC minimum system circuit is based on the FMQL series 100TAI chip and includes DDR3 circuit, FLASH circuit, clock circuit, power supply circuit, RS-232 debugging circuit, JTAG interface, watchdog circuit and LED indicator circuit.

[0009] The 100TAI chip model is JFMQL100TAI, which integrates a quad-core high-performance processor with a working frequency of 1GHz to meet the performance requirements of AI computing.

[0010] The DDR3 circuit uses two DDR3 SDRAM chips connected to the BANK 502 on the PS side of the 100TAI chip, with a storage space of 1GB, a bus width of 32bit, and a maximum data rate of 1066Mbps.

[0011] The FLASH circuit uses a 16MB QSPI interface FLASH memory to store the program and a 16MB SPI interface FLASH memory to store configuration and log information.

[0012] The clock circuit uses a single clock input and a 50MHz crystal oscillator to provide the clock input for the 100TAI chip.

[0013] The power supply circuit consists of a DC / DC power supply chip and an LDO chip;

[0014] The RS-232 debugging circuit uses an RS-232 driver to convert TTL level to RS-232 level to enable serial port printing function;

[0015] The JTAG interface is debugged using JTAG standalone mode;

[0016] The watchdog circuit generates a feed signal from the FPGA at regular intervals. Once the feed signal stops, the watchdog circuit will drive the processor to start and reset.

[0017] The LED indicator circuit is used to display the power status, processor running status, and program loading status.

[0018] Furthermore,

[0019] The acquisition and communication interface includes acquisition and communication interfaces for various types of signals, enabling distributed acquisition and data transmission of different signals.

[0020] Distributed acquisition includes the acquisition of audio and video signals;

[0021] For AUDIO audio signals, the audio signal acquisition circuit uses an audio driver chip to amplify and filter the audio signal before sampling and analog-to-digital conversion by the audio driver, and then transmitting it to the processor's I / O port for processing.

[0022] For ARINC818 video signals, after conversion by an optical module, they are connected to the 100TAI MGT BANK for processing; for SDI video signals, an SDI video equalizer driver is used to convert the signals into differential LVDS level signals for processing.

[0023] Furthermore,

[0024] The acquisition and communication interface realizes the data transmission and communication functions of different signals, including Ethernet communication and SRIO communication;

[0025] The Ethernet interface consists of an Ethernet PHY chip with RGMII / GMII functionality and a switch. Depending on the actual needs of different boards, it can realize the data transmission function of multiple Ethernet channels. One PHY chip and switch are connected to the PS end of the 100TAI chip. The PHY chip is configured with an RGMII / GMII interface, and the switch connects multiple PHY chips. The circuit supports 10 / 100 / 1000Mbps rate auto-adaptation and can realize the transmission of multiple optical / electrical Ethernet channels as needed.

[0026] The SRIO interface is brought out by the MGT BANK through a high-speed connector for communication with other boards.

[0027] Furthermore,

[0028] External storage circuitry includes storage mode selection circuitry, eMMC storage circuitry, and NVMe storage circuitry;

[0029] The storage mode selection circuit is set with a selection switch, which enables the power supply switching function between the EMMC storage circuit and the NVME storage circuit by changing the jumper. The appropriate external storage circuit can be selected according to the actual needs of different boards.

[0030] The EMMC storage circuit uses an EMMC storage chip, which is directly connected to the PL terminal of the 100TAI chip;

[0031] The NVME storage circuit uses an NVME disk to connect and communicate with the 100TAI chip via a PCIe high-speed bus.

[0032] Furthermore,

[0033] The NVME disk circuitry is designed on other boards, and the general-purpose platform only retains the PCIe interface for communication with it.

[0034] Furthermore,

[0035] The intelligent computing circuit includes an intelligent computing unit and peripheral circuits. It is constructed by connecting four DDR3 SDRAM chips in parallel and connecting them to BANK33, BANK34 and BANK35 on the PL side of the 100TAI chip. Its storage capacity is 2GB, the bus width is 64bit, and the maximum speed is 1066Mbps.

[0036] This utility model discloses a general-purpose airborne hardware platform for AI computing, integrating data acquisition, processing, and computation. It supports complex AI computing functions for onboard data, providing hardware platform support for subsequent user application development of onboard data. The core SoC minimum system circuit and intelligent computing circuit constitute the basic core circuit of the general-purpose airborne hardware platform for AI computing, and have universality. The data acquisition communication interface and external storage circuit can be selected and reconfigured according to user needs, and have scalability, saving time and manpower costs for subsequent board development. Attached Figure Description

[0037] Figure 1 This is a block diagram of the minimum system core SoC for a general-purpose airborne hardware platform used for AI computing.

[0038] Figure 2 This is a block diagram of the communication interface for a general-purpose airborne hardware platform used for AI computing.

[0039] Figure 3 This is a block diagram of the external storage circuit of a general-purpose airborne hardware platform for AI computing.

[0040] Figure 4 It is an intelligent computing circuit, a general-purpose airborne hardware platform for AI computing. Detailed Implementation

[0041] The present invention will now be described in detail with reference to the accompanying drawings.

[0042] This utility model embodiment provides a general-purpose airborne hardware platform based on AI computing. The general-purpose platform includes a core SoC minimum system circuit, a data acquisition and communication interface, an external storage circuit, and an intelligent computing circuit. The core SoC minimum system circuit is hardware-connected to the data acquisition and communication interface, the external storage circuit, and the intelligent computing circuit, respectively.

[0043] Please see Figure 1 This is a block diagram of the minimum system core SoC of a general-purpose airborne hardware platform for AI computing.

[0044] The core SoC minimum system circuit is based on the FMQL series 100TAI chip with AI processing and computing functions. It includes DDR3 (PS side) circuit, FLASH circuit, clock circuit, power supply circuit, RS-232 debugging circuit, JTAG interface, watchdog and LED indicator circuit. The power supply voltage required for its operation and debugging is +5V to 12V.

[0045] The 100TAI chip model is JFMQL100TAI. It integrates a quad-core high-performance processor with a working frequency of up to 1GHz, and supports GPU and VPU, which can meet the performance requirements of AI computing.

[0046] The DDR3 (PS side) circuit uses two DDR3 SDRAM chips connected to the BANK 502 on the PS side of the 100TAI chip, with a storage space of up to 1GB, a bus width of 32bit, and a maximum data rate of up to 1066Mbps.

[0047] The FLASH circuit uses one 16MB QSPI interface FLASH memory to store the program and one 16MB SPI interface FLASH memory to store configuration and log information.

[0048] The clock circuit uses a single clock input, employing a 50MHz crystal oscillator to provide the clock input for the 100TAI chip. The power supply circuit mainly consists of a DC / DC power supply chip, an LDO chip, and related resistors and capacitors. The LDO provides power to the MGT module, ensuring ripple is controlled within 10mVpp, with 1.0V_MGT≤4A and 1.2V_MGT≤3A. The DC / DC provides power to other power supplies, with 1.0V power supply current ≤30A and other power supplies ≤8A.

[0049] The RS-232 debugging circuit uses one RS-232 driver to convert TTL level to RS-232 level to enable serial port printing function;

[0050] The JTAG interface is debugged using JTAG standalone mode;

[0051] The watchdog circuit generates a feed signal from the FPGA at regular intervals. Once the feed signal stops, the watchdog circuit will drive the processor to start and reset.

[0052] LED indicator circuits are mainly used to display power status, processor running status, and program loading status.

[0053] Please see Figure 2 This is a block diagram of the communication interface for a general-purpose airborne hardware platform used for AI computing.

[0054] The aforementioned acquisition and communication interface includes acquisition and communication interfaces for various types of signals, mainly realizing the functions of distributed acquisition and data transmission of different signals.

[0055] Distributed acquisition mainly includes the acquisition of audio and video signals. The acquisition interface circuit can be customized according to the actual needs of different boards.

[0056] For AUDIO audio signals, the audio signal acquisition circuit uses an audio driver chip to amplify and filter the audio signal before sampling and analog-to-digital conversion by the audio driver, and then transmitting it to the processor's I / O port for processing.

[0057] For ARINC818 video signals, the signal is converted by an optical module and then connected to the 100TAI MGT BANK for processing; for SDI video signals, an SDI video equalizer driver is used to convert the signal into a differential LVDS level signal for processing.

[0058] The acquisition and communication interface enables data transmission and communication functions for different signals, mainly including Ethernet communication and SRIO communication.

[0059] The Ethernet interface consists of an Ethernet PHY chip with RGMII / GMII functionality and a switch, enabling multi-channel Ethernet data transmission according to the actual needs of different boards. One PHY chip and switch connect to the PS end of the 100TAI chip. The PHY chip can be configured with an RGMII / GMII interface, and the switch connects multiple PHY chips. The circuit supports adaptive speeds of 10 / 100 / 1000Mbps, enabling multi-channel optical / electrical Ethernet transmission as needed.

[0060] The SRIO interface is brought out by the MGT BANK through a high-speed connector for communication with other boards.

[0061] Please see Figure 3 This is a block diagram of the external storage circuit of a general-purpose airborne hardware platform used for AI computing.

[0062] The external storage circuit mainly includes a high-capacity storage chip and its peripheral circuits, used to store a large amount of data information generated during acquisition and transmission, as well as calculated model information, etc. The platform is equipped with a storage chip selection circuit, which can select EMMC or NVME as the storage chip.

[0063] The external storage circuitry includes a storage mode selection circuit, an EMMC storage circuit, and an NVME storage circuit.

[0064] The storage mode selection circuit is set with a selection switch, which enables the power supply switching function between the EMMC storage circuit and the NVME storage circuit by changing the jumper. The appropriate external storage circuit can be selected according to the actual needs of different boards.

[0065] The EMMC storage circuit uses an EMMC storage chip, which is directly connected to the PL terminal of the 100TAI chip;

[0066] The NVMe storage circuit uses an NVMe drive that connects and communicates with the 100TAI chip via a high-speed PCIe bus. The NVMe drive circuitry is designed on other boards; this general-purpose platform only retains the PCIe interface for communication with it.

[0067] Please see Figure 4 It is an intelligent computing circuit, a general-purpose airborne hardware platform for AI computing.

[0068] The intelligent computing circuit includes an intelligent computing unit and peripheral circuits, providing hardware support for complex high-speed calculations of different AI algorithms. It is mainly composed of four DDR3 SDRAM chips connected in parallel, which are connected to BANK33, BANK34 and BANK35 on the PL side of the 100TAI chip. Its storage capacity is 2GB, the bus width is 64bit, and the maximum speed can reach 1066Mbps, which can support complex calculations of AI data on airborne products.

[0069] This utility model discloses a general-purpose airborne hardware platform for AI computing, specifically comprising a core SoC minimum system circuit, a data acquisition and communication interface, an external storage circuit, and an intelligent computing circuit. The core SoC minimum system circuit is based on the FMQL series 100TAI chip with AI processing and computing capabilities, and includes DDR3 (PS side) circuitry, FLASH circuitry, clock circuitry, power supply circuitry, RS-232 debugging circuitry, JTAG interface, watchdog timer, and LED indicator circuitry. The data acquisition and communication interface includes various signal acquisition and communication interfaces. The external storage circuit mainly comprises a high-capacity storage chip and its peripheral circuitry. The intelligent computing circuit includes an intelligent computing unit and its peripheral circuitry.

[0070] This invention proposes a general-purpose airborne hardware platform for AI computing, integrating data acquisition, data processing, and intelligent computing, providing a fundamental hardware platform for the intelligentization of airborne products. Its core SoC minimum system circuit and intelligent computing circuit constitute the basic core circuit of the general-purpose airborne hardware platform for AI computing, possessing universality and requiring no changes in subsequent board designs. Its data acquisition and communication interface and external storage circuit can be selected and reconfigured according to user needs, exhibiting scalability. This design approach of basic core circuit + scalable circuit significantly reduces development cycle and cost, and lowers debugging difficulty.

Claims

1. A general-purpose airborne hardware platform based on AI computing, characterized in that, The general platform includes a core SoC minimum system circuit, a data acquisition and communication interface, an external storage circuit, and an intelligent computing circuit. The core SoC minimum system circuit is hardware connected to the data acquisition and communication interface, external storage circuit, and intelligent computing circuit, respectively.

2. The general-purpose airborne hardware platform based on AI computing according to claim 1, characterized in that, The core SoC minimum system circuit is based on the FMQL series 100TAI chip and includes DDR3 circuit, FLASH circuit, clock circuit, power supply circuit, RS-232 debugging circuit, JTAG interface, watchdog circuit and LED indicator circuit. The 100TAI chip model is JFMQL100TAI, which integrates a quad-core high-performance processor with a working frequency of 1GHz to meet the performance requirements of AI computing. The DDR3 circuit uses two DDR3 SDRAM chips connected to the BANK 502 on the PS side of the 100TAI chip, with a storage space of 1GB, a bus width of 32bit, and a maximum data rate of 1066Mbps. The FLASH circuit uses a 16MB QSPI interface FLASH memory to store the program and a 16MB SPI interface FLASH memory to store configuration and log information. The clock circuit uses a single clock input and a 50MHz crystal oscillator to provide the clock input for the 100TAI chip. The power supply circuit consists of a DC / DC power supply chip and an LDO chip; The RS-232 debugging circuit uses an RS-232 driver to convert TTL level to RS-232 level to enable serial port printing function; The JTAG interface is debugged using JTAG standalone mode. The watchdog circuit generates a feed signal from the FPGA at regular intervals. Once the feed signal stops, the watchdog circuit will drive the processor to start and reset. The LED indicator circuit is used to display the power status, processor running status, and program loading status.

3. The general-purpose airborne hardware platform based on AI computing according to claim 2, characterized in that, The acquisition and communication interface includes acquisition and communication interfaces for various types of signals, enabling distributed acquisition and data transmission of different signals. Distributed acquisition includes the acquisition of audio and video signals; For AUDIO audio signals, the audio signal acquisition circuit uses an audio driver chip to amplify and filter the audio signal before sampling and analog-to-digital conversion by the audio driver, and then transmitting it to the processor's I / O port for processing. For ARINC818 video signals, after conversion by an optical module, they are connected to the 100TAI MGT BANK for processing; for SDI video signals, an SDI video equalizer driver is used to convert the signals into differential LVDS level signals for processing.

4. The general-purpose airborne hardware platform based on AI computing according to claim 3, characterized in that, The acquisition and communication interface realizes the data transmission and communication functions of different signals, including Ethernet communication and SRIO communication; The Ethernet interface consists of an Ethernet PHY chip with RGMII / GMII functionality and a switch. Depending on the actual needs of different boards, it can realize the data transmission function of multiple Ethernet channels. One PHY chip and switch are connected to the PS end of the 100TAI chip. The PHY chip is configured with an RGMII / GMII interface, and the switch connects multiple PHY chips. The circuit supports 10 / 100 / 1000Mbps rate auto-adaptation and can realize the transmission of multiple optical / electrical Ethernet channels as needed. The SRIO interface is brought out by the MGT BANK through a high-speed connector for communication with other boards.

5. The general-purpose airborne hardware platform based on AI computing according to claim 4, characterized in that, External storage circuitry includes storage mode selection circuitry, eMMC storage circuitry, and NVME storage circuitry; The storage mode selection circuit is set with a selection switch, which enables the power supply switching function between the EMMC storage circuit and the NVME storage circuit by changing the jumper. The appropriate external storage circuit can be selected according to the actual needs of different boards. The EMMC storage circuit uses an EMMC storage chip, which is directly connected to the PL terminal of the 100TAI chip; The NVME storage circuit uses an NVME disk to connect and communicate with the 100TAI chip via a PCIe high-speed bus.

6. The general-purpose airborne hardware platform based on AI computing according to claim 5, characterized in that, The NVME disk circuitry is designed on other boards, and the general-purpose platform only retains the PCIe interface for communication with it.

7. A general-purpose airborne hardware platform based on AI computing as described in claim 6, characterized in that, The intelligent computing circuit includes an intelligent computing unit and peripheral circuits. It is constructed by connecting four DDR3 SDRAM chips in parallel and connecting them to BANK33, BANK34 and BANK35 on the PL side of the 100TAI chip. Its storage capacity is 2GB, the bus width is 64bit, and the maximum speed is 1066Mbps.

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