Double-sided heat dissipation power semiconductor packaging structure and electronic device

Abstract

The utility model discloses a double-sided heat dissipation power semiconductor packaging structure and an electronic device, and relates to the technical field of power semiconductor packaging. The double-sided heat dissipation power semiconductor packaging structure comprises a lead frame, a chip main body, a copper-clad ceramic substrate, a sealing colloid and the like, double-sided heat dissipation is realized through the turnover arrangement of the chip main body, the staggered attachment of the copper-clad ceramic substrate and the zigzag design of a drain electrode pin, and the heat dissipation efficiency and reliability are improved. In addition, due to the coplanar design of the heat dissipation base island, the grid electrode pin and the drain electrode pin, the packaging structure is further optimized, and good electrical performance and heat conduction performance are ensured.

Description

Technical Field

[0001] This application relates to the field of power semiconductor packaging, and in particular to a double-sided heat dissipation power semiconductor packaging structure and electronic device. Background Technology

[0002] DFN packaging is an advanced double-sided or square flat lead-free packaging process, also known as dual-frame chip packaging. It offers advantages such as small size, high density, and good thermal conductivity, and is widely used in the field of integrated circuit packaging.

[0003] To enhance the heat dissipation capability of DFN-packaged devices, a double-sided heat dissipation structure is typically used. In existing double-sided DFN packages, both the front and back (the side soldered to the PCB) heat sinks are made of metal. In applications, the front heat sink is usually connected to the device housing or an external heat sink for better heat dissipation. However, since the front heat sink is metal, it needs to be insulated from electrical conductivity. Therefore, an insulating sheet is required between the front heat sink and the device housing or external heat sink. This insulating sheet is usually made of plastic, which has low thermal conductivity, resulting in a significant reduction in actual heat dissipation performance. Furthermore, it increases the assembly process and costs. Utility Model Content

[0004] In order to obtain a device with good heat dissipation performance on the front and insulation properties, this application provides a double-sided heat dissipation power semiconductor packaging structure and electronic device.

[0005] The first aspect of this application provides a double-sided heat dissipation power semiconductor packaging structure using the following technical solution:

[0006] A double-sided heat dissipation power semiconductor package structure includes:

[0007] The lead frame includes a gate pin, a drain pin, and a heat dissipation base island, wherein the drain pin has a bend.

[0008] The chip body is flipped and mounted on the lead frame. The chip body has a front side and a corresponding back side. The front side is provided with a source pad and a gate pad, and the back side is provided with a drain pad. The source pad is bonded to the heat dissipation base island, and the gate pad is bonded to the gate pin.

[0009] A copper-clad ceramic substrate is attached to the back side of the chip body in a staggered manner. The copper-clad ceramic substrate has a drain layer formed only on its inner surface. When the drain layer is bonded to a drain pad located on the back side, the drain layer has a pin mounting area that extends beyond the chip body. The drain pin is bent and bonded to the pin mounting area of ​​the drain layer.

[0010] An encapsulant is formed between the first lower surface of the heat dissipation island and the outer surface of the copper-clad ceramic substrate to seal the bend between the chip body and the drain pin. The outer surface of the copper-clad ceramic substrate is exposed on the top surface of the encapsulant, and the first lower surface of the heat dissipation island, the second lower surface of the gate pin, and the third lower surface of the drain pin are all exposed on the bottom surface of the encapsulant.

[0011] By adopting the above technical solutions, the use of copper-clad ceramic substrates not only improves the heat dissipation capacity of the device's front side, but also significantly enhances heat dissipation compared to traditional plastic insulating sheets due to the high thermal conductivity of ceramics and copper. Furthermore, the copper-clad ceramic substrates possess inherent insulating properties, eliminating the need for additional insulating sheets, reducing assembly steps, and lowering production costs. Meanwhile, traditional insulating sheets are prone to misalignment and puncture, potentially leading to leakage risks. The use of copper-clad ceramic substrates eliminates these potential safety hazards, improving product reliability and safety. In addition, the staggered attachment design of the copper-clad ceramic substrate and the lead mounting area design of the drain layer ensure good electrical connection and mechanical stability, further enhancing the overall performance of the packaging structure.

[0012] Optionally, the first lower surface of the heat dissipation base island, the second lower surface of the gate pin, and the third lower surface of the drain pin are coplanar and aligned with the bottom surface of the encapsulant.

[0013] By adopting the above technical solution, it is ensured that these parts are flush with the bottom surface of the encapsulant. This not only improves the overall flatness of the encapsulation structure but also enhances the contact area and uniformity between the encapsulation structure and the external heat dissipation device, thereby improving heat dissipation efficiency. In addition, the coplanar design simplifies the manufacturing process, reduces assembly errors, and improves product reliability and consistency.

[0014] Optionally, the lead frame also includes multiple source pins connected side-by-side to one side of the heat sink island, and multiple drain pins arranged on the other side of the heat sink island opposite to the source pins.

[0015] By adopting the above technical solution, the multi-source pin design results in more uniform current distribution, reduces the risk of localized overheating, and improves overall reliability. The multi-drain pin layout optimizes the heat dissipation path, further enhancing heat dissipation, while also facilitating connection to external circuits and simplifying the assembly process.

[0016] Optionally, one side of the heat dissipation island extends out of the chip body and approaches the drain pin. The drain pin has a notch on one side of the heat dissipation island, such that the distance between the drain pin and the heat dissipation island is equal to the gap between the drain pin and the side of the chip body.

[0017] By adopting the above technical solution, sufficient heat dissipation gaps are ensured between the drain pin and the heat dissipation island, as well as between the drain pin and the chip body, thereby improving heat dissipation efficiency. At the same time, the stability of the entire packaging structure is guaranteed, and the risk of device failure caused by thermal stress is reduced.

[0018] Optionally, the copper-clad ceramic substrate includes a copper layer and a ceramic layer, wherein the copper layer is attached to and extends beyond the back side of the chip body, and the ceramic layer covers the side of the copper layer opposite to the chip body.

[0019] By adopting the above technical solution, the copper-clad ceramic substrate integrates heat dissipation and insulation functions, eliminating the need for additional insulating sheets between the front of the device and the equipment casing or external heat sink, reducing assembly steps and lowering production costs.

[0020] Optionally, the thickness of the copper layer is 100um to 300um, and the thickness of the ceramic layer is 100um to 300um.

[0021] By adopting the above technical solution, it is possible to ensure that both the copper and ceramic layers possess excellent thermal conductivity, while guaranteeing sufficient mechanical strength and insulation performance. The optimized thickness range of the copper layer improves heat dissipation efficiency, reduces thermal resistance, and enhances the overall heat dissipation capacity of the device. The optimized thickness range of the ceramic layer ensures good insulation performance, prevents the risk of leakage, and maintains the device's slim and lightweight characteristics.

[0022] Optionally, the portion of the heat dissipation island where the chip body is attached is provided with multiple stabilizing bumps, which are used to stabilize the parallelism between the attachment portion of the heat dissipation island and the front surface of the chip body.

[0023] By adopting the above technical solution, it is possible to effectively ensure that the attachment area of ​​the heat dissipation island is highly parallel to the front side of the chip body, thereby improving the uniformity and stability of the contact between the chip body and the heat dissipation island, and further enhancing the heat dissipation effect. In addition, the flat bumps can also prevent the chip body from tilting or shifting during the soldering process, ensuring the overall reliability and consistency of the packaging structure.

[0024] Optionally, the plurality of the stabilized protrusions are distributed in a rectangular array.

[0025] By adopting the above technical solutions, the contact area and heat transfer efficiency between the chip and the heat dissipation island are increased, ensuring good heat dissipation performance. Furthermore, the stable bumps distributed in a rectangular array can effectively prevent the chip from tilting or deforming during the soldering process, improving the reliability and stability of the packaging structure.

[0026] Optionally, a solder layer is provided between the chip body and the copper-clad ceramic substrate, the heat dissipation island and the gate pin, and a solder layer is provided between the copper-clad ceramic substrate and the drain pin.

[0027] By adopting the above technical solution, the solder layer can effectively improve the connection reliability between the chip body and the copper-clad ceramic substrate, heat dissipation island, and gate pins, ensuring good electrical contact and mechanical stability between components, thereby improving the reliability and heat dissipation efficiency of the entire package structure. Simultaneously, the solder layer can also improve the heat conduction path, reduce thermal resistance, and further enhance the heat dissipation performance of the device.

[0028] A second aspect of this application provides an electronic device, including the aforementioned double-sided heat dissipation power semiconductor package structure and a printed circuit board.

[0029] By adopting the above technical solution, this electronic device utilizes a copper-clad ceramic substrate as the surface heat dissipation material, improving the heat dissipation capacity of the device's front side while also providing insulation properties. This eliminates the need for additional insulating sheets, reduces assembly processes, and lowers costs. The high thermal conductivity and insulation of the copper-clad ceramic substrate ensure a good connection with the device casing or external heat sink, improving overall heat dissipation and avoiding the risks of misalignment and puncture that may occur with insulating sheets, thus enhancing product reliability and safety.

[0030] In summary, this application includes at least one of the following beneficial technical effects:

[0031] 1. Using a copper-clad ceramic substrate as the surface heat dissipation material, the thermal conductivity of ceramic and copper is much higher than that of plastic materials, giving the front side of the device excellent heat dissipation capabilities. At the same time, the ceramic substrate itself has insulating properties, eliminating the need for additional insulating sheets, reducing assembly processes and lowering costs.

[0032] 2. The coplanar design not only improves the overall flatness of the package structure but also enhances the contact area and uniformity between the package structure and the external heat dissipation device, thereby improving heat dissipation efficiency. Furthermore, the coplanar design simplifies the manufacturing process, reduces assembly errors, and improves product reliability and consistency.

[0033] 3. The gap design ensures that there is sufficient heat dissipation gap between the drain pin and the heat dissipation island, as well as between the drain pin and the chip body, which improves heat dissipation efficiency and also ensures the stability of the entire package structure, reducing the risk of device failure caused by thermal stress. Attached Figure Description

[0034] Figure 1 This is a cross-sectional schematic diagram of a preferred embodiment of the double-sided heat dissipation power semiconductor package structure of this application;

[0035] Figure 2 This is a cross-sectional schematic diagram of a double-sided heat dissipation power semiconductor package structure according to another preferred embodiment of this application;

[0036] Figure 3This is a schematic diagram of the encapsulation bonding surface of a preferred embodiment of the double-sided heat dissipation power semiconductor package structure of this application.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10. Lead frame; 11. Gate pin; 12. Drain pin; 121. Bend; 122. Notch; 13. Heat dissipation island; 131. Flat bump; 14. Source pin; 20. Chip body; 21. Front side; 22. Back side; 23. Source pad; 24. Gate pad; 25. Drain pad; 30. Copper-clad ceramic substrate; 31. Drain layer; 32. Copper layer; 33. Ceramic layer; 40. Encapsulant; 50. Solder layer. Detailed Implementation

[0039] The following will refer to the appendices in the embodiments of this application. Figure 1-3 The technical solutions in the embodiments of this application are clearly and completely described. Obviously, the described embodiments are only some embodiments for understanding the inventive concept of this application, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art under the premise of understanding the inventive concept of this application are within the scope of protection of this application.

[0040] It should be noted that if directional indicators (such as up, down, left, right, front, back, etc.) are involved in the embodiments of this application, such directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. To better understand the technical solution of this application, the double-sided heat dissipation power semiconductor packaging structure and electronic device of this application will be described and explained in further detail below, but this is not considered as a limitation of the scope of protection of this application. In specific applications of variations, the source of the example can be used as the drain, and the drain of the example can be used as the source. The source to the drain represents the relative flow direction of electron flow. When the source described in the specification is used as the source, the drain described in the specification must be used as the drain; when the source described in the specification is used as the drain, the drain described in the specification must be used as the source. To facilitate understanding of the technical solution of this application, the specification and scope of protection still use the terms "source" and "drain," but in reality, they are not limited to source and drain. Instead, they represent a first electrode and a second electrode that represent two different potential poles. Therefore, those skilled in the art can interchange the "source" and "drain" of the semiconductor device after understanding the technical solution of this application, and the scope of protection of this application naturally includes such equivalent interchange.

[0041] The description in this specification primarily concerns the packaging structure; therefore, the transistor structure within the chip body is not detailed. It can be a prior art transistor structure or a transistor structure developed by the applicant. Whether the chip body uses an N-type transistor structure, a P-type transistor structure, or something else is not within the scope of this application. The isolation oxide layer or potential effect oxide layer present in the chip body can have various structures and variations. Whether the gate in the chip body is trench-type or stacked is not within the scope of this application; those skilled in the art, after clearly understanding the technical solution of this application, can make appropriate selections and adjustments based on prior art transistors.

[0042] The term "pad" in the specification for "source pad" and "gate pad" is not limited to a simple pad layer, and the term "pad" in the specification for "drain pad" is not limited to a simple pad layer, but refers to a drain contact in a broad sense, and may also be an additional metal bonding layer. The meaning of "pad" is that it is a pad-shaped object viewed in a two-dimensional plane; however, the referred element can have various three-dimensional structures. In a three-dimensional structure, a "pad" in a narrow sense refers to an object whose thickness (or height) is less than 30% of the width or diameter of the object. The terms "source pad," "gate pad," and "drain pad" in the specification and claims are used in a broad sense, including the shape of the "pad" in the narrow sense.

[0043] The accompanying drawings illustrate commonalities across multiple embodiments, while variations that differ or distinguish them are described in text. Therefore, based on industry characteristics and the nature of the technology, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination thereof described below can characterize the same embodiment, or whether multiple mutually exclusive technical features can only characterize different variations. In the accompanying drawings, G represents the gate signal, S represents the source electrode, and D represents the drain electrode.

[0044] The double-sided heat dissipation power semiconductor packaging structure provided in this application embodiment refers to... Figure 1The system includes a lead frame 10, a chip body 20, a copper-clad ceramic substrate 30, and an encapsulant 40. The lead frame 10 includes a gate pin 11, a drain pin 12, and a heat dissipation island 13. The drain pin 12 has a bend 121. The chip body 20 is flipped onto the lead frame 10 and has a front side 21 and a corresponding back side 22. The front side 21 has a source pad 23 and a gate pad 24, and the back side 22 has a drain pad 25. The source pad 23 is bonded to the heat dissipation island 13, and the gate pad 24 is bonded to the gate pin 11. The copper-clad ceramic substrate 30 is misaligned and attached to the back side 22 of the chip body 20, with a drain layer 31 formed only on its inner surface. When the drain layer 31 is bonded... Located on the back side 22, the drain pad 25 has a drain layer 31 extending beyond the chip body 20, with the drain pin 12 bent and bonded to the pin mounting area of ​​the drain layer 31. An encapsulant 40 is formed between the first lower surface of the heat dissipation island 13 and the outer surface of the copper-clad ceramic substrate 30 to seal the bend 121 between the chip body 20 and the drain pin 12. The outer surface of the copper-clad ceramic substrate 30 is exposed on the top surface of the encapsulant 40, while the first lower surface of the heat dissipation island 13, the second lower surface of the gate pin 11, and the third lower surface of the drain pin 12 are all exposed on the bottom surface of the encapsulant 40. This design provides the front side 21 of the device with excellent heat dissipation and insulation properties, eliminating the need for additional insulating sheets, reducing assembly process complexity and cost, and improving heat dissipation and safety.

[0045] Specifically, the chip body 20 has a semiconductor substrate, commonly made of silicon (Si), but can also include any semiconductor material such as SiC, GaN, GA2O3, SiGe, or GaAs, or other III-V or II-VI compounds. In the example, the front side 21 is the surface processed by semiconductor technology, and the back side 22 is the surface opposite to the front side 21, such as the transistor structure of a semiconductor power device being disposed between the front side 21 and the back side 22.

[0046] The source pad 23 and gate pad 24 are fixed to the front side 21 of the chip body 20 by soldering or other connection methods, and the drain pad 25 is fixed to the back side 22 of the chip body 20 by soldering or other connection methods. The heat dissipation base island 13 is die-bonded to the source pad 23 by baking. The heat dissipation substrate can be a metal with good heat dissipation performance, such as copper. The gate pin 11 can also be die-bonded to the gate pad 24 by baking. At the same time, the copper-clad ceramic substrate 30 can also be die-bonded to the drain pad 25 by baking. Specifically, a solder layer 50 is provided between the heat dissipation base island 13 and the source pad 23, between the gate pin 11 and the gate pad 24, and between the copper-clad ceramic substrate 30 and the drain pad 25 for soldering. Optionally, the solder layer 50 can be solder paste.

[0047] Reference Figure 2In a preferred embodiment, the portion of the heat dissipation island 13 where the chip body 20 is attached is provided with multiple stabilizing bumps 131. These bumps stabilize the parallelism between the attachment portion of the heat dissipation island 13 and the front surface 21 of the chip body 20, and are arranged in a rectangular array. This effectively ensures that the attachment portion of the heat dissipation island 13 remains highly parallel to the front surface 21 of the chip body 20, thereby improving the uniformity and stability of the contact between the chip body 20 and the heat dissipation island 13, and further enhancing the heat dissipation effect. Furthermore, the stabilizing bumps 131 also prevent the chip body 20 from tilting or shifting during the soldering process, ensuring the overall reliability and consistency of the packaging structure.

[0048] Reference Figure 1 and Figure 3 In a preferred embodiment, the lead frame 10 further includes a plurality of source pins 14, which are connected side-by-side on one side of the heat sink island 13. A gate pin 11 is located on the same side as the source pins 14, and is situated on the outermost side of the parallel source pins 14. In other embodiments, the gate pin 11 may be located between the plurality of source pins 14. Similarly, a plurality of drain pins 12 are also provided, arranged on the other side of the heat sink island 13 opposite to the source pins 14.

[0049] In a preferred embodiment, the first lower surface of the heat dissipation island 13, the second lower surface of the gate pin 11, the third lower surface of the drain pin 12, and the fourth lower surface of the source pin 14 are coplanar and aligned with the bottom surface of the encapsulant 40. This ensures that these portions are flush with the bottom surface of the encapsulant 40, which not only improves the overall flatness of the packaging structure but also enhances the contact area and uniformity between the packaging structure and the external heat dissipation device, thereby improving heat dissipation efficiency.

[0050] Reference Figure 1 The copper-clad ceramic substrate 30 is misaligned and attached to the back side 22 of the chip body 20. This attachment method indicates that the copper-clad ceramic substrate 30 is not installed at the wafer stage of semiconductor manufacturing, but rather at the packaging stage. This attachment serves three purposes: first, it provides a physical and mechanical bond between the copper-clad ceramic substrate 30 and the chip body 20, making them inseparable in the final product form; second, it provides electrical coupling between the copper-clad ceramic substrate 30 and the drain pad 25 of the chip body 20, allowing electron flow; and third, it provides thermal coupling between the copper-clad ceramic substrate 30 and the chip body 20, enabling faster heat transfer from the chip body 20 to the copper-clad ceramic substrate 30 during operation.

[0051] Specifically, the copper-clad ceramic substrate 30 consists of a copper layer 32 and a ceramic layer 33. The copper layer 32 is attached to and extends beyond the back surface 22 of the chip body 20, and the ceramic layer 33 covers the side of the copper layer 32 facing away from the chip body 20. The thickness of the copper layer 32 can be selected from 100µm to 300µm, and the thickness of the ceramic layer 33 can also be selected from 100µm to 300µm. For example, a 150µm copper layer 32 and a 200µm ceramic layer 33 can be selected to obtain optimal thermal conductivity and insulation performance. The materials of the copper layer 32 and the ceramic layer 33 can be selected according to specific application requirements. For example, the copper layer 32 can be pure copper or a copper alloy, and the ceramic layer 33 can be made of materials such as alumina, aluminum nitride, or silicon carbide to obtain optimal thermal conductivity and insulation performance.

[0052] In a preferred embodiment, the copper layer 32 is connected to the drain pin 12 via the solder layer 50. One side of the heat dissipation island 13 extends outward from the chip body 20 and approaches the drain pin 12. The drain pin 12 has a notch 122 on one side relative to the heat dissipation island 13, such that the distance between the drain pin 12 and the heat dissipation island 13 is equal to the gap between the drain pin 12 and the side of the chip body 20. This ensures sufficient heat dissipation gaps between the drain pin 12 and the heat dissipation island 13, and between the drain pin 12 and the chip body 20, improving heat dissipation efficiency and ensuring the stability of the entire package structure, reducing the risk of device failure due to thermal stress.

[0053] The function of the encapsulant 40 is to prevent moisture and impurities from entering the interior and affecting the performance of the device. Optionally, the material of the encapsulant 40 can be epoxy resin, polyurethane, or silicone rubber, which have good high temperature resistance and corrosion resistance. The shape of the encapsulant 40 can be designed according to actual needs, for example, it can be a planar structure or a structure with a notch 122, to adapt to different packaging requirements.

[0054] The implementation principle of this embodiment is as follows:

[0055] The packaging structure of this application adopts a flip-chip approach and uses a copper-clad ceramic substrate 30 as the surface heat dissipation material. Combined with an optimized lead frame 10 and chip body 20 structure, it achieves excellent heat dissipation and insulation characteristics on the front side 21 of the device. The copper layer 32 and ceramic layer 33 of the copper-clad ceramic substrate 30 have excellent thermal conductivity and insulation properties, respectively, eliminating the thermal resistance and safety hazards caused by traditional insulating sheets. In addition, the reasonable design of the encapsulant 40 further improves the sealing performance and reliability of the device. In summary, the design of this embodiment significantly improves the heat dissipation effect and safety of the double-sided heat dissipation power semiconductor packaging structure, reduces production and maintenance costs, and is suitable for various high-performance electronic devices.

[0056] This application also discloses an electronic device, including the above-described double-sided heat dissipation power semiconductor package structure and a printed circuit board. The source pin 14, drain pin 12 and gate pin 11 of the double-sided heat dissipation power semiconductor package structure are bonded to the circuit board with solder.

[0057] The double-sided heat-dissipating power semiconductor package structure in this embodiment can also be applied to various electronic devices, such as power management modules, frequency converters, and electric vehicle controllers. By integrating this package structure into these electronic devices, the heat dissipation performance and reliability of these devices can be significantly improved, the failure rate reduced, and the service life extended. For example, in an electric vehicle controller, this package structure can effectively reduce the risk of failure caused by high temperatures, improving the safety and reliability of the entire vehicle.

[0058] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A double-sided heat dissipation power semiconductor package structure, characterized in that, include: The lead frame (10) includes a gate pin (11), a drain pin (12) and a heat dissipation base island (13), wherein the drain pin (12) has a bend (121). The chip body (20) is flipped and mounted on the lead frame (10). The chip body (20) has a front side (21) and a corresponding back side (22). The front side (21) is provided with a source pad (23) and a gate pad (24). The back side (22) is provided with a drain pad (25). The source pad (23) is bonded to the heat dissipation base island (13). The gate pad (24) is bonded to the gate pin (11). A copper-clad ceramic substrate (30) is attached to the back side (22) of the chip body (20) in a staggered manner. The copper-clad ceramic substrate (30) has a drain layer (31) formed only on its inner surface. When the drain layer (31) is bonded to the drain pad (25) located on the back side (22), the drain layer (31) has a pin mounting area that extends beyond the chip body (20). The drain pin (12) is bent and bonded to the pin mounting area of ​​the drain layer (31). A sealant (40) is formed between the first lower surface of the heat dissipation base island (13) and the outer surface of the copper-clad ceramic substrate (30) to seal the bend (121) between the chip body (20) and the drain pin (12). The outer surface of the copper-clad ceramic substrate (30) is exposed on the top surface of the sealant (40), and the first lower surface of the heat dissipation base island (13), the second lower surface of the gate pin (11), and the third lower surface of the drain pin (12) are all exposed on the bottom surface of the sealant (40).

2. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: The first lower surface of the heat dissipation base island (13), the second lower surface of the gate pin (11), and the third lower surface of the drain pin (12) are coplanar and aligned with the bottom surface of the encapsulant (40).

3. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: The lead frame (10) also includes a plurality of source pins (14), which are connected side by side to the outside of one side of the heat dissipation base island (13). The drain pins (12) are configured as a plurality, which are arranged on the other side of the heat dissipation base island (13) opposite to the source pins (14).

4. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: The chip body (20) extends from one side of the heat dissipation base island (13) and approaches the drain pin (12). The drain pin (12) has a notch (122) on one side relative to the heat dissipation base island (13), such that the distance between the drain pin (12) and the heat dissipation base island (13) is equal to the gap between the drain pin (12) and the side of the chip body (20).

5. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: The copper-clad ceramic substrate (30) includes a copper layer (32) and a ceramic layer (33). The copper layer (32) is attached to the back side (22) of the chip body (20) and extends beyond the back side (22) of the chip body (20). The ceramic layer (33) covers the side of the copper layer (32) that is away from the chip body (20).

6. The double-sided heat dissipation power semiconductor packaging structure according to claim 5, characterized in that: The copper layer (32) has a thickness of 100um to 300um, and the ceramic layer (33) has a thickness of 100um to 300um.

7. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: The heat dissipation base island (13) is provided with a plurality of flat bumps (131) at the part where the chip body (20) is attached. The flat bumps (131) are used to stabilize the parallelism between the attachment part of the heat dissipation base island (13) and the front side (21) of the chip body (20).

8. The double-sided heat dissipation power semiconductor packaging structure according to claim 7, characterized in that: The multiple stable convex points (131) are distributed in a rectangular array.

9. The double-sided heat dissipation power semiconductor packaging structure according to claim 1, characterized in that: A solder layer (50) is provided between the chip body (20) and the copper-clad ceramic substrate (30), the heat dissipation base island (13) and the gate pin (11), and a solder layer (50) is provided between the copper-clad ceramic substrate (30) and the drain pin (12).

10. An electronic device, characterized in that: Includes the double-sided heat dissipation power semiconductor packaging structure and printed circuit board as described in any one of claims 1-9.

Images