Control circuit of release and circuit breaker system

Abstract

The utility model provides a control circuit of a release and a circuit breaker system, in the control circuit of the release, the output end of a control chip is respectively and electrically connected with the first end of a first pull-down resistor and the grid electrode of a first NMOS tube, the drain electrode of the first NMOS tube is respectively and electrically connected with the first end of a pull-up resistor and the grid electrode of a PMOS tube, and the drain electrode of the first NMOS tube is electrically connected with the first end of a second pull-down resistor. The drain electrode of the PMOS tube is electrically connected with the first end of the second pull-down resistor and the grid electrode of the second NMOS tube respectively, the drain electrode of the second NMOS tube is used for being electrically connected with the output end of a coil in the release, the power supply end of the control chip is used for accessing a first working voltage, and the second end of the pull-up resistor and the source electrode of the PMOS tube are used for accessing a second working voltage respectively. When the voltage value of the tripping signal output by the control chip is small, the high-voltage-resistant second NMOS tube can be driven, and the reliability of tripping control is improved.

Description

Technical Field

[0001] This utility model relates to the field of circuit breaker technology, specifically to a control circuit for a trip unit and a circuit breaker system. Background Technology

[0002] Residual current circuit breakers (RCCBs) are important protective devices specifically designed to provide protection against both direct and indirect electric shock. They are widely used in various electrical applications, including industrial, commercial, high-rise buildings, and residential buildings, and offer significant advantages such as compact size, ease of operation, high breaking capacity, and high reliability.

[0003] Commonly available miniature residual current circuit breakers typically use dedicated leakage current chips. Based on the tripping signal output by the dedicated leakage current chip, the thyristor is driven to conduct, triggering the trip unit to operate.

[0004] However, when a high-voltage MOSFET is used to control the trip unit, the voltage value of the trip signal output by the leakage current chip may not be able to drive the high-voltage MOSFET, resulting in low reliability of the trip control. Utility Model Content

[0005] In view of the shortcomings of the existing technology, this utility model provides a control circuit and circuit breaker system for a trip unit.

[0006] In one embodiment, the present invention provides a control circuit for a trip unit, the control circuit of which includes a control chip, a first NMOS transistor, a second NMOS transistor, a PMOS transistor, a first pull-down resistor, a second pull-down resistor, and a pull-up resistor;

[0007] The output terminal of the control chip is electrically connected to the first terminal of the first pull-down resistor and the gate of the first NMOS transistor, respectively. The drain of the first NMOS transistor is electrically connected to the first terminal of the pull-up resistor and the gate of the PMOS transistor, respectively. The drain of the PMOS transistor is electrically connected to the first terminal of the second pull-down resistor and the gate of the second NMOS transistor, respectively.

[0008] The drain of the second NMOS transistor is used to electrically connect to the output terminal of the coil in the trip unit. The power supply terminal of the control chip is used to connect to the first working voltage. The second terminal of the pull-up resistor and the source of the PMOS transistor are used to connect to the second working voltage, respectively. The second terminal of the first pull-down resistor, the source of the first NMOS transistor, the second terminal of the second pull-down resistor, and the source of the second NMOS transistor are grounded, respectively.

[0009] In one embodiment, the control circuit of the trip unit also includes a reverse protection diode;

[0010] The anode of the anti-reverse diode is electrically connected to the drain of the PMOS transistor, and the cathode of the anti-reverse diode is electrically connected to the first terminal of the second pull-down resistor and the gate of the second NMOS transistor.

[0011] In one embodiment, the control circuit of the trip unit also includes a varistor;

[0012] The first end of the varistor is electrically connected to the drain of the second NMOS transistor, and the second end of the varistor is electrically connected to the source of the second NMOS transistor.

[0013] In one embodiment, the control circuit of the trip unit also includes a freewheeling diode;

[0014] The cathode of the freewheeling diode is electrically connected to the input terminal of the coil in the trip unit, and the anode of the freewheeling diode is electrically connected to the output terminal of the coil in the trip unit.

[0015] In one embodiment, the control circuit of the trip unit further includes a rectifier unit, a first power processing unit, and a second power processing unit.

[0016] The input terminal of the rectifier unit is used to connect to AC voltage, and the output terminal of the rectifier unit is electrically connected to the input terminal of the first power processing unit and the input terminal of the second power processing unit, respectively.

[0017] The output terminal of the first power processing unit is electrically connected to the power supply terminal of the control chip, and is used to output the first operating voltage to the power supply terminal of the control chip.

[0018] The output terminal of the second power supply processing unit is electrically connected to the second terminal of the pull-up resistor and the source of the PMOS transistor, respectively, to output a second operating voltage to the second terminal of the pull-up resistor and the source of the PMOS transistor.

[0019] In one embodiment, the first power processing unit includes a first voltage divider resistor;

[0020] The first end of the first voltage divider resistor is electrically connected to the output terminal of the rectifier unit, and the second end of the first voltage divider resistor is electrically connected to the power supply terminal of the control chip.

[0021] In one embodiment, the second power processing unit includes a step-down resistor and a Zener diode;

[0022] The first end of the step-down resistor is electrically connected to the output end of the rectifier unit. The second end of the step-down resistor is electrically connected to the cathode of the Zener diode, the second end of the pull-up resistor, and the source of the PMOS transistor. The anode of the Zener diode is grounded.

[0023] In one embodiment, the control circuit of the trip unit further includes a residual current acquisition unit;

[0024] The residual current acquisition unit is electrically connected to the input terminal of the control chip and is used to acquire the residual current of the circuit controlled by the trip unit and feed it back to the control chip.

[0025] In one embodiment, the residual current acquisition unit includes a current transformer, a current action value adjustment resistor, and a bidirectional diode.

[0026] The first terminal of the current transformer is electrically connected to the first terminal of the current operating value adjustment resistor, the first terminal of the bidirectional diode, and the first input terminal of the control chip, respectively. The second terminal of the current transformer is electrically connected to the second terminal of the current operating value adjustment resistor, the second terminal of the bidirectional diode, and the second input terminal of the control chip, respectively.

[0027] Current transformers are used to collect the residual current in the circuit controlled by the trip unit.

[0028] Secondly, in one embodiment, the present invention provides a circuit breaker system, the circuit breaker system including a trip unit and a control circuit for the trip unit in any of the above embodiments.

[0029] Through the control circuit and circuit breaker system of the aforementioned trip unit, a first NMOS transistor and a PMOS transistor are configured. The control chip can output a trip signal according to the first working voltage, thereby controlling the first NMOS transistor and the PMOS transistor to conduct, and then controlling the conduction of the line between the second working voltage and the second NMOS transistor. Since the control chip and the PMOS transistor are respectively connected to the corresponding first working voltage and second working voltage, the power supply for driving the second NMOS transistor and the power supply for the control chip are independent of each other. The first NMOS transistor and the PMOS transistor do not need to withstand high voltage. Therefore, even when the voltage value of the trip signal output by the control chip is low, it can still control the first NMOS transistor and the PMOS transistor to conduct. Thus, it is only necessary to make the second working voltage meet the driving requirements of the second NMOS transistor to drive the second NMOS transistor. This allows the second NMOS transistor to be driven even when the voltage value of the trip signal output by the control chip is low, thereby improving the reliability of the trip control. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the control circuit of the trip unit in one embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the control circuit of a trip unit including a reverse protection diode, a freewheeling diode and a varistor in one embodiment of the present invention;

[0033] Figure 3This is a schematic diagram of the surge protection unit and the rectifier unit in one embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the control circuit of the trip unit, which includes the specific structure of the residual current acquisition unit and the specific structure of the first power processing unit, in one embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the structure of the second power processing unit in one embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0037] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified. In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to implement and use this invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this invention can be implemented without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of this invention with unnecessary detail. Therefore, this invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0038] Firstly, such as Figure 1 As shown, in one embodiment, the present invention provides a control circuit for a trip unit. The control circuit for the trip unit includes a control chip IC, a first NMOS transistor Q3, a second NMOS transistor Q2, a PMOS transistor Q1, a first pull-down resistor R14, a second pull-down resistor R13, and a pull-up resistor R11.

[0039] In this configuration, the output terminal OS of the control chip IC is electrically connected to the first terminal of the first pull-down resistor R14 and the gate of the first NMOS transistor Q3. The drain of the first NMOS transistor Q3 is electrically connected to the first terminal of the pull-up resistor R11 and the gate of the PMOS transistor Q1. The drain of the PMOS transistor Q1 is electrically connected to the first terminal of the second pull-down resistor R13 and the gate of the second NMOS transistor Q2. The drain of the second NMOS transistor Q2 is electrically connected to the output terminal of the coil in the trip unit KA. The power supply terminal VDD of the control chip IC is used to connect to the first operating voltage (such as +5V). The second terminal of the pull-up resistor R11 and the source of the PMOS transistor Q1 are used to connect to the second operating voltage (such as +12V). The second terminal of the first pull-down resistor R14, the source of the first NMOS transistor Q3, the second terminal of the second pull-down resistor R13, and the source of the second NMOS transistor Q2 are grounded.

[0040] When the control chip IC does not output a high-level trip signal, the gate of the first NMOS transistor Q3 is connected to a low level due to the presence of the first pull-down resistor R14, and Q3 is cut off. The gate of the PMOS transistor Q1 is connected to a high level due to the presence of the pull-up resistor R11, and Q1 is cut off. The gate of the second NMOS transistor Q2 is connected to a low level due to the presence of the second pull-down resistor R13, and Q2 is cut off. The voltage VCC connected to the input terminal of the coil in the trip unit KA cannot form a current loop to ground through the trip unit KA and the second NMOS transistor Q2. At this time, there is no large current in the trip unit KA, and the trip unit KA does not perform the trip action.

[0041] When the control chip IC outputs a high-level trip signal, the gate of the first NMOS transistor Q3 is connected to a high level, and Q3 is turned on. Due to the presence of the pull-up resistor R11, the gate of the PMOS transistor Q1 is connected to a low level, and Q1 is turned on. The gate of the second NMOS transistor Q2 is connected to a high level, and Q2 is turned on. The voltage VCC connected to the input terminal of the coil in the trip unit KA can form a current loop to ground through the trip unit KA and the second NMOS transistor Q2. At this time, there is a large current in the trip unit KA, and the trip unit KA performs the trip action.

[0042] Through the control circuit of the aforementioned trip unit, a first NMOS transistor Q3 and a PMOS transistor Q1 are configured. The control chip can output a trip signal according to the first working voltage, thereby controlling the first NMOS transistor Q3 and the PMOS transistor Q1 to conduct, and then controlling the connection between the second working voltage and the second NMOS transistor Q2. Since the control chip and the PMOS transistor Q1 are respectively connected to the corresponding first working voltage and second working voltage, the power supply for driving the second NMOS transistor Q2 and the power supply for the control chip are independent of each other. The first NMOS transistor Q3 and the PMOS transistor Q1 do not need to withstand high voltage. Therefore, even when the voltage value of the trip signal output by the control chip is low, it can still control the first NMOS transistor Q3 and the PMOS transistor Q1 to conduct. Thus, as long as the second working voltage meets the driving requirements of the second NMOS transistor Q2, the second NMOS transistor Q2 can be driven. This allows the second NMOS transistor Q2 to be driven even when the voltage value of the trip signal output by the control chip is low, thus improving the reliability of the trip control.

[0043] like Figure 2 As shown, in one embodiment, the control circuit of the trip unit further includes a reverse protection diode D2.

[0044] In this configuration, the anode of the anti-reverse diode D2 is electrically connected to the drain of the PMOS transistor Q1, and the cathode of the anti-reverse diode D2 is electrically connected to the first terminal of the second pull-down resistor R13 and the gate of the second NMOS transistor Q2, respectively.

[0045] In this embodiment, the second NMOS transistor Q2 is connected in series with the trip unit KA. Its environment is relatively high-voltage. When the second NMOS transistor Q2 fails, such as due to a short circuit, high voltage and high current will flow back to the control chip IC, the first NMOS transistor Q3, and the PMOS transistor Q1. These devices are not capable of withstanding high voltage and high current, making them susceptible to damage. Therefore, in this embodiment, a corresponding anti-reverse diode D2 is added to address this issue. Utilizing the unidirectional conduction characteristic of a diode, even if the second NMOS transistor Q2 fails, high voltage and high current cannot flow back to the control chip IC, the first NMOS transistor Q3, and the PMOS transistor Q1, thus providing protection.

[0046] like Figure 2 As shown, in one embodiment, the control circuit of the trip unit further includes a varistor RV4.

[0047] The first end of the varistor RV4 is electrically connected to the drain of the second NMOS transistor Q2, and the second end of the varistor RV4 is electrically connected to the source of the second NMOS transistor Q2.

[0048] While the second NMOS transistor Q2 is capable of withstanding high voltage, it can still be damaged if the voltage across it is too high, such as during a lightning strike. Therefore, in this embodiment, a varistor RV4 is added to address this issue. When the voltage is below the rated voltage of varistor RV4, it exhibits a high resistance value, allowing only a small current to flow. However, when the voltage exceeds its rated voltage, the resistance of varistor RV4 decreases rapidly, forming a low-impedance path that allows the overvoltage to flow through, thereby protecting the second NMOS transistor Q2.

[0049] like Figure 2 As shown, in one embodiment, the control circuit of the trip unit further includes a freewheeling diode VD9.

[0050] The cathode of the freewheeling diode VD9 is electrically connected to the input terminal of the coil in the trip unit KA, and the anode of the freewheeling diode VD9 is electrically connected to the output terminal of the coil in the trip unit KA.

[0051] Among them, the trip unit KA is an inductive load. When the current changes suddenly, it will generate a sudden voltage due to the energy stored in it. The freewheeling diode VD9 is connected in reverse parallel across the trip unit KA, which can provide a freewheeling circuit for the trip unit KA, thereby dissipating the energy stored in the trip unit KA and preventing the reverse electromotive force generated during tripping from damaging the second NMOS transistor Q2.

[0052] In one embodiment, the control circuit of the trip unit further includes a rectifier unit, a first power processing unit, and a second power processing unit.

[0053] The input terminal of the rectifier unit is used to connect to AC voltage, and the output terminal of the rectifier unit is electrically connected to the input terminals of the first power processing unit and the second power processing unit, respectively.

[0054] The circuit breaker system typically uses AC voltage to power its internal components, thus requiring a corresponding rectifier unit. The rectifier unit rectifies the AC voltage to obtain a corresponding DC voltage, which is then supplied to the first power processing unit and the second power processing unit, respectively.

[0055] Since the control chip and the second NMOS transistor require different operating voltages, corresponding first power processing units and second power processing units need to be set up respectively.

[0056] The output terminal of the first power processing unit is electrically connected to the power supply terminal of the control chip, and is used to output the first operating voltage to the power supply terminal of the control chip.

[0057] The first power processing unit can convert the DC voltage output by the rectifier unit according to the power supply requirements of the control chip, thereby outputting the corresponding first operating voltage to the control chip.

[0058] The output terminal of the second power supply processing unit is electrically connected to the second terminal of the pull-up resistor and the source of the PMOS transistor, respectively, to output a second operating voltage to the second terminal of the pull-up resistor and the source of the PMOS transistor.

[0059] The second power supply processing unit can convert the DC voltage output by the rectifier unit according to the power supply requirements of the second NMOS transistor, thereby outputting the corresponding second working voltage to the pull-up resistor and PMOS transistor, and then transmitting the second working voltage to the second NMOS transistor through the pull-up resistor and PMOS transistor.

[0060] like Figure 3 As shown, in one embodiment, the rectifier unit includes rectifier diodes VD1, VD2, VD3, VD4, VD5, VD6, VD7, and VD8.

[0061] Specifically, the anode of rectifier diode VD1 and the cathode of rectifier diode VD2 are connected to the N phase of the three-phase four-wire AC power supply, the anode of rectifier diode VD3 and the cathode of rectifier diode VD4 are connected to the A phase of the three-phase four-wire AC power supply, the anode of rectifier diode VD5 and the cathode of rectifier diode VD6 are connected to the B phase of the three-phase four-wire AC power supply, and the anode of rectifier diode VD7 and the cathode of rectifier diode VD8 are connected to the C phase of the three-phase four-wire AC power supply. The cathodes of rectifier diodes VD1, VD3, VD5, and VD7 are connected to the input terminal of the coil in trip unit KA to output DC voltage VCC. The anodes of rectifier diodes VD2, VD4, VD6, and VD8 are grounded.

[0062] Since the circuit uses three-phase four-wire AC power, it requires eight rectifier diodes to form a bridge rectifier.

[0063] In one embodiment, the control circuit of the trip unit further includes a surge protection unit, such as... Figure 3 As shown, the surge protection unit includes varistors RV1, RV2, and RV3.

[0064] Among them, varistor RV3 is electrically connected between phase A and phase N of the three-phase four-wire AC power supply, varistor RV2 is electrically connected between phase B and phase N of the three-phase four-wire AC power supply, and varistor RV1 is electrically connected between phase C and phase N of the three-phase four-wire AC power supply.

[0065] Among them, varistors RV1, RV2, and RV3 are used to protect the surge voltage on the corresponding phase, preventing it from flowing to the downstream stage and damaging the relevant devices.

[0066] like Figure 3 and Figure 4 As shown, in one embodiment, the first power processing unit includes a first voltage divider resistor (including resistor R5 and resistor R6) and a second voltage divider resistor.

[0067] Among them, the first end of resistor R6 is electrically connected to the output end of the rectifier unit through the trip unit KA to connect to the DC voltage NET_DC. The second end of resistor R6 is electrically connected to the first end of resistor R5. The second end of resistor R5 is electrically connected to the power supply terminal VDD of the control chip IC and the first end of the second voltage divider resistor to output a first working voltage of +5V. The second end of the second voltage divider resistor is grounded.

[0068] Among them, Figure 4 In this embodiment, the second voltage divider resistor is located inside the control chip IC. Therefore, the specific connection relationship of the second voltage divider resistor is not shown. However, it can be understood that the first and second voltage divider resistors form a resistor divider network, providing the divided voltage to the power supply terminal VDD of the control chip IC. Of course, in other embodiments, the second voltage divider resistor can also be located outside the control chip IC.

[0069] like Figure 3 , Figure 4 and Figure 5 As shown, in one embodiment, the second power processing unit includes a step-down resistor (including resistors R4 and R8) and a Zener diode ZD1.

[0070] The first end of resistor R4 is electrically connected to the output of the rectifier unit through trip unit KA to receive DC voltage NET_DC. The second end of resistor R4 is electrically connected to the first end of resistor R8. The second end of resistor R8 is electrically connected to the cathode of Zener diode ZD1, the second end of pull-up resistor R11, and the source of PMOS transistor Q1 to output a second working voltage of +12V. The anode of Zener diode ZD1 is grounded.

[0071] The Zener diode ZD1 has a Zener voltage of 12V, enabling it to output a second operating voltage of +12V to the subsequent stage. Of course, in other scenarios, depending on the power supply requirements of the second NMOS transistor Q2, a Zener diode with a Zener voltage of 9V or 13V can also be used.

[0072] The second power processing unit also includes a filter capacitor C9, which is used to filter out noise signals.

[0073] like Figure 3 , Figure 4 and Figure 5 As shown, the rectifier unit uses a trip unit KA to generate a DC voltage NET_DC. This DC voltage NET_DC is output to resistor R6 in the first power processing unit, resistor R4 in the second power processing unit, and the second NMOS transistor Q2. When the second NMOS transistor Q2 is in the off state, although the trip unit KA can form a current loop to ground through the first and / or second power processing units, the high impedance in this loop results in a small current flowing through the trip unit KA, thus failing to trip. When the second NMOS transistor Q2 is in the on state, it short-circuits both the first and second power processing units, reducing the impedance in the loop and allowing a larger current to flow through the trip unit KA, thus enabling tripping.

[0074] In one embodiment, the control circuit of the trip unit further includes a residual current acquisition unit.

[0075] The residual current acquisition unit is electrically connected to the input terminal of the control chip and is used to acquire the residual current of the circuit controlled by the trip unit and feed it back to the control chip.

[0076] The control chip can determine whether to perform a tripping operation based on the residual current. When the residual current is too large, the safety hazard is high, so a tripping operation is required, which enables the control chip to control the trip unit to trip through the subsequent devices.

[0077] like Figure 4 As shown, in one embodiment, the residual current acquisition unit includes a current transformer connected via terminals TA1 and TA2, a current operating value adjustment resistor (including resistor R1* and resistor R1), and a bidirectional diode D1.

[0078] The first terminal of the current transformer (e.g., terminal TA1) is electrically connected to the first terminal of resistor R1*, the first terminal of resistor R1, the first terminal of bidirectional diode D1, and the first input terminal In1 of the control chip IC. The second terminal of the current transformer (e.g., terminal TA2) is electrically connected to the second terminal of resistor R1*, the second terminal of resistor R1, the second terminal of bidirectional diode D1, and the second input terminal In2 of the control chip IC.

[0079] The current transformer is used to collect the residual current of the circuit controlled by the trip unit.

[0080] Among them, resistors R1* and R1 can be adjusted according to the residual current operating value.

[0081] The bidirectional diode D1 can be internally composed of two Zener diodes, thereby ensuring that the voltage output to the control chip IC is controlled within an appropriate range.

[0082] It should be noted that, Figure 4 The resistors R2, R3, R12, C1, C2, C3, C4, C5, C6, and C7 shown are all basic components that realize the basic functions of the circuit. Their specific principles will not be elaborated here.

[0083] Secondly, in one embodiment, the present invention provides a circuit breaker system, the circuit breaker system including a trip unit and a control circuit for the trip unit in any of the above embodiments.

[0084] By using the circuit breaker system described above, a first NMOS transistor and a PMOS transistor are configured. The control chip can output a trip signal based on the first operating voltage, thereby controlling the first NMOS transistor and the PMOS transistor to conduct, and further controlling the connection between the second operating voltage and the second NMOS transistor. Since the control chip and the PMOS transistor are respectively connected to the corresponding first and second operating voltages, the power supply for driving the second NMOS transistor and the power supply for the control chip are independent of each other. The first NMOS transistor and the PMOS transistor do not need to withstand high voltage. Therefore, even when the voltage value of the trip signal output by the control chip is low, it can still control the first NMOS transistor and the PMOS transistor to conduct. Thus, it is only necessary to ensure that the second operating voltage meets the driving requirements of the second NMOS transistor to drive it. This allows the second NMOS transistor to be driven even when the voltage value of the trip signal output by the control chip is low, thereby improving the reliability of the trip control.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0086] The control circuit and circuit breaker system of the trip unit provided by this utility model have been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A control circuit for a trip unit, characterized in that, The control circuit of the trip unit includes a control chip, a first NMOS transistor, a second NMOS transistor, a PMOS transistor, a first pull-down resistor, a second pull-down resistor, and a pull-up resistor; The output terminal of the control chip is electrically connected to the first terminal of the first pull-down resistor and the gate of the first NMOS transistor, respectively. The drain of the first NMOS transistor is electrically connected to the first terminal of the pull-up resistor and the gate of the PMOS transistor, respectively. The drain of the PMOS transistor is electrically connected to the first terminal of the second pull-down resistor and the gate of the second NMOS transistor, respectively. The drain of the second NMOS transistor is used to be electrically connected to the output terminal of the coil in the trip unit. The power supply terminal of the control chip is used to connect to the first working voltage. The second terminal of the pull-up resistor and the source of the PMOS transistor are respectively used to connect to the second working voltage. The second terminal of the first pull-down resistor, the source of the first NMOS transistor, the second terminal of the second pull-down resistor, and the source of the second NMOS transistor are respectively grounded.

2. The control circuit of the trip unit according to claim 1, characterized in that, The control circuit of the trip unit also includes a reverse protection diode; The anode of the anti-reverse diode is electrically connected to the drain of the PMOS transistor, and the cathode of the anti-reverse diode is electrically connected to the first terminal of the second pull-down resistor and the gate of the second NMOS transistor, respectively.

3. The control circuit of the trip unit according to claim 1, characterized in that, The control circuit of the trip unit also includes a varistor; The first end of the varistor is electrically connected to the drain of the second NMOS transistor, and the second end of the varistor is electrically connected to the source of the second NMOS transistor.

4. The control circuit of the trip unit according to claim 1, characterized in that, The control circuit of the trip unit also includes a freewheeling diode; The cathode of the freewheeling diode is electrically connected to the input terminal of the coil in the trip unit, and the anode of the freewheeling diode is electrically connected to the output terminal of the coil in the trip unit.

5. The control circuit of the trip unit according to any one of claims 1-4, characterized in that, The control circuit of the trip unit also includes a rectifier unit, a first power processing unit, and a second power processing unit. The input terminal of the rectifier unit is used to connect to AC voltage, and the output terminal of the rectifier unit is electrically connected to the input terminal of the first power processing unit and the input terminal of the second power processing unit, respectively. The output terminal of the first power processing unit is electrically connected to the power supply terminal of the control chip, and is used to output the first operating voltage to the power supply terminal of the control chip; The output terminal of the second power processing unit is electrically connected to the second terminal of the pull-up resistor and the source of the PMOS transistor, respectively, for outputting the second operating voltage to the second terminal of the pull-up resistor and the source of the PMOS transistor.

6. The control circuit of the trip unit according to claim 5, characterized in that, The first power processing unit includes a first voltage divider resistor; The first end of the first voltage divider resistor is electrically connected to the output terminal of the rectifier unit, and the second end of the first voltage divider resistor is connected to the power supply terminal of the control chip.

7. The control circuit of the trip unit according to claim 5, characterized in that, The second power processing unit includes a step-down resistor and a Zener diode; The first end of the step-down resistor is electrically connected to the output end of the rectifier unit, the second end of the step-down resistor is electrically connected to the cathode of the Zener diode, the second end of the pull-up resistor and the source of the PMOS transistor, and the anode of the Zener diode is grounded.

8. The control circuit of the trip unit according to claim 1, characterized in that, The control circuit of the trip unit also includes a residual current acquisition unit; The residual current acquisition unit is electrically connected to the input terminal of the control chip and is used to acquire the residual current of the circuit controlled by the trip unit and feed it back to the control chip.

9. The control circuit of the trip unit according to claim 8, characterized in that, The residual current acquisition unit includes a current transformer, a current action value adjustment resistor, and a bidirectional diode. The first terminal of the current transformer is electrically connected to the first terminal of the current action value adjustment resistor, the first terminal of the bidirectional diode, and the first input terminal of the control chip, respectively; the second terminal of the current transformer is electrically connected to the second terminal of the current action value adjustment resistor, the second terminal of the bidirectional diode, and the second input terminal of the control chip, respectively. The current transformer is used to collect the residual current of the circuit controlled by the trip unit.

10. A circuit breaker system, characterized in that, The circuit breaker system includes a trip unit and a control circuit for the trip unit as described in any one of claims 1 to 8.

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