Imaging sensor chip with symmetrical left and right edge pixel-free areas

Abstract

The utility model discloses an imaging sensor chip with symmetrical left and right edge pixel-free areas. The imaging sensor chip comprises a standard pixel column, a non-standard pixel column and a row gating circuit. Wherein the standard pixel column comprises standard pixels, the non-standard pixel column comprises pixels, and the photosensitive range of the non-standard pixels is smaller than that of the standard pixels. The row gating circuit is arranged on one side of the non-standard pixel column. According to the imaging sensor chip provided by the utility model, the arrangement position of the row gating circuit is moved from the edge part of a traditional imaging sensor to the position between the pixel columns in the middle area, so that non-pixel areas and splicing seams on the left side and the right side of the imaging sensor chip are reduced, and an original image with less missing range is provided for subsequent image processing and reconstruction.

Description

Technical Field

[0001] This utility model relates to an imaging sensor chip with symmetrical left and right edge pixel-free areas, belonging to the field of sensor technology. Background Technology

[0002] CMOS imaging sensors have wide applications in visible light imaging, remote sensing imaging, and medical imaging. Due to their high sensitivity, low noise, and fast readout, CMOS imaging detectors are the preferred imaging sensors in various current imaging designs. In medical imaging, CMOS imaging sensors are widely used in digital X-ray radiography, digital fluoroscopy, and CT imaging due to their excellent image quality and tolerance to low-dose radiation. CMOS imaging sensor chips require row gating circuits, coordinated with external timing mechanisms, to ensure that each row opens and closes according to a predetermined pattern, guaranteeing the regular transfer of integrated charge to the integrator. Currently, the row gating circuits of existing CMOS imaging sensor chips are located on one edge of the left or right side of the chip (correspondingly, the peripheral circuit area is on the bottom), and due to the space requirements of the row gating circuit board design, they occupy a certain width at the chip edge. Because the row gating circuit increases the width of the chip outside the effective pixel area, it increases the size of the pixelless area between chips when multiple chips are stitched together, causing this area to be unimageable. Furthermore, because the width of the pixelless areas on the left and right sides of the chip is different, the pixelless dimensions on the left and right sides of the chip are inconsistent when multiple chips are spliced ​​together, which makes it difficult to align the pixel columns of the upper and lower rows of chips.

[0003] Chinese patent application No. 202311152866.X discloses a readout pixel chip for a pixel detector. This readout pixel chip includes a readout pixel array area, a peripheral circuit area, and an I / O pin area. The readout pixel array area is rectangular, the peripheral circuit area includes partitions distributed along multiple edges of the readout pixel array area, and the I / O pin area includes partitions distributed along multiple edges of the readout pixel array area. This readout pixel chip aims to optimize the circuit design at the edges of the readout pixel chip, reduce the circuit area occupied, and minimize the detection dead zone when stitching together multiple pixel detectors. However, it still cannot obtain a true image of the stitched area.

[0004] Due to the limitations of wafer size in manufacturing CMOS imaging sensors, large-sized single imaging detectors cannot be fabricated. To use large-size or wide-width CMOS imaging sensors, multi-chip stitching is necessary. Controlling the stitching gap size between the effective imaging areas of each chip is crucial during multi-chip stitching, as this area contains no imaging pixels and is considered a non-effective image sampling area. If this gap is too large, it will severely impact subsequent image processing and reconstruction. Therefore, effectively controlling and reducing the stitching gap becomes a key technology in the stitching of large-size CMOS detectors. Summary of the Invention

[0005] The technical problem to be solved by this utility model is to provide an imaging sensor chip with symmetrical left and right edge pixel-free areas.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solution:

[0007] An imaging sensor chip with symmetrical left and right edge pixel-free areas includes standard pixel columns, non-standard pixel columns, and row gating circuits; wherein,

[0008] The standard pixel column includes standard pixels, the non-standard pixel column includes non-standard pixels, and the photosensitive range of the non-standard pixels is smaller than that of the standard pixels;

[0009] The row selection circuit is arranged on one side of the non-standard pixel column.

[0010] Preferably, the imaging sensor chip includes multiple columns of standard pixel columns, one column of non-standard pixel columns, and one column of row gating circuits; the row gating circuits are arranged between the non-standard pixel columns and the standard pixel columns.

[0011] Preferably, the imaging sensor chip includes multiple columns of standard pixel columns, multiple columns of non-standard pixel columns, and a row gating circuit; the row gating circuit is arranged between the non-standard pixel columns.

[0012] Preferably, the imaging sensor chip includes multiple columns of standard pixel columns, multiple columns of non-standard pixel columns, and multiple columns of row gating circuits; the multiple columns of row gating circuits can serve as backups for each other.

[0013] Preferably, the row gating circuit is arranged between the non-standard pixel column and the standard pixel column; the multiple row gating circuits are spaced apart by multiple columns of the standard pixel column.

[0014] Preferably, the row gating circuit is arranged between the non-standard pixel column and the standard pixel column; the multiple row gating circuits are spaced apart by multiple columns of the standard pixel column and the non-standard pixel column.

[0015] Preferably, the row gating circuits are arranged between the non-standard pixel columns; multiple rows of the row gating circuits are spaced apart by multiple columns of the standard pixel columns and the non-standard pixel columns.

[0016] Preferably, the pixel-free areas on the left and right sides of the imaging sensor chip are no larger than 50μm.

[0017] Preferably, the photosensitive range of the non-standard pixel is 70% to 80% of that of the standard pixel.

[0018] Preferably, the number of non-standard pixels in the non-standard pixel column is the same as the number of standard pixels in the standard pixel column; the standard pixels and non-standard pixels in each row are aligned.

[0019] Compared with existing technologies, this invention provides a novel spatial arrangement structure for an integrating imaging sensor chip, reducing the size of the left and right edges of the chip. This technical solution effectively reduces the size of the pixel-free area during chip stitching and ensures that the stitching gap size on both sides of the chip is the same after stitching, providing a raw image with less missing areas for subsequent image processing and reconstruction. By moving the row gating circuit from the traditional edge of the imaging sensor to the pixel edge in the middle region, two columns of row gating circuits can be arranged simultaneously without increasing the size of the edge of the imaging sensor chip. If one column of row gating circuits fails, the other can be used as a backup. Furthermore, the row gating section in the middle region, due to the special process used, has no impact on pixel light sensitivity and does not introduce new bad lines. Because the row gating circuit is placed in the middle region, the size of the pixel-free area on both sides of the imaging sensor chip is completely identical, achieving mirror symmetry and ensuring the alignment of the pixel columns during chip stitching. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of an imaging sensor chip with symmetrical left and right edge pixel-free areas, as shown in the first embodiment of this utility model. Detailed Implementation

[0021] The technical content of this utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The technical concept of this embodiment is to arrange row selection circuits between columns of photosensitive pixels to reduce the pixel-free areas on the left and right sides of the imaging sensor chip. Specifically, the photosensitive range of any column of photosensitive pixels is reduced to 70% to 80% of its original range, and the row selection circuit of the imaging sensor chip is arranged between the pixels in that column and the adjacent columns. After imaging, the pixels in that column can undergo brightness difference coefficient correction through software calculation to compensate for missing brightness, ensuring that the pixels in that column can be used in subsequent image data and can still be used as normal pixels for imaging.

[0023] It should be noted that the left and right sides of the chip proposed in this embodiment refer to the side where the peripheral circuits and I / O pin areas are arranged, with the bottom side considered. In other words, splicing multiple imaging sensor chips means splicing the left and right sides of adjacent imaging sensor chips together.

[0024] First Embodiment

[0025] The core of an imaging sensor chip is an array of pixel circuits (hereinafter referred to as pixels), with the I / O circuits located at the bottom of the chip. Each row of pixels in the pixel array is driven by a row gating circuit; this is well-known technology and will not be described further.

[0026] like Figure 1 As shown, the imaging sensor chip includes standard pixel 1, non-standard pixel 2, and row selection circuit 3. Standard pixel 1 and non-standard pixel 2 are collectively referred to as pixels, which together constitute the pixel array of the imaging sensor chip. Standard pixel 1 is a pixel with its full light-sensitive range, while non-standard pixel 2 is a pixel with a reduced light-sensitive range. Preferably, the light-sensitive range of non-standard pixel 2 is 70% to 80% of that of standard pixel 1.

[0027] Multiple standard pixels 1 are arranged vertically at equal intervals to form a standard pixel column 11. Multiple non-standard pixels 2 are arranged vertically at equal intervals to form a non-standard pixel column 21. The number of non-standard pixels 2 in non-standard pixel column 21 is the same as the number of standard pixels 1 in standard pixel column 11. Pixels of the same position in each column are aligned horizontally, that is, the standard pixels 1 and non-standard pixels 2 in each row are aligned.

[0028] The imaging sensor chip provided in this embodiment includes a non-standard pixel column 21 and multiple standard pixel columns 11. The non-standard pixel column 21 is located between any two adjacent standard pixel columns 11. In other words, in a pixel array composed mostly of standard pixels 1, a certain column is a non-standard pixel column 21 composed of non-standard pixels 2.

[0029] The row gating circuit 3 is arranged between the non-standard pixel column 21 and the adjacent standard pixel column 11, along the column direction. The row gating circuit 3 can drive the pixels in each row of the array.

[0030] In existing technologies, the row gating circuit is located on the left or right side of the imaging sensor chip, occupying a width of 300μm or more. This results in unequal widths of the pixel-free areas on the left and right sides of the chip, affecting the image quality after stitching. For example, if one edge is a row gating circuit and the other edge is a pixel, the row gating circuit portion cannot be photosensitive, limiting the effective photosensitive area of ​​the image. The unsensitized portion can only be simulated using an interpolation algorithm. Alternatively, the unequal widths of the two edges can also affect the simulation effect of the image interpolation algorithm.

[0031] The imaging sensor chip provided in this embodiment is manufactured using advanced semiconductor processes, such as 180nm. The spacing between standard pixels 1 is approximately zero, with a single standard pixel 1 having a width of 255μm as an example. The light-sensing range of non-standard pixels 2 is 70% to 80% of that of standard pixels 1. The difference in arrangement space between the two meets the requirements for arranging the row selection circuit 3. After imaging, the non-standard pixels 2 can undergo brightness difference coefficient correction through software calculation to compensate for missing brightness. This ensures that the non-standard pixels 2 can be used in subsequent image data and can still be used as normal pixels for imaging without adding bad lines. Therefore, the pixel-free areas on the left and right sides of the imaging sensor chip are reduced to 50μm or less, with the same width, i.e., symmetrical.

[0032] Therefore, the imaging sensor chip provided in this embodiment, which arranges the row selection circuit 3 between the pixel columns, has the following advantages: ① It reduces the pixel-free areas on the left and right sides of the imaging sensor chip by 300μm or more, and reduces the seam width after the left and right sides of adjacent imaging sensor chips are stitched together to 255μm (the width of a standard pixel 1) or less; ② Non-pixel circuits are no longer arranged on the left and right sides of the imaging sensor chip, so the pixel-free areas on the left and right sides after the chip is cut are equal in width, which facilitates imaging compensation after left and right stitching; ③ The consistency of the seam width of the imaging sensor chip can ensure the alignment of pixels in the column direction during the length stitching extension of subsequent image processing.

[0033] Based on the above advantages, the imaging sensor chip provided in this embodiment can provide original images with less missing range for subsequent image processing and reconstruction.

[0034] Second embodiment

[0035] Unlike the embodiments described above, the imaging sensor chip provided in this embodiment includes two columns of non-standard pixel columns 21, multiple columns of standard pixel columns 11, and a row gating circuit 3. The two columns of non-standard pixel columns 21 are adjacent pixel columns. The row gating circuit 3 is arranged between the two adjacent columns of non-standard pixel columns 21.

[0036] The light-sensing range of the two adjacent non-standard pixels 2 is smaller than that of the standard pixel 1, so the spacing between the two adjacent non-standard pixel columns 21 is larger, which meets the needs of arranging the row selection circuit 3.

[0037] After imaging, the non-standard pixel 2 can still be used as a normal pixel image because the missing brightness is compensated by software calculation.

[0038] Third embodiment

[0039] Unlike the embodiments described above, the imaging sensor chip provided in this embodiment includes multiple columns of non-standard pixel columns 21, multiple columns of standard pixel columns 11, and multiple rows of gating circuits 3. The rows of gating circuits 3 are arranged between two adjacent columns of non-standard pixel columns 21, or between adjacent columns of standard pixel columns 11 and non-standard pixel columns 21. The multiple rows of gating circuits 3 are spaced apart by multiple columns of standard pixel columns 11 and / or columns of non-standard pixel columns 21. The multiple rows of gating circuits 3 can collaboratively drive each row of pixels, or serve as backups for each other.

[0040] Taking this embodiment as an example, which includes two rows of gating circuits 3, the two rows of gating circuits 3 can drive each row of pixels in a coordinated manner, and can also be used in one position and used as backup for each other.

[0041] In summary, the present invention provides an imaging sensor chip with symmetrical pixel-free areas on the left and right edges. By moving the row selection circuit from the edge of the traditional imaging sensor to between the pixel columns in the middle region, the pixel-free areas and stitching seams on the left and right sides of the imaging sensor chip are reduced, providing a raw image with less missing range for subsequent image processing and reconstruction.

[0042] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of the various embodiments can be combined, and all are within the protection scope of this utility model.

[0043] The terms “up,” “down,” “left,” “right,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0044] The above provides a detailed description of an imaging sensor chip with symmetrical pixel-free areas on the left and right edges provided by this utility model. Any obvious modifications made by those skilled in the art without departing from the essential content of this utility model will constitute an infringement of the patent rights of this utility model and will incur corresponding legal liability.

Claims

1. An imaging sensor chip with symmetrical left and right edge pixel-free regions, characterized in that... This includes standard pixel columns, non-standard pixel columns, and row gating circuits; among which, The standard pixel column includes standard pixels, the non-standard pixel column includes non-standard pixels, and the photosensitive range of the non-standard pixels is smaller than that of the standard pixels; The non-standard pixel column is located between the two standard pixel columns; the row gating circuit is arranged on one side of the non-standard pixel column.

2. The imaging sensor chip as described in claim 1, characterized in that... It includes multiple columns of standard pixels, one column of non-standard pixels, and one column of row gating circuits; the row gating circuits are arranged between the non-standard pixel columns and the standard pixel columns.

3. The imaging sensor chip as described in claim 1, characterized in that... It includes multiple columns of standard pixel columns, multiple columns of non-standard pixel columns, and one column of row gating circuit; the row gating circuit is arranged between the non-standard pixel columns.

4. The imaging sensor chip as described in claim 1, characterized in that... It includes multiple columns of standard pixel columns, multiple columns of non-standard pixel columns, and multiple columns of row gating circuits; the multiple columns of row gating circuits can be used as backups for each other.

5. The imaging sensor chip as described in claim 4, characterized in that: The row gating circuit is arranged between the non-standard pixel column and the standard pixel column; multiple rows of the row gating circuit are spaced apart by multiple columns of the standard pixel column.

6. The imaging sensor chip as described in claim 4, characterized in that: The row gating circuit is arranged between the non-standard pixel column and the standard pixel column; the multiple row gating circuits are spaced apart by multiple columns of the standard pixel column and the non-standard pixel column.

7. The imaging sensor chip as described in claim 4, characterized in that: The row gating circuits are arranged between the non-standard pixel columns; multiple rows of the row gating circuits are spaced apart by multiple columns of the standard pixel columns and the non-standard pixel columns.

8. The imaging sensor chip according to any one of claims 1 to 7, characterized in that: The pixel-free areas on the left and right sides of the imaging sensor chip are no larger than 50μm.

9. The imaging sensor chip according to any one of claims 1 to 7, characterized in that: The photosensitive range of the non-standard pixel is 70% to 80% of that of the standard pixel.

10. The imaging sensor chip as described in claim 1, characterized in that: The number of non-standard pixels in the non-standard pixel column is the same as the number of standard pixels in the standard pixel column; the standard pixels and non-standard pixels in each row are aligned.

Images