Photonic device structure and photonic semiconductor device

Abstract

The utility model provides a photonic device structure and a photonic semiconductor device. The photonic device structure includes a substrate having a top-side oxide layer and a silicon layer on the top-side oxide layer. The photonic device structure also includes a rib waveguide assembly in the silicon layer and including a contact hole. The contact hole includes a contact hole depth and a contact hole trench in the silicon layer and having a first sidewall, a second sidewall and a bottom surface. The contact hole further includes a contact etch stop layer in the contact hole trench.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a photonic device structure and a photonic semiconductor device. Background Technology

[0002] The ribbed waveguide includes contacts extending through the contact etch stop layer to contact the doped region located below. An oxide hard mask or layer deposited on the contact etch stop layer may collapse during patterning of the contact etch stop layer and / or the contacts themselves. Utility Model Content

[0003] According to some embodiments, a photonic device structure is provided. The photonic device structure includes a substrate having a top-side oxide layer and a silicon layer located on the top-side oxide layer. The structure also includes a ribbed waveguide assembly located in the silicon layer and including a plurality of contact holes. Each contact hole includes an upper portion having a first width located in the silicon layer and a lower portion including a contact hole trench located in the silicon layer, the lower portion having a second width narrower than the first width. The contact hole also includes a contact etch stop layer located in the contact hole trench.

[0004] According to some embodiments, a photonic semiconductor device is provided. The photonic semiconductor device includes a substrate and a first top-side oxide layer on the substrate. The device also includes a silicon layer on the first top-side oxide layer. The silicon layer of the photonic semiconductor device includes a first waveguide component, a second waveguide component, and at least one third waveguide component, the third waveguide component including a contact hole. Each contact hole includes an upper portion having a first width in the silicon layer and a lower portion including a contact hole trench in the silicon layer, the lower portion having a second width narrower than the first width. The contact hole also includes a contact etch stop layer located in the contact hole trench.

[0005] According to some embodiments, a photonic semiconductor device is provided. The photonic semiconductor device includes a substrate and a first top-side oxide layer on the substrate. The photonic semiconductor device also includes a silicon layer on the first top-side oxide layer. The silicon layer of the photonic semiconductor device includes a first waveguide component, a second waveguide component, and at least one third waveguide component, the third waveguide component including contact holes. Each contact hole includes an upper portion having a first width in the silicon layer and a lower portion including a contact hole trench in the silicon layer, the lower portion having a second width narrower than the first width. The silicon layer also includes a contact etch stop layer located in the contact hole trench. The photonic semiconductor device also includes a contact oxide layer located in the contact hole trench. The contact oxide layer defines a contact etch stop layer cavity, and the contact etch stop layer is located within the contact etch stop layer cavity. Attached Figure Description

[0006] The appearance of some embodiments of this disclosure will be best understood when read in conjunction with the accompanying drawings, based on the following detailed description. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a cross-sectional view of a photonic device according to some embodiments;

[0008] Figures 2A to 2AD Manufacturing according to some embodiments Figure 1 A cross-sectional view of a section of a photonic device;

[0009] Figures 3A to 3B This is a cross-sectional view of the rib groove according to the first embodiment;

[0010] Figure 3C Show Figures 3A to 3B Top view of the embodiment depicted in the figure;

[0011] Figures 4A to 4B This is a cross-sectional view of the rib groove according to the second embodiment;

[0012] Figures 5A to 5B This is a cross-sectional view of the rib groove according to the third embodiment;

[0013] Figure 6 This is a flowchart of a method for manufacturing a photonic device structure according to some embodiments.

[0014] [Symbol Explanation]

[0015] 100:Photonic device

[0016] 102:Substrate

[0017] 104: Backside oxide layer

[0018] 106: First top-side oxide layer

[0019] 108: Silicon layer

[0020] 110: Distributed Bragg Reflector

[0021] 112: First etch stop layer

[0022] 114: Pillar

[0023] 116: Column cavity

[0024] 118: Waveguide Components

[0025] 120: Waveguide assembly

[0026] 122: Waveguide Components

[0027] 124: Waveguide Components

[0028] 128: Silicate Glass Materials

[0029] 130: Undoped silicate glass assembly

[0030] 132: Etching Stop Layer

[0031] 134: Contact Hole

[0032] 135: Etching Stop Layer Cavity

[0033] 136: Oxide layer

[0034] 137: Trench

[0035] 138: Contact element

[0036] 140: Metal components

[0037] 142: Bump pad

[0038] 144: Thickness

[0039] 146: Thickness

[0040] 147: Thickness

[0041] 148: Light Source

[0042] 150: Facets

[0043] 152: Metal Components

[0044] 154: Second top-side oxide layer

[0045] 156: Second Etching Stop Layer

[0046] 158: Third top side oxide layer

[0047] 160: Third Etching Stop Layer

[0048] 162: Fourth top side oxide layer

[0049] 164: Fourth Etching Stop Layer

[0050] 166: Doped components

[0051] 168: Doped components

[0052] 170: Depth

[0053] 172: Hard Mask

[0054] 174, 180, 184, 188, 192, 194, 196, 198, 200, 202, 204: Photoresist; 176: DBR pores

[0055] 178: Polyimide layer

[0056] 182: Opening

[0057] 186: Strip-shaped pores

[0058] 190: R2S hole

[0059] 206: Contact cavity

[0060] 300, 312, 314: Bottom part

[0061] 302: Top surface

[0062] 304, 305: Sidewall

[0063] 306: Bottom surface

[0064] 308: Width or diameter

[0065] 309: Width or diameter

[0066] 310: Altitude

[0067] 311: Radius

[0068] 600: Flowchart

[0069] 602,604,606,608,610,612,614,616,618,620,622,624,626,628,630,632,634: Steps Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, some embodiments of this disclosure may repeat reference numerals and / or letters in various instances. Such repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, for ease of description, some embodiments of this disclosure may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature and another element(s), as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used in some embodiments of this disclosure may be interpreted accordingly.

[0072] The term "about" can be used to include any numerical value that is variable without altering its essential function. When used with a range, "about" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also indicates a range of "2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0073] Some embodiments disclosed herein relate to structures composed of different layers. When the terms "on" or "above" are used to refer to two different layers (including a substrate), they simply indicate that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other without any layers between them. Additionally, when referring to performing process steps on a substrate, depending on the context, this should be understood as performing such steps on any layers that may be present on the substrate.

[0074] The ribbed waveguide includes contacts extending through the contact etch stop layer to contact a doped region located below. An oxide hard mask or layer deposited on the contact etch stop layer may collapse during patterning of the contact etch stop layer and / or the contacts themselves. According to some embodiments of this disclosure, rib trenches are used to prevent mask collapse during patterning of the etch stop layer.

[0075] Now for reference Figure 1 The image illustrates a photonic device 100 according to one embodiment. Figure 1As shown, the photonic device 100 includes a substrate 102 having a back oxide layer 104 and a first top oxide layer 106. According to some embodiments, the substrate 102 may comprise, for example, but not limited to, silicon, specifically, but not limited to, crystalline or polycrystalline Si. In alternative embodiments, the substrate 102 may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. According to one embodiment, the substrate 102 may be implemented as an SOI substrate, i.e., silicon-on-insulator substrate. In such embodiments, the substrate 102 may comprise, for example, but not limited to, silicon oxide or other suitable insulating materials.

[0076] According to some embodiments, the back oxide layer 104 and the first top oxide layer 106 may comprise, for example, but not limited to, non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. In such embodiments, the back oxide layer 104 and the first top oxide layer 106 may have a thickness 144 in the range of 0.5 μm to 3 μm, and in some embodiments, may have a thickness 144 of 2 μm. Figure 1 As shown, the photonic device 100 also includes a first silicon layer 108 formed on a first top-side oxide layer 106. According to some embodiments, the first silicon layer 108 may comprise silicon, such as, but not limited to, silicon in the form of crystalline Si or polycrystalline Si. According to some embodiments, the first silicon layer 108 may be implemented having a thickness 146 in the range of 1 μm to 5 μm, and in some embodiments, may have a thickness 146 of 3 μm. A distributed Bragg reflector (DBR) 110 is formed on the top portion of the first silicon layer 108, such as... Figure 1 As depicted in the figure. It should be understood that the construction and / or location of the distributed Bragg reflector 110 may depend on the specific application using the photonic device 100, the required wavelength traveling through it, etc.

[0077] Figure 1The photonic device 100 also includes a first etch stop layer 112, which is formed on various portions of the substrate 102 and on additional layers of the photonic device 100, as described in some embodiments of this disclosure. It should be understood that the first etch stop layer 112 may contain any suitable barrier material to protect underlying layers and components from damage during subsequent etching processes. The first etch stop layer 112 may be implemented as tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. It should be understood that the first etch stop layer 112 corresponds to a material layer having etching properties distinctly different from the material to be etched, thereby stopping or halting the etching process of the layers deposited on the etch stop layer. According to one embodiment, a pillar 114 is formed of the material of the first silicon layer 108 on one side of the photonic device 100, such as... Figure 1 As shown. In some embodiments, the support column 114 is positioned adjacent to the support column cavity 116 extending downward into the substrate 102, as... Figure 1 As shown in the illustration. According to such an embodiment, the support 114 can be used to support the light source 148, as discussed in more detail below.

[0078] Figure 1 The photonic device 100 shown also includes an echelle grating assembly (or interchangeably, a waveguide assembly) 118, a strip waveguide assembly 120, a rib-to-strip (R2S) waveguide assembly 122, and a rib waveguide assembly 124. Each of the waveguide assemblies 118-124 is suitably at least partially located in the first silicon layer 108. Figure 1 As shown, silicate glass material 128 is formed within each of waveguide components 118-124, as described below regarding Figures 2A to 2AD A more detailed description. That is, such as... Figure 1 As depicted, silicate glass material 128 may be deposited between portions of the first silicon layer 108, the combination of which provides structure for the aforementioned waveguide components 118-124. According to one exemplary embodiment, silicate glass material 128 is borophosphosilicate glass (BPSG). It should be understood that other suitable silicate glasses or materials providing similar optical and / or insulating properties may be used in other embodiments.

[0079] According to some embodiments, the echelle grating waveguide assembly 118 may correspond to a type of diffraction grating having a relatively low groove density and a groove shape optimized for use at high incident angles, and therefore having a high diffraction order. According to another embodiment, the strip waveguide assembly 120 may correspond to a type of waveguide having the form of a channel extending along the surface of some solid transparent host medium (e.g., a dielectric or semiconductor). The rib-to-strip waveguide assembly 122 may correspond to a converter assembly that converts a rib waveguide output to a strip waveguide input and / or converts a strip waveguide output to a rib waveguide input. Furthermore, as... Figure 1 As shown, the photonic device 100 includes a waveguide assembly 124, which may correspond to a waveguide in which the guiding layer may consist of a base plate and strips (or strips) superimposed thereon. As those skilled in the art will understand, ribbed waveguides can provide confinement of waves in two dimensions, and near-uniform confinement is possible in multi-layered ribbed structures. It should be understood that, although Figure 1 The diagram shows a single ribbed waveguide assembly 124, but depending on the desired design configuration, the photonic device 100 can be implemented with multiple ribbed waveguide assemblies, such as three, four, five, etc. Therefore, Figure 1 The illustrations in the figures are intended only as an illustrative exemplary embodiment of some of the embodiments according to this disclosure.

[0080] like Figure 1 As shown, the photonic device 100 also includes an undoped silicate glass (USG) component 130 disposed on a first silicon layer 108 and a silicate glass material 128. In some embodiments, the undoped silicate glass component 130 may be implemented with a thickness 147 in the range of 5,000 angstroms to 10,000 angstroms. In one embodiment, the undoped silicate glass component 130 has an implanted thickness 147 of 8 angstroms.

[0081] The second etch stop layer 156 is formed on the undoped silicate glass assembly 130, such as Figure 1 As shown. According to some embodiments, the second etch stop layer 156 may include any suitable barrier material to protect the underlying layers and components from damage during subsequent etching processes. The second etch stop layer 156 may be implemented as tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. It should be understood that the second etch stop layer 156 corresponds to a material layer having etching properties that are distinctly different from the material to be etched, thereby stopping or terminating the etching process of the layers deposited on the etch stop layer.

[0082] Above the second etch stop layer 156 is a second top-side oxide layer 154. A third top-side oxide layer 158 is suitably formed on the second etch stop layer 156, such as... Figure 1As shown. According to some embodiments, the second top-side oxide layer 154 and the third top-side oxide layer 158 may contain, for example, but not limited to, non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. Figure 1 The diagram depicts a third etch stop layer 160 formed on a third top-side oxide layer 158. As indicated above with respect to the first etch stop layer 112 and the second etch stop layer 156, the third etch stop layer 160 suitably comprises a material layer having etch characteristics distinctly different from the material to be etched, thereby stopping or halting the etching process of the layer deposited on the etch stop layer. Therefore, the third etch stop layer 160 may comprise, for example, but not limited to, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc.

[0083] According to some embodiments, Figure 1 The photonic device 100 also includes a fourth top-side oxide layer 162 formed or deposited on the third etch stop layer 160. This fourth top-side oxide layer 162 may comprise, for example, but not limited to, a non-low-k dielectric material, such as silicon oxide, SiC, SiCN, SiOCN, etc. A fourth etch stop layer 164 may be formed on the fourth top-side oxide layer 162, such as... Figure 1 As shown. In some embodiments, the fourth etch stop layer 164 may comprise, for example, but not limited to, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. In different embodiments disclosed in some embodiments of this disclosure, the first top-side oxide layer 106, the second top-side oxide layer 154, the third top-side oxide layer 158, and the fourth top-side oxide layer 162 may comprise the same or different oxide materials. In some embodiments, the first top-side oxide layer 106, the second top-side oxide layer 154, the third top-side oxide layer 158, and the fourth top-side oxide layer 162 may comprise the same oxide material deposited or formed at different times or stages of the fabrication of the photonic device 100.

[0084] exist Figure 1 In this design, the ribbed waveguide assembly 124 includes a ribbed contact hole 134, an upper portion extending a preselected distance into the first silicon layer 108, a lower portion including a contact hole or rib trench 137 formed in the first silicon layer 108, a contact etch stop layer cavity 135 formed within a contact oxide layer 136 deposited in the trench 137, a ribbed contact 138 formed of a suitable conductive material extending through the ribbed contact hole 134, a ribbed N+ doped assembly 166, and a P+ doped assembly 168 located below a contact etch stop layer (CESL) 132 within the first silicon layer 108. Figure 1As shown, each contact hole 134 includes the aforementioned silicate glass material 128. According to some embodiments, the thickness or depth of the contact etch stop layer (CESL) 132 is 5% or greater than the depth 170 of the contact hole 134.

[0085] According to some embodiments, the contact oxide layer 136 may comprise, for example, but not limited to, a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. According to some embodiments, the contact etch stop layer 132 may be made of, for example, but not limited to, oxides, SiN, undoped silicate glass, fluorosilicate glass, borosilicate glass, etc. Figure 1 As shown, the contact etch stop layer 132 is formed within the contact etch stop layer cavity 135 of the contact oxide layer 136 in the contact hole trench 137. According to some embodiments, the contact etch stop layer 132 is located within the oxide layer 136 in the contact hole or rib trench 137 such that the distance between the contact etch stop layer 132 and the first silicon layer 108 is greater than or equal to one-quarter of the thickness of the contact etch stop layer (CESL) 132.

[0086] As will be understood, the doping used to form the N+ doped component 166 and the P+ doped component 168 can be accomplished, for example, by ion implantation. In short, an ion implanter is used to implant atoms into a silicon lattice, thereby altering the conductivity of the lattice at the implantation site. An ion implanter typically includes an ion source, a beamline, and a processing chamber. The ion source generates the desired ions (e.g., Co, Ti, Ni, Pt, or Pb, depending on the desired N-type or P-type electrode). The beamline organizes the ions into a bundle with high purity in terms of ion mass, energy, and species. The ion beam is then used to irradiate the wafer substrate in the processing chamber. The ion beam strikes exposed areas on the wafer substrate, and the ions can be implanted into the substrate as dopants at the desired depth. Alternatively, the substrate can be partially etched, followed by blanket deposition of metal, and then annealing, in which the metal reacts with the exposed silicon underneath. Unreacted metal can then be removed, for example, by a selective etching process. Figure 1 As shown, contact hole 134 includes a contact hole depth 170 extending into the first silicon layer 108 to a depth between 8,000 and 14,000 angstroms. In other embodiments, the contact hole depth 170 extends into the first silicon layer 108 to a depth between 9,000 and 12,000 angstroms. According to some embodiments, rib-doped component 166 may have a dopant concentration of N+, and rib-doped component 168 may have a dopant concentration of P+. It should also be understood that contact 138 extends through contact etch stop layer 132 to contact the respective first rib-doped component 166 and first rib-doped component 168.

[0087] According to some embodiments, the contact 138 is in electrical contact with a portion of the metal assembly 140 formed between the second top-side oxide layer 154 and the third top-side oxide layer 158, such as Figure 1 As shown. According to such an embodiment, each metal component 140, which provides a function similar to a conductor, is in electrical contact with a corresponding bump pad 142. It should be understood that the metal component 140 can be implemented as, for example, but not limited to, any suitable conductive material, including, for example, but not limited to, suitable conductive metals, including, for example, but not limited to, copper, aluminum, iron, and their alloys. Furthermore, some embodiments of this disclosure may utilize bump pads 142 comprising, for example, but not limited to, Al, Fe, Cu, Al-Cu, their alloys, or any other suitable material, as will be understood by those skilled in the art. Figure 1 As shown, each of the bump pads 142 is suitably disposed through the fourth top-side oxide layer 162. Subsequent fabrication (not shown) may include adding one or more solder bumps, which may include lead alloy solder, lead-free solder, flux-cored solder, silver alloy solder, etc.

[0088] According to one embodiment, Figure 1 The photonic device 100 may utilize a light source 148 coupled to pillar 114 and located above pillar cavity 116. The light source 148 may be implemented as, for example, but not limited to, a laser (e.g., a III-V laser), an optical fiber, an external light source, reflected light, etc. In some embodiments, the light source 148 may generate light in the wavelength range of 200 nm to 1300 nm, and in some embodiments, it may generate light in the wavelength range of 300 nm to 1200 nm. Facet 150 is optically coupled to the light source 148, thereby directing any light into the photonic device 100, such as... Figure 1 As shown. Therefore, Figure 1 The illustration of the light source 148 depicted is intended only to show the direction in which light (i.e., photons) enters the photon device 100. Figure 1 The photonic device 100 may also include one or more metal components 152 disposed therein to provide additional functionality and transmittance.

[0089] Now turn to Figures 2A to 2AD The illustration depicts the manufacturing process according to some embodiments. Figure 1The patterning of the photonic device 100 is a series of intermediate stages of the optical components. The patterning of the layer can employ any suitable patterning technique, such as photolithography, which uses photoresist layer deposition and selective exposure via a photomask to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), etc., followed by development of the exposed photoresist, and then etching, deposition, or other process steps involving lateral scribes by the developed photoresist. In other embodiments, the patterning of the electron-sensitive resist layer can be performed via electron beam lithography (electron beam lithography, i.e., e-beam lithography). Those skilled in the art will understand that the foregoing is merely illustrative.

[0090] like Figure 2A As shown, substrate 102 is formed having a back oxide layer 104. In some embodiments, the back oxide layer 104 includes a polyimide layer 178 formed on its surface opposite to the surface of the substrate 102. According to one embodiment, substrate 102 is an SOI substrate, as described above regarding... Figure 1 As stated above.

[0091] exist Figure 2B In this process, a first top-side oxide layer 106 is formed on the substrate 102. For example... Figure 2B As shown, a first top-side oxide layer 106 is deposited on the top side of the substrate, opposite to the side of the substrate 102 to which the back oxide layer 104 is attached. As described above, the first top-side oxide layer 106 may comprise, for example, but not limited to, non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. According to some embodiments, the formation of the first top-side oxide layer 106 may be accomplished via any suitable deposition or layering process, including, for example, but not limited to, deposition via, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, chemical-mechanical polishing (CMP) may be performed after the deposition of the first top-side oxide layer 106 to obtain, as shown in the figure. Figure 2B The plane shown.

[0092] The first silicon layer 108 is then deposited on the first top-side oxide layer 106, as follows: Figure 2CAs shown. Suitable methods for forming the first silicon layer 108 may include, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, chemical-mechanical polishing (CMP) may be performed after depositing the first silicon layer 108 to obtain, as shown. Figure 2C The plane is shown. The first silicon layer 108 may contain silicon, such as, but not limited to, silicon in the form of crystalline Si or polycrystalline Si. According to some embodiments, the first silicon layer 108 may be implemented to have a thickness in the range of 1 μm to 5 μm, and in some embodiments, it may have a thickness of 3 μm.

[0093] The hard mask 172 is then formed on the first silicon layer 108, as follows: Figure 2D As depicted in the illustration. According to some embodiments, the hard mask 172 comprises multiple oxide material layers, with a polyimide layer disposed therebetween. In some embodiments, a first oxide material is deposited, followed by CMP, and then the polyimide material is deposited. After CMP is performed on the polyimide material, a second oxide material is deposited, followed by CMP, thereby obtaining... Figure 2D The intermediate manufacturing stage is shown. As discussed above, various deposition methods can be used to produce the hard mask 172, as those familiar with this technique will understand.

[0094] Then, photoresist 174 is deposited and patterned on the hard mask 172, such as... Figure 2E As shown in the illustration. In some embodiments, photoresist 174 is coated onto a hard mask 172, and then portions of the photoresist 174 are developed by exposure to a suitable light source to form a pattern thereon. The unexposed portions are then removed, thereby obtaining... Figure 2E The patterned photoresist 174 is shown. Etching is then performed to remove portions of the hard mask 172 and / or the underlying first silicon layer 108 to form a distributed Bragg reflector (DBR) aperture 176. Suitable removal processes include, but are not limited to, etching processes, implemented as dry etching, RIE, wet etching, some other etching process, or a combination of the foregoing. According to some embodiments, the DBR aperture 176 may be implemented with a depth ranging from 0.01 μm to 0.6 μm, and in some embodiments, the depth of the DBR aperture 176 may be less than or equal to 0.4 μm. Figure 2FAn illustration of the photonic device 100 after the formation of the DBR aperture 176 is provided. The DBR aperture 176 is then filled with a suitable material having the desired refractive index to form a distributed Bragg reflector 110, as shown below. Figure 2G As shown. According to some embodiments, the DBR holes 176 are filled with silicate glass or oxide materials (including, for example, but not limited to, undoped silicate glass, BPSG glass, etc.).

[0095] exist Figure 2H In the process, photoresist 180 is then deposited and patterned on the hard mask 172. In some embodiments, photoresist 180 is coated onto the hard mask 172, and then portions of the photoresist 180 are developed by exposure to a suitable light source to form a pattern thereon. The unexposed portions are then removed, resulting in... Figure 2H The patterned photoresist 180 is shown. Etching is then performed to remove portions of the hard mask 172 and / or the underlying first silicon layer 108 to form strip-shaped and rib-shaped hard mask vias (or openings) 182, as shown. Figure 2I As shown in the figure. Suitable removal processes include, for example, but not limited to, etching processes, which are implemented as dry etching processes, RIE processes, wet etching processes, some other etching processes, or combinations of the foregoing processes.

[0096] Then, photoresist 184 is deposited and patterned on the hard mask 172, such as... Figure 2J As shown. In some embodiments, photoresist 184 is coated onto a hard mask 172, and then portions of the photoresist 184 are developed by exposure to a suitable light source to form a pattern thereon. The unexposed portions are then removed, resulting in... Figure 2J The patterned photoresist 184 is shown. Etching is then performed to remove portions of the first silicon layer 108 to allow the formation of strip-shaped holes 186, as shown. Figure 2K As shown in the figure. Suitable removal processes include, for example, but not limited to, etching processes, which are implemented as dry etching processes, RIE processes, wet etching processes, some other etching processes, or combinations of the foregoing processes.

[0097] exist Figure 2L In this process, photoresist 188 is deposited and patterned on the hard mask 172 and within a portion of the strip-shaped aperture 186. For example... Figure 2L As shown, the photoresist is further patterned to enable the formation of the ribbed waveguide assembly 124. The photoresist 188 is then exposed, and the unexposed portions of the photoresist 188 are removed, thereby obtaining... Figure 2L This represents an intermediate fabrication stage of the photonic device 100. Subsequently, etching is performed to remove portions of the first silicon layer 108 to enable the formation of the R2S vias 190 and the ribbed contact vias 134, as shown. Figure 2MAs shown in the figure. Suitable etching processes include, for example, but not limited to, dry etching, RIE, wet etching, some other etching process, or a combination of the foregoing processes.

[0098] exist Figure 2N In this process, photoresist 192 is deposited and patterned on the hard mask 172 and in a portion of the strip-shaped aperture 186, the R2S aperture 190, and the rib-shaped contact aperture 134. For example... Figure 2N As shown, photoresist 192 is coated, and then portions of the photoresist 192 are developed by exposure to a suitable light source to form contact hole trenches 137, which define the locations of contact etch stop layers 132. Subsequently, etching is performed to remove portions of the first silicon layer 108 to enable the formation of ribbed contact hole trenches 137, as shown. Figure 2O As shown in the figure. Suitable etching processes include, for example, but not limited to, dry etching, RIE, wet etching, some other etching process, or a combination of the foregoing processes.

[0099] Then, photoresist 194 is formed and patterned on the photonic device 100, such as... Figure 2P As shown. Therefore, photoresist 194 is deposited into the strip-shaped via 186 and the R2S via 190. Then, doping is performed on the first silicon layer 108 exposed in the rib-shaped contact via 134. Figure 2Q As shown, ribbed N+ doped components 166 and ribbed P+ doped components 168 are formed in ribbed contact holes 134 within the first silicon layer 108, below the contact hole trench 137. As will be understood, the doping used to form doped components 166 and 168 can be accomplished, for example, by ion implantation. As discussed above, an ion implanter is used to implant atoms into a silicon lattice, thereby altering the conductivity of the lattice at the implantation site. An ion implanter typically includes an ion source, a beamline, and a processing chamber. The ion source generates the desired ions (e.g., Co, Ti, Ni, Pt, or Pb, depending on the desired N-type or P-type electrode). The beamline organizes the ions into a bundle with high purity in terms of ion mass, energy, and species. The ion beam is then used to irradiate the wafer substrate in the processing chamber. The ion beam strikes exposed areas on the wafer substrate, and the ions can be implanted into the substrate as dopants at the desired depth. Alternatively, the substrate can be partially etched, followed by blanket deposition of metal and annealing, wherein the metal reacts with the exposed silicon beneath. Unreacted metal can then be removed, for example, by a selective etching process.

[0100] Then, photoresist 196 is deposited into the strip-shaped hole 186, the R2S hole 190, and the first contact hole 134, as follows: Figure 2R As shown. According to one embodiment, the contact oxide layer 136 is then deposited in the contact hole trench 137 on the bottom of the ribbed contact hole 134, as... Figure 2SAs shown. According to some embodiments, the contact oxide layer 136 may comprise, for example, but not limited to, a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. Figure 2S As shown, the contact oxide layer 136 covers a portion of the bottom of the ribbed contact hole 134 and extends downward into the contact hole trench (or rib trench) 137, thereby defining a portion therein of the contact etch stop layer cavity 135 (as shown). Figure 2Y As shown below (and discussed in more detail).

[0101] like Figure 2T As shown, photoresist 198 is coated and patterned to protect the strip-shaped holes 186 and R2S holes 190, thereby exposing the ribbed contact holes 134. Subsequently, a contact etch stop layer 132 is deposited in the ribbed contact holes 134, and as... Figure 2U As shown, the contact etch stop layer cavity 135 on the contact oxide layer 136 within the contact trench 137 is located above the corresponding doped components 166 and 168. According to some embodiments, the contact etch stop layer 132 suitably comprises a material layer having etch characteristics distinctly different from the material to be etched, thereby stopping or halting the etching process of the layer deposited on the etch stop layer. Therefore, the contact etch stop layer 132 may comprise, for example, but not limited to, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc.

[0102] exist Figure 2V In the next step, photoresist 200 is deposited and patterned to allow for the removal of the contact etch stop layer 132 from portions of the ribbed contact holes 134, as shown. After removing the uncovered contact etch stop layer 132 and photoresist 200, Figure 2W The image shows a contact etch stop layer 132 in a contact etch stop layer cavity 135. (See image for details.) Figure 2X As shown, according to some embodiments, a photoresist 202 is then deposited and patterned on the photonic device 100. For example... Figure 2X As shown, the photoresist 202 is patterned to enable the deposition of the contact oxide layer 136 material on the contact etch stop layer 132. Subsequently, in Figure 2Y The image depicts a fully encapsulated contact etch stop layer 132.

[0103] Silicate glass material 128 is then deposited onto photonic device 100, such as... Figure 2Z As shown above, silicate glass material 128 is suitably formed in the strip-shaped hole 186, the R2S hole 190, and the rib-shaped contact hole 134. Subsequently, CMP and polyimide etching (i.e., removal of the hard mask 172) are performed, as... Figure 2AA As depicted in the text. Then, an undoped silicate glass assembly 130 is deposited, as shown in the image. Figure 2ABAs shown. According to some embodiments, the undoped silicate glass (USG) assembly 130 can be implemented with a thickness in the range of 5,000 angstroms to 10,000 angstroms. In one embodiment, the undoped silicate glass (USG) assembly 130 has an implant thickness of 8 angstroms.

[0104] exist Figure 2AC In this process, photoresist 204 is deposited and patterned on undoped silicate glass (USG) assembly 130. As shown, the photoresist 204 is appropriately patterned to allow for the subsequent formation of ribbed contact cavities 206 within ribbed contact holes 134. Etching is then performed to form the ribbed contact cavities 206, as shown. Figure 2AD As shown. According to some embodiments, CMP can also be performed to planarize the undoped silicate glass (USG) assembly 130. Thereafter, as will be understood, subsequent formation of the photonic device 100 can be performed, such as forming ribbed contacts 138, interlayer dielectric fabrication, metal assembly 140, bump pads 142, forming pillars 114, pillar cavities 116, etc.

[0105] Now turn to Figures 3A to 3B A close-up cross-sectional view of the bottom portion 300 of the ribbed contact hole 134 according to the first embodiment is shown. That is, Figures 3A to 3B The contact hole trench 137 is shown, in which a contact etch stop layer 132 is formed via a dry etching process. Figure 3A ) and wet etching process ( Figure 3B The etch stop layer is made within cavity 135. Therefore, Figures 3A to 3B The cross-section shown is the same with respect to the etch stop layer cavity 135, however, it is for contact etch stop layer 132 (as described above). Figures 2U to 2Y The etching performed (as described) is different. As shown in the figure, Figure 3A The etch stop layer 132, which is dry-etched, has substantially straight edges on each side. In contrast, Figure 3B The curves, arcs, or radians 311 on each side of the etch stop layer 132 are represented by wet etching, which is produced by the wet etching process. It should be understood that the wet etching material can remove some of the material contacting the etch stop layer 132 during patterning, thereby resulting in... Figure 3B The slight curvature 311 shown in the figure. According to such an embodiment, the curvature 311 at this interface between the contact etch stop layer 132 and the contact oxide layer 136 may be approximately one-tenth the thickness of the contact etch stop layer 132.

[0106] therefore, Figures 3A to 3C A contact hole trench 137 is illustrated within a first silicon layer 108 formed in a contact hole 134. The contact hole trench 137 includes a top surface 302, a first sidewall 304, a second sidewall 305, and a bottom surface 306. The top surface 302 is flush with the contact hole trench 137. According to one embodiment, the top surface 302 is perpendicular to both the first sidewall 304 and the second sidewall 305. Figures 3A to 3B As shown, the sidewalls 304 and 305 and the bottom surface 306 of the contact hole trench 137 include a contact oxide layer 136 formed thereon. Figures 3A to 3B The location of the contact etch stop layer 132 within the etch stop layer cavity 135 is further described by the following: the portions of the contact oxide layer 136 formed on the sidewalls 304, 305, and bottom surface 306 of the contact hole trench 137, and the contact oxide layer 136 formed on the contact etch stop layer 132 (i.e., the contact oxide layer 136 material positioned across the top surface 302 and the contact etch stop layer 132). Figure 3A and Figure 3B As shown, the top of the contact etch stop layer 132 is level with, i.e., flush with, the top surface 302 of the contact hole trench 137 in the first silicon layer 108 located within the contact hole 134. As shown, the height of the outer sidewalls 304 and 305 of the contact hole trench 137 is at least 5% of the depth of the contact 138 (not shown). Figure 3C Show Figures 3A to 3B A top view of the embodiment depicted in the figure. Figure 3C The contact hole 134 depicted is circular; however, it should be understood that other shapes, such as rectangular, polygonal, etc., may be used in different embodiments. Figure 3C As shown, the upper portion of the contact hole 134 has a width or diameter 308 that is greater than the width or diameter 309 of the lower portion of the contact hole 134 (i.e., the contact hole trench 137). Furthermore, the top surface 302 extends circumferentially around the bottom surface 306 of the contact hole trench 137. As discussed above, a contact oxide layer 136 is formed across the lower portion of the contact hole 134 (i.e., across the contact hole trench 137), thereby encapsulating the contact etch stop layer 132.

[0107] Now for reference Figures 4A to 4B A close-up cross-sectional view of the bottom portion 312 of the ribbed contact hole 134 according to the second embodiment is shown. That is, Figures 4A to 4B The contact hole trench 137 is shown, in which a contact etch stop layer (CESL) 132 is placed via a dry etching process. Figure 4A ) and wet etching process ( Figure 4BThe etch stop layer cavity 135 is formed within the cavity, wherein the contact etch stop layer (CESL) 132 is partially located above the top surface 302 of the etch stop layer cavity 135. Therefore, Figure 4A and Figure 4B The cross-section shown is the same with respect to the etch stop layer cavity 135, however, for the contact etch stop layer (CESL) 132 (as described above with respect to...) Figures 2U to 2Y The etching performed (as described) is different. As shown in the figure, Figure 4A The contact etch stop layer (CESL) 132, which is dry-etched, has substantially straight edges on each side. In contrast, Figure 4B The curves, arcs, or radians 311 on each side of the contact etch stop layer (CESL) 132 are represented by wet etching, which is produced by the wet etching process. It should be understood that the wet etching material can remove some of the material from the contact etch stop layer 132 during patterning, thereby resulting in... Figure 4B The slight curvature 311 shown in the figure. According to such an embodiment, the curvature 311 at this interface between the contact etch stop layer (CESL) 132 and the contact oxide layer 136 may be approximately one-tenth the thickness of the contact etch stop layer (CESL) 132.

[0108] therefore, Figures 4A to 4B The diagram illustrates a contact hole trench 137 formed in a first silicon layer 108 within a contact hole 134, wherein the contact hole trench 137 includes the features described above. Figures 3A to 3B The same surfaces described, namely top surface 302, sidewalls 304, sidewalls 305, and bottom surface 306. However, in Figures 4A to 4B In the second embodiment, the contact etch stop layer (CESL) 132 is positioned such that a portion of it extends above the plane of the top surface 302, i.e., the contact etch stop layer (CESL) 132 is higher than the top surface 302 of the contact hole trench 137 in the first silicon layer 108 at the bottom of the contact hole 134. Figures 4A to 4B As shown, the sidewalls 304 and 305 and the bottom surface 306 of the contact hole trench 137 include a contact oxide layer 136 formed thereon. (As mentioned above regarding...) Figures 3A to 3B The discussion, Figures 4A to 4BThe height 310 of the sidewalls 304 and 305 of the contact hole groove 137 shown is at least 5% of the depth of the contact element 138 (not shown). It should be understood that when viewed from above, Figures 4A to 4B The embodiments are still the same as Figures 3A to 3B Same, and therefore Figure 3C Can be used to show Figures 4A to 4B A top view of an embodiment.

[0109] Figures 5A to 5B A close-up cross-sectional view of the bottom portion 314 of the ribbed contact hole 134 according to the third embodiment is shown. That is, Figures 5A to 5B The contact hole trench 137 is shown, in which a contact etchstop layer (CESL) 132 is deposited via a dry etching process. Figure 5A ) and wet etching process ( Figure 5B The etch stop layer cavity 135 is formed within the cavity, wherein the contact etch stop layer (CESL) 132 is partially located below the top surface 302 of the etch stop layer cavity 135. Therefore, Figure 5A and Figure 5B The cross-section shown is the same with respect to the etch stop layer cavity 135, however, for the contact etch stop layer (CESL) 132 (as described above with respect to...) Figures 2U to 2Y The etching performed (as described) is different. As shown in the figure, Figure 5A The contact etch stop layer (CESL) 132, which is dry-etched, has substantially straight edges on each side. In contrast, Figure 5B The curves, arcs, or radians 311 on each side of the contact etch stop layer (CESL) 132 are represented by wet etching, which is produced by the wet etching process. It should be understood that the wet etching material can remove some of the material from the contact etch stop layer 132 during patterning, thereby resulting in... Figure 5B The slight curvature 311 shown in the figure. According to such an embodiment, the curvature 311 at this interface between the contact etch stop layer (CESL) 132 and the contact oxide layer 136 may be approximately one-tenth the thickness of the contact etch stop layer (CESL) 132.

[0110] therefore, Figures 5A to 5B The diagram illustrates a contact hole trench 137 forming a first silicon layer 108 within a contact hole 134, wherein the contact hole trench 137 includes the features described above. Figures 3A to 4B The same surfaces described, namely top surface 302, sidewalls 304, sidewalls 305, and bottom surface 306. However, in Figures 5A to 5B In the third embodiment (bottom portion 314), the contact etch stop layer (CESL) 132 is located below the plane of the top surface 302 of the contact hole trench 137. For example... Figures 5A to 5B As shown, the sidewalls 304 and 305 and the bottom surface 306 of the contact hole trench 137 include a contact oxide layer 136 formed thereon. (As mentioned above regarding...) Figures 3A to 4B The discussion, Figures 5A to 5B The height 310 of the sidewalls 304 and 305 of the contact hole groove 137 shown is at least 5% of the depth of the contact element 138 (not shown). It should be understood that when viewed from above, Figures 4A to 4B The embodiments are still the same as Figures 3A to 3B Same, and therefore Figure 3C Can be used to show Figures 4A to 4B A top view of an embodiment.

[0111] Now for reference Figure 6 The diagram 600 illustrates a method for manufacturing a photonic device structure according to an exemplary embodiment. Figure 6 As shown, the method begins at step 602, whereby a first top-side oxide layer 106 is formed on the substrate 102, as follows. Figure 2B As shown. In some embodiments, substrate 102 may be an SOI (silicon-on-insulator) substrate. Then, in step 604, a silicon layer 108 is formed on the first top-side oxide layer 106. Figure 2C An illustrative example of the deposition of silicon layer 108 is provided. In step 606, a hard mask 172 is formed on silicon layer 108, as shown... Figure 2D As shown in the figure.

[0112] Then, in step 608, the distributed Bragg reflector 110 is patterned in the hard mask 172 and the silicon layer 108. Figure 2E and Figure 2F As discussed above, illustrative examples of the process performed in step 608 are provided. In step 610, strip-shaped, rib-shaped, and strip-shaped and rib-shaped hard mask openings 182 are patterned in the hard mask, such as... Figures 2G to 2I As shown. Subsequently, in step 612, etching is performed to remove a portion of the silicon layer 108 to form strip-shaped holes 186 and rib-to-strip (R2S) holes 190. Figures 2J to 2K Illustrations are provided of the formation of the strip-shaped hole 186 and the R2S hole 190 according to some embodiments.

[0113] In step 614, ribbed contact holes 134 corresponding to the ribbed waveguide assembly 124 are formed in the silicon layer 108. For example... Figures 2L to 2M As shown, photoresist 188 can be deposited and patterned on silicon layer 108, and then etched to remove a portion of silicon layer 108, thereby defining ribbed contact holes 134. In step 616, contact hole trenches 137 are formed (i.e., patterned, etched, etc.) in contact holes 134. Figures 2N to 2O The formation of the contact hole trench 137 may include coating and patterning a photoresist 192, etching the bottom of the contact hole 134 to remove a portion of the silicon layer 108, thereby creating the contact hole trench 137.

[0114] In step 618, the silicon layer 108 doped in the first contact hole 134 below the contact hole trench 137, such as Figures 2P to 2Q As shown. As discussed above, N+ doped component 166 and P+ doped component 168 are formed in the first contact hole 134 of the ribbed waveguide component 124. In step 620, a contact oxide layer 136 is formed (i.e., deposited and patterned) in the contact hole 134, as shown. Figures 2R to 2S As shown. According to one embodiment, a contact oxide layer 136 is deposited on the contact hole trench 137, on the top surface 302, sidewalls 304, sidewalls 305, and bottom surface 306. As... Figures 2R to 2S As shown, patterning may include, for example, but not limited to, coating and patterning a photoresist 196, then depositing a contact oxide layer 136 and removing the photoresist 196.

[0115] Subsequently, in step 622, a contact etch stop layer (CESL) 132 is formed in the contact hole trench (or rib trench) 137 of the contact hole 134. The formation of the contact etch stop layer (CESL) 132 may include patterning (coating, developing, etc.) of the photoresist 198, such as... Figure 2T As shown. Figure 2UAs shown, the formation of the contact etch stop layer (CESL) 132 may cause CESL 132 material to deposit on the top surface 302 of the contact hole trench (or rib trench) 137. Therefore, in step 624, the contact hole trench (or rib trench) 137 is etched to remove the aforementioned contact etch stop layer (CESL) 132 material deposited on the top surface 302. In such an embodiment, a photoresist 200 may be coated and patterned to protect the portion of the contact etch stop layer (CESL) 132 material formed between the sidewalls 304 and 305 of the contact hole trench (or rib trench) 137, such as... Figure 2V As shown. Then a suitable etching process can be performed to obtain... Figure 2W The intermediate manufacturing stage is shown. It should be understood that when dry etching is performed at this manufacturing stage, the contact etch stop layer (CESL) 132 in the contact hole trench (or rib trench) 137 will have approximately straight edges, such as... Figure 3A , Figure 4A and Figure 5B As shown. When performing wet etching to remove excess material, arc 311 may be generated by the wet etching process, such as... Figure 3B , Figure 4B and Figure 5B As shown.

[0116] In step 626, an etch stop layer cavity 135 is formed in the contact hole trench 137, such as Figures 2X to 2Y As shown in the illustration. According to one embodiment, photoresist 202 can be coated and patterned to expose the contact etch stop layer (CESL) 132 retained in the contact hole trench 137, as shown. Figure 2X As shown. Subsequently, deposition of the contact oxide layer 136 on the encapsulated contact etch stop layer (CESL) 132 is performed, as follows. Figure 2Y As shown in the diagram. In step 628, silicate glass material 128 is deposited, which fills the contact hole 134, as shown. Figure 2Z As shown in the diagram. Subsequently, CMP and polyimide etching (i.e., removal of hard mask 172) are performed in step 630, as... Figure 2AA As depicted in the diagram. In step 632, an undoped silicate glass assembly 130 is deposited on the silicon layer 108, as shown in the diagram. Figure 2ABAs shown in the diagram. In step 634, a contact cavity 206 is formed in the contact hole 134, as shown in the diagram. Figures 2AC to 2AD As shown. Figure 2AD As shown, the contact cavity 206 extends through the undoped silicate glass assembly 130, the silicate glass material 128, the contact oxide layer 136, and the contact etch stop layer 132, thereby allowing subsequent formation of the contact 138, such as... Figure 1 As shown in the figure.

[0117] According to a first embodiment, a photonic device structure is provided. The photonic device structure includes a substrate having a top-side oxide layer and a silicon layer located on the top-side oxide layer. The structure also includes a ribbed waveguide assembly located in the silicon layer and including a plurality of contact holes. Each contact hole includes an upper portion having a first width located in the silicon layer and a lower portion including a contact hole trench located in the silicon layer, the lower portion having a second width narrower than the first width. The contact hole also includes a contact etch stop layer located in the contact hole trench. In some embodiments, the photonic device structure further includes a contact oxide layer located in the contact hole trench, wherein the contact oxide layer defines a contact etch stop layer cavity and wherein the contact etch stop layer is located therein. In some embodiments, the contact hole trench further includes a first sidewall, a second sidewall, and a bottom surface, wherein the contact oxide layer is located on the first sidewall, the second sidewall, and the bottom surface. In some embodiments, the contact hole trench further includes a top surface perpendicular to the first sidewall and the second sidewall, wherein the contact oxide layer is located on the top surface. In some embodiments, the top of the contact etch stop layer is flush with the top surface. In some embodiments, the top of the contact etch stop layer is located above a plane formed by the top surface. In some embodiments, the top of the contact etch stop layer is located below the plane formed by the top surface. In some embodiments, the distance between the contact etch stop layer and the silicon layer of the contact hole trench is greater than or equal to one-quarter of the thickness of the contact etch stop layer. In some embodiments, the depth of the contact etch stop layer is 5% or more of the depth of the contact hole.

[0118] According to a second embodiment, a photonic semiconductor device is provided. The photonic semiconductor device includes a substrate and a first top-side oxide layer on the substrate. The device also includes a silicon layer on the first top-side oxide layer. The silicon layer of the photonic semiconductor device includes a first waveguide component, a second waveguide component, and at least one third waveguide component, the at least one third waveguide component including a contact hole. Additionally, each contact hole includes an upper portion having a first width located in the silicon layer and a lower portion including a contact hole trench located in the silicon layer, the lower portion having a second width narrower than the first width. The contact hole also includes a contact etch stop layer located in the contact hole trench. In some embodiments, the photonic semiconductor device further includes a pillar, a pillar cavity, a facet, and a light source. The pillar cavity is located in the substrate, between the pillar and the first top-side oxide layer. The facet is positioned adjacent to the silicon layer. The light source is located on the pillar and optically coupled to the facet. In some embodiments, the photonic semiconductor device further includes a contact oxide layer located in the contact hole trench, wherein the contact oxide layer defines a contact etch stop layer cavity and wherein the contact etch stop layer is located therein. In some embodiments, the contact hole trench further includes a first sidewall, a second sidewall, and a bottom surface, wherein a contact oxide layer is located on the first sidewall, the second sidewall, and the bottom surface. In some embodiments, the contact hole trench further includes a top surface perpendicular to the first and second sidewalls, wherein the contact oxide layer is located on the top surface. In some embodiments, the top of the contact etch stop layer is positioned at least flush with, below, or above the top surface. In some embodiments, the distance between the contact etch stop layer and the silicon layer of the contact hole trench is greater than or equal to one-quarter of the thickness of the contact etch stop layer. In some embodiments, the depth of the contact etch stop layer is 5% or more of the depth of the contact hole.

[0119] According to a third embodiment, a method for manufacturing a photonic semiconductor device is provided. The method includes: forming a silicon layer on a first top-side oxide layer of a substrate, and forming strip waveguides, rib-to-strip waveguides, and / or distributed Bragg reflector waveguides in the silicon layer. The method further includes forming a plurality of contact holes in the rib waveguides in the silicon layer. Additionally, the method includes forming a contact hole trench in each of the contact holes, such that the contact hole trench includes a first sidewall, a second sidewall, and a bottom surface. The method further includes: doping at least a first of the contact holes to a dopant concentration of N+ and at least a second of the contact holes to a dopant concentration of P+, and forming a contact oxide layer on the first sidewall, second sidewall, and bottom surface in each of the contact hole trenches. Furthermore, the method includes forming a contact etch stop layer on the contact oxide layer between the first and second sidewalls in each of the contact holes. In some embodiments, the depth of the contact etch stop layer is 5% or more of the depth of the contact hole. In some embodiments, the distance between the contact etch stop layer and the silicon layer of the contact hole trench is greater than or equal to one-quarter of the thickness of the contact etch stop layer.

[0120] According to some embodiments, a photonic semiconductor device is provided. The photonic semiconductor device includes a substrate and a first top-side oxide layer on the substrate. The photonic semiconductor device also includes a silicon layer on the first top-side oxide layer. The silicon layer of the photonic semiconductor device includes a first waveguide component, a second waveguide component, and at least one third waveguide component, the third waveguide component including contact holes. Each contact hole includes an upper portion having a first width in the silicon layer and a lower portion including a contact hole trench in the silicon layer, the lower portion having a second width narrower than the first width. The silicon layer also includes a contact etch stop layer located in the contact hole trench. The photonic semiconductor device also includes a contact oxide layer located in the contact hole trench. The contact oxide layer defines a contact etch stop layer cavity, and the contact etch stop layer is located within the contact etch stop layer cavity.

[0121] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the appearance of some embodiments disclosed herein. Those skilled in the art should understand that they can readily use some embodiments disclosed herein as a basis to design or modify other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments disclosed herein, and that they can make various changes, substitutions, and modifications to some embodiments disclosed herein without departing from the spirit and scope of these embodiments.

Claims

1. A photonic device structure, characterized in that, Include: A substrate, comprising a top-side oxide layer located on the substrate; A silicon layer is located on the top oxide layer; A ribbed waveguide assembly is located in the silicon layer, the ribbed waveguide assembly having a plurality of contact holes, each of the plurality of contact holes comprising: An upper portion, located within the silicon layer, having a first width; and The lower portion includes a contact trench located in the silicon layer, the lower portion having a second width narrower than the first width; and A contact etch stop layer is located in the contact hole trench.

2. The photonic device structure as described in claim 1, characterized in that, Also includes: A contact oxide layer is located in the contact hole trench, wherein the contact oxide layer defines a contact etch stop layer cavity and wherein the contact etch stop layer is located in the contact etch stop layer cavity.

3. The photonic device structure as described in claim 2, characterized in that, The contact hole trench further includes a first sidewall, a second sidewall, and a bottom surface, wherein the contact oxide layer is located on the first sidewall, the second sidewall, and the bottom surface.

4. The photonic device structure as described in claim 3, characterized in that, The contact hole groove also includes a top surface perpendicular to the first sidewall and the second sidewall, and the contact oxide layer is located on the top surface.

5. The photonic device structure as described in claim 4, characterized in that, The top of the contact etch stop layer is flush with the top surface.

6. The photonic device structure as described in claim 4, characterized in that, The distance between the contact etch stop layer and the silicon layer of the contact hole trench is greater than or equal to one-quarter of the thickness of the contact etch stop layer.

7. The photonic device structure as described in claim 2, characterized in that, The depth of the contact etch stop layer is 5% or greater than the depth of the contact hole.

8. A photonic semiconductor device, characterized in that, Include: One substrate; A first top-side oxide layer is located on the substrate; and A silicon layer is located on the first top-side oxide layer, the silicon layer comprising: First waveguide component; A second waveguide component; and At least one third waveguide assembly, the at least one third waveguide assembly comprising a plurality of contact holes, each of said plurality of contact holes further comprising: An upper portion, located within the silicon layer, having a first width; and The lower portion includes a contact trench located in the silicon layer, the lower portion having a second width narrower than the first width; and A contact etch stop layer is located in the contact hole trench.

9. The photonic semiconductor device as claimed in claim 8, characterized in that, Also includes: One pillar; A pillar cavity is located in the substrate, and the pillar cavity is located between the pillar and the first top-side oxide layer; A facet, positioned adjacent to the silicon layer, and A light source is located on the pillar and is optically coupled to the facet.

10. A photonic semiconductor device, characterized in that, Include: One substrate; A first top-side oxide layer is located on the substrate; A silicon layer is located on the first top-side oxide layer, the silicon layer comprising: First waveguide component; A second waveguide component; At least one third waveguide assembly, the at least one third waveguide assembly comprising a plurality of contact holes, each of said plurality of contact holes further comprising: An upper portion, located within the silicon layer, having a first width; and The lower portion includes a contact hole trench located in the silicon layer, and the lower portion has a second width that is narrower than the first width; A contact etch stop layer is located in the contact hole trench; and A contact oxide layer is located in the contact hole trench, wherein the contact oxide layer defines a contact etch stop layer cavity, and the contact etch stop layer is located in the contact etch stop layer cavity.

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