Power factor correction package device and electronic apparatus

Abstract

The utility model discloses a power factor correction packaging device and electronic equipment. The power factor correction packaging device comprises a substrate, a first booster circuit, a second booster circuit, a strong current pin and a weak current pin, the strong current pin and the weak current pin are located on the two opposite sides of the substrate respectively, and the first booster circuit and the second booster circuit are both connected with the strong current pin and the weak current pin. According to the power factor correction packaging device, the first booster circuit and the second booster circuit are integrated to form the power factor correction packaging device, so that the number of devices is reduced, installation and wiring are facilitated, the occupied space can be saved, the production cost is remarkably reduced, and the power factor correction packaging device is suitable for large-scale popularization and application. And the strong current pin and the weak current pin are respectively positioned on two opposite sides of the substrate, so that electromagnetic interference can be reduced, and stable work is ensured.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a power factor correction packaged device and electronic device. Background Technology

[0002] Power factor correction (PFC) technology can effectively reduce grid current harmonics, decrease interference to the grid, and improve the stability and reliability of the entire system. As system power increases, multi-channel interleaved Boost PFC topologies are commonly used in related technologies. Multi-channel interleaved Boost PFC topologies can reduce current stress on inductors and switches, as well as ripple current in capacitors. However, multi-channel interleaved Boost PFC topologies involve a large number of components, leading to inconvenient wiring and installation, and are also susceptible to electromagnetic interference. Utility Model Content

[0003] This application aims to address at least one of the technical problems existing in the prior art. Therefore, this application provides a power factor correction packaged device and an electronic device.

[0004] The power factor correction packaged device according to the embodiments of this application includes a substrate and a first boost circuit, a second boost circuit, a high-voltage pin, and a low-voltage pin packaged on the substrate; the high-voltage pin and the low-voltage pin are respectively located on opposite sides of the substrate, and the first boost circuit and the second boost circuit are both connected to the high-voltage pin and the low-voltage pin.

[0005] In some embodiments, the high-voltage pin includes a first input pin and an output pin, the low-voltage pin includes a first control pin and a first ground pin, and the first boost circuit includes:

[0006] A first switching transistor, wherein the first terminal of the first switching transistor is connected to the first ground pin, and the control terminal of the first switching transistor is connected to the first control pin;

[0007] A first diode, the positive terminal of which is connected to the first terminal of the first switching transistor, and the negative terminal of which is connected to the second terminal of the first switching transistor;

[0008] The second diode has its anode connected to the second terminal of the first switching transistor and the first input pin, and its cathode connected to the output pin.

[0009] In some embodiments, the first switching transistor includes a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.

[0010] In some embodiments, the second diode includes either a silicon fast recovery diode or a silicon carbide Schottky diode.

[0011] In some embodiments, the high-voltage pin includes a second input pin and an output pin, the low-voltage pin includes a second control pin and a second ground pin, and the second boost circuit includes:

[0012] The second switching transistor has its first terminal connected to the second ground pin and its control terminal connected to the second control pin.

[0013] A third diode, wherein the anode of the third diode is connected to the first terminal of the second switching transistor, and the cathode of the third diode is connected to the second terminal of the second switching transistor;

[0014] A fourth diode, the positive terminal of which is connected to the second terminal of the second switching transistor and the second input pin, and the negative terminal of which is connected to the output pin.

[0015] In some embodiments, the second switching transistor includes a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.

[0016] In some embodiments, the fourth diode includes either a silicon fast recovery diode or a silicon carbide Schottky diode.

[0017] In some embodiments, the low-voltage pin further includes a first detection pin and a second detection pin, and the power factor correction package device further includes:

[0018] A thermistor is packaged on the substrate and connected to a first detection pin and a second detection pin, respectively.

[0019] In some embodiments, the first boost circuit, the second boost circuit, the high-voltage pin, and the low-voltage pin are packaged on the substrate using a dual in-line package (DIP) process.

[0020] The electronic device according to the embodiments of this application includes the power factor correction package device of any of the above embodiments.

[0021] In the power factor correction packaged device and electronic device of this application embodiment, the first boost circuit and the second boost circuit are packaged and integrated on the substrate to form a single device. In this way, the number of devices is reduced while ensuring power factor correction, which facilitates installation and wiring. In addition, it can save space and significantly reduce production costs. Furthermore, the high-voltage pins and low-voltage pins are located on opposite sides of the substrate, which can avoid the crossing of high and low voltage, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0022] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0024] Figure 1 This is a circuit diagram of the power factor correction packaged device according to an embodiment of this application.

[0025] Figure 2 This is a schematic diagram showing the temperature relationship between the thermistor and the IGBT in one embodiment of this application.

[0026] Explanation of key component symbols:

[0027] 100 - Power factor correction package device; 1 - Substrate; 10 - First boost circuit; 101 - First switching transistor; 102 - First diode; 103 - Second diode; 20 - Second boost circuit; 201 - Second switching transistor; 202 - Third diode; 203 - Fourth diode; 30 - High voltage pin; PFC1 - First input pin; PFC2 - Second input pin; P - Output pin; 40 - Low voltage pin; G1 - First control pin; GND1 - First ground pin; G2 - Second control pin; GND2 - Second ground pin; NTC1 - First detection pin; NTC2 - Second detection pin; 301 - Thermistor; Detailed Implementation

[0028] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0029] With the widespread use of electronic products, harmonic pollution of power grids is becoming increasingly serious. Power factor correction (PFC) technology can effectively reduce harmonic components, improve the power factor, thereby reducing energy consumption, reducing the size and weight of power equipment, reducing conductor cross-sectional area, and weakening external radiation and conduction interference from power equipment.

[0030] Boost PFC is a commonly used PFC topology. Boost PFC mainly consists of switching devices and diodes. The switching devices control the circuit's on / off state, while the diodes provide a freewheeling path for the inductor when the switching devices are off, ensuring stable circuit operation. In applications such as commercial air conditioning, as system power increases, multi-channel interleaved Boost PFC topologies are commonly used. Multi-channel interleaved Boost PFC topologies utilize multiple Boost PFC converters connected in an interleaved parallel configuration. In an interleaved parallel PFC circuit, two or more Boost PFC converters are connected in parallel, with each converter's switching transistors conducting alternately. That is, the turn-on times within a switching cycle are sequentially delayed by a certain time (usually 180°), resulting in an interleaved current flow through each Boost PFC converter. The advantage of this method is that it significantly reduces the effective values ​​of input current ripple and output capacitor ripple current, and improves the circuit's power rating. However, in the multi-interleaved Boost PFC topology, each Boost PFC contains multiple devices. The presence of multiple devices makes the wiring more complex, which can easily lead to electromagnetic interference. In addition, multiple devices are inconvenient to install and occupy a lot of space.

[0031] In view of this, please refer to Figure 1 This application provides a power factor correction package device 100, which includes a substrate 1 and a first boost circuit 10, a second boost circuit 20, a high-voltage pin 30, and a low-voltage pin 40 packaged on the substrate 1. The high-voltage pin 30 and the low-voltage pin 40 are located on opposite sides of the substrate 1, and the first boost circuit 10 and the second boost circuit 20 are both connected to the high-voltage pin 30 and the low-voltage pin 40.

[0032] In the power factor correction packaged device 100 of this application embodiment, the first boost circuit 10 and the second boost circuit 20 are packaged and integrated on the substrate 1 to form a single device. In this way, while achieving power factor correction, the number of devices is reduced, which facilitates installation and wiring. Furthermore, it can save space and significantly reduce production costs. The high-voltage pin 30 and the low-voltage pin 40 are located on opposite sides of the substrate 1, which can avoid the crossover of high and low voltage, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0033] The substrate 1 can be made of ceramic, polymer, plastic or composite material, and the substrate 1 needs to have good thermal conductivity to facilitate heat dissipation.

[0034] Both high-voltage pins 30 and low-voltage pins 40 can include multiple pins, and the specific number of high-voltage pins 30 and low-voltage pins 40 can be set according to the needs of the first boost circuit 10 and the second boost circuit 20. The high-voltage pins 30 and low-voltage pins 40 are respectively packaged on opposite sides of the substrate 1 and extend out of the substrate 1.

[0035] High-voltage pin 30 is used to connect circuits with higher voltage or current ratings. Higher voltage ratings refer to voltages greater than 24 volts; for example, pin 30 can connect to 220 volt or 380 volt circuits. Higher current ratings refer to currents typically measured in amperes (A) or kiloamperes (kA); for example, pin 30 can connect to circuits flowing through 2 amperes or 5 amperes. Low-voltage pin 40 is used to connect circuits with lower voltage or current ratings. Lower voltage ratings refer to voltages less than 24 volts, such as 3 volts or 12 volts DC. Lower current ratings refer to currents typically measured in milliamperes (mA) or microamperes (µA).

[0036] Both the first boost circuit 10 and the second boost circuit 20 can be Boost PFC circuits. A Boost PFC circuit is a switching DC-DC boost circuit that adjusts the input voltage through periodic switching to achieve the desired output voltage. The first boost circuit 10 and the second boost circuit 20 are packaged on substrate 1 and are both connected to a high-voltage pin 30 and a low-voltage pin 40. The first boost circuit 10 and the second boost circuit 20 are connected to external circuits through the high-voltage pin 30 and the low-voltage pin 40. The switching transistors of the first boost circuit 10 and the second boost circuit 20 can be interleaved, that is, their turn-on times within the switching cycle are delayed by a certain time (e.g., 180°), thus causing the currents flowing through the first boost circuit 10 and the second boost circuit 20 to also be interleaved. This significantly reduces the effective values ​​of the input current ripple and the output capacitor ripple current, and improves the power rating of the circuit.

[0037] Furthermore, the first boost circuit 10 and the second boost circuit 20, the high-voltage pin 30, and the low-voltage pin 40 can be encapsulated on the substrate 1 using an epoxy resin-based molding compound to form a device. It should be noted that during encapsulation, the back side of the substrate 1 needs to be exposed for heat dissipation. This ensures that the first boost circuit 10 and the second boost circuit 20 operate within a specified temperature range, thereby improving the stability and reliability of the power factor correction packaged device 100. The packaging process can employ a dual in-line package (DIP) process, for example, using a DIP24 package.

[0038] Please refer to Table 1, which compares the dual-interleaved Boost PFC structure in the related art with the power factor correction package device 100 of this application. Table 1 shows that the total area occupied by the dual-interleaved Boost PFC structure in the related art is 1957 square millimeters, while the area occupied by the power factor correction package device 100 of this application is 719 square millimeters. Therefore, this application can significantly reduce the occupied area.

[0039]

[0040] Table 1

[0041] Please refer to further information. Figure 1 In some embodiments, the high-voltage pin 30 includes a first input pin PFC1 and an output pin P, the low-voltage pin 40 includes a first control pin G1 and a first ground pin GND1, and the first boost circuit 10 includes a first switching transistor 101, a first diode 102, and a second diode 103. Specifically, the first electrode of the first switching transistor 101 is connected to the first ground pin GND1, and the control electrode of the first switching transistor 101 is connected to the first control pin G1; the anode of the third diode 202 is connected to the first electrode of the first switching transistor 101, the cathode of the third diode 202 is connected to the second electrode of the first switching transistor 101, the anode of the second diode 103 is connected to the second electrode of the first switching transistor 101 and the first input pin PFC1, and the cathode of the second diode 103 is connected to the output pin P.

[0042] It should be noted that each type of pin may include one or more. When there are multiple pins of the same type, the multiple pins of the same type are arranged adjacent to each other. Understandably, multiple pins of the same type can improve the current carrying capacity. For example, the first input pin PFC1 and the output pin P may each include two, with the two first input pins PFC1 arranged adjacent to each other and the two output pins P arranged adjacent to each other.

[0043] The first switching transistor 101 is used to control the on / off state of the first boost circuit 10. The first switching transistor 101 can switch at a certain frequency in the first boost circuit 10 to achieve voltage increase and power factor correction. The first switching transistor 101 can be either a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). For example, in some examples, the first switching transistor 101 can be a MOSFET; in other examples, the first switching transistor 101 can be an IGBT.

[0044] The first electrode of the first switching transistor 101 is the collector, the second electrode is the emitter, and the control electrode is the gate. That is, the collector of the first switching transistor 101 is connected to the first ground pin GND1, the emitter of the first switching transistor 101 is connected to the positive electrode of the second diode 103, and the gate of the first switching transistor 101 is connected to the first control pin G1.

[0045] The first diode 102 is used to prevent reverse voltage from damaging the first switching transistor 101. It should be noted that the first switching transistor 101 is a MOSFET, and the first diode 102 is a parasitic diode of the first switching transistor 101.

[0046] The second diode 103 provides isolation to prevent backflow of current and reduces energy loss of the first switching transistor 101 during operation. The second diode 103 includes either a silicon fast recovery diode (Si-FRD) or a silicon carbide Schottky diode (SiC Schottky diode). For example, in some examples, the second diode 103 can be a silicon fast recovery diode, while in other examples, it can be a silicon carbide Schottky diode.

[0047] It should be noted that silicon fast recovery diodes are semiconductor devices specifically designed for high-speed switching applications. They feature excellent switching characteristics and short reverse recovery times, significantly improving power supply efficiency. Silicon carbide Schottky diodes are metal-semiconductor devices that utilize the rectification characteristics created by the contact barrier between a metal and an N-type semiconductor. They offer advantages such as high voltage withstand capability, high-temperature stability, and fast switching speed.

[0048] Thus, by setting up the first switching transistor 101, the first diode 102, and the second diode 103, the power factor correction function of the first boost circuit 10 can be realized.

[0049] Please refer to further information. Figure 1In some embodiments, the high-voltage pin 30 includes a second input pin PFC2 and an output pin P, the low-voltage pin 40 includes a second control pin G2 and a second ground pin GND2, and the second boost circuit 20 includes a second switching transistor 201, a third diode 202, and a fourth diode 203. The first terminal of the second switching transistor is connected to the second ground pin GND2, and the control terminal of the second switching transistor 201 is connected to the second control pin G2. The anode of the third diode 202 is connected to the first terminal of the second switching transistor 201, and the cathode of the third diode 202 is connected to the second terminal of the second switching transistor 201. The anode of the fourth diode 203 is connected to the second terminal of the second switching transistor 201 and the second input pin PFC2, and the cathode of the fourth diode 203 is connected to the output pin P.

[0050] Specifically, the second switching transistor 201 is used to control the on / off state of the second boost circuit 20. The second switching transistor 201 can switch at a certain frequency in the second boost circuit 20 to achieve voltage increase and power factor correction. The second switching transistor 201 can be either a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). For example, in some examples, the second switching transistor 201 can be a MOSFET; in other examples, the second switching transistor 201 can be an IGBT.

[0051] The first electrode of the second switching transistor 201 is the collector, the second electrode is the emitter, and the control electrode is the gate. That is, the collector of the second switching transistor 201 is connected to the second ground pin GND2, the emitter of the second switching transistor 201 is connected to the positive electrode of the fourth diode 203, and the gate of the second switching transistor 201 is connected to the second control pin G2.

[0052] The third diode 202 is used to prevent reverse voltage from damaging the second switching transistor 201. It should be noted that when the second switching transistor 201 is a MOSFET, the third diode 202 is a parasitic diode of the second switching transistor 201.

[0053] The fourth diode 203 provides isolation to prevent backflow of current and reduces energy loss during the switching process of the second switching transistor 201. The fourth diode 203 includes either a silicon fast recovery diode or a silicon carbide Schottky diode. For example, in some examples, the fourth diode 203 can be a silicon fast recovery diode, while in other examples, it can be a silicon carbide Schottky diode.

[0054] Thus, by setting up the second switching transistor 201, the third diode 202 and the fourth diode 203, the power factor correction function of the second boost circuit 20 can be realized.

[0055] like Figure 1 As shown, in some embodiments, the low-voltage pin 40 further includes a first detection pin NTC1 and a second detection pin NTC2, and the power factor correction package device 100 further includes a thermistor 301, which is packaged on the substrate 1 and connected to the first detection pin NTC1 and the second detection pin NTC2 respectively.

[0056] Thermistor 301 is used to monitor the temperature of the power factor correction package 100. Understandably, when the first boost circuit 10 and the second boost circuit 20 are working, the first switching transistor 101 and the second switching transistor 201 need to switch at a certain frequency, which causes the temperature of the entire power factor correction package to rise. Therefore, thermistor 301 can monitor the temperature of the power factor correction package 100 in real time, thereby avoiding damage to the first boost circuit 10 or the second circuit due to high temperature.

[0057] For example, in some examples, both the first switching transistor 101 and the second switching transistor 201 are IGBTs, and the temperature read by the thermistor 301 has a linear relationship with the IGBT junction temperature Tj (e.g., Figure 2 (As shown). Therefore, by reading the temperature of the thermistor 301, the IGBT junction temperature can be prevented from exceeding its rated maximum value.

[0058] The electronic device according to the embodiments of this application includes the power factor correction package device 100 of any of the above embodiments.

[0059] In the electronic device of this application embodiment, the first boost circuit 10 and the second boost circuit 20 are packaged and integrated on the substrate 1 to form a single device. In this way, the number of devices is reduced while ensuring power factor correction, which facilitates installation and wiring. Furthermore, it can save space and significantly reduce production costs. The high-voltage pin 30 and the low-voltage pin 40 are located on opposite sides of the substrate 1, which can avoid the crossover of high and low voltage, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0060] The electronic equipment in this application can be electrical equipment such as air conditioning equipment.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0062] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A power factor correction packaged device, characterized in that, It includes a substrate and a first boost circuit, a second boost circuit, a high-voltage pin, and a low-voltage pin packaged on the substrate; the high-voltage pin and the low-voltage pin are respectively located on opposite sides of the substrate, and the first boost circuit and the second boost circuit are both connected to the high-voltage pin and the low-voltage pin.

2. The power factor correction packaged device according to claim 1, characterized in that, The high-voltage pins include a first input pin and an output pin, the low-voltage pins include a first control pin and a first ground pin, and the first boost circuit includes: A first switching transistor, wherein the first terminal of the first switching transistor is connected to the first ground pin, and the control terminal of the first switching transistor is connected to the first control pin; A first diode, the positive terminal of which is connected to the first terminal of the first switching transistor, and the negative terminal of which is connected to the second terminal of the first switching transistor; The second diode has its anode connected to the second terminal of the first switching transistor and the first input pin, and its cathode connected to the output pin.

3. The power factor correction packaged device according to claim 2, characterized in that, The first switching transistor includes a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.

4. The power factor correction packaged device according to claim 2, characterized in that, The second diode includes either a silicon fast recovery diode or a silicon carbide Schottky diode.

5. The power factor correction packaged device according to claim 1, characterized in that, The high-voltage pin includes a second input pin and an output pin, the low-voltage pin includes a second control pin and a second ground pin, and the second boost circuit includes: The second switching transistor has its first terminal connected to the second ground pin and its control terminal connected to the second control pin. A third diode, wherein the anode of the third diode is connected to the first terminal of the second switching transistor, and the cathode of the third diode is connected to the second terminal of the second switching transistor; A fourth diode, the positive terminal of which is connected to the second terminal of the second switching transistor and the second input pin, and the negative terminal of which is connected to the output pin.

6. The power factor correction packaged device according to claim 5, characterized in that, The second switching transistor includes either a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.

7. The power factor correction packaged device according to claim 5, characterized in that, The fourth diode includes either a silicon fast recovery diode or a silicon carbide Schottky diode.

8. The power factor correction packaged device according to claim 1, characterized in that, The low-voltage pins include a first detection pin and a second detection pin, and the power factor correction package further includes: A thermistor is packaged on the substrate and connected to a first detection pin and a second detection pin, respectively.

9. The power factor correction packaged device according to claim 1, characterized in that, The first boost circuit, the second boost circuit, the high-voltage pin, and the low-voltage pin are packaged on the substrate using a dual in-line package (DIP) process.

10. An electronic device, characterized in that, Includes the power factor correction packaged device as described in any one of claims 1-9.

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