Chip packaging structure and electronic device

Abstract

The utility model provides a chip packaging structure and an electronic device. The chip packaging structure comprises a first packaging substrate; the first chip is positioned on the second surface of the first packaging substrate and is connected with the wire in the first packaging substrate; the first plastic packaging layer is positioned on one side, far away from the second surface, of the first packaging substrate and the first chip; the second packaging substrate is located on the side, away from the first packaging substrate, of the first plastic packaging layer, the second packaging substrate is connected with the second face of the first packaging substrate through copper columns penetrating through the first plastic packaging layer, and the second packaging substrate comprises a rewiring layer; the second chip is positioned on the fourth surface of the second packaging substrate and is connected with the wire in the second packaging substrate; and the second plastic packaging layer is positioned on one side, far away from the fourth surface, of the second packaging substrate and the second chip. According to the packaging structure, the rewiring layer is used for replacing the traditional adapter plate design in the packaging structure, so that the packaging structure can adapt to smaller pin spacing and more input / output interfaces.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a chip packaging structure and electronic device. Background Technology

[0002] In existing technologies, adapter boards are commonly used as a connection solution for high-bandwidth memory (HBM) chips, but they have some obvious disadvantages.

[0003] First, the use of an adapter board increases the complexity and size of the package structure. As an additional component, the adapter board requires extra space for installation, which leads to an increase in the overall size of the package structure. Meanwhile, current electronic products strive for miniaturization and thinner designs.

[0004] Secondly, adapter boards may introduce additional signal delay and loss. The circuitry and connection points on the adapter board may increase the signal transmission path and impedance, leading to a decrease in signal quality.

[0005] Furthermore, with the continuous advancement of semiconductor technology, component sizes are shrinking, and lead pitch is also decreasing. However, due to design and manufacturing limitations, adapter boards often struggle to accommodate such small lead pitches. This makes component connections difficult during packaging, potentially leading to poor connections or short circuits. Adapter boards cannot accommodate even smaller lead pitches and more input / output interfaces, thus failing to meet the demands for higher integration and richer functionality. Utility Model Content

[0006] To at least overcome the aforementioned deficiencies in the prior art, this application provides a chip packaging structure and an electronic device, the chip packaging structure comprising:

[0007] A first packaging substrate, the first packaging substrate including opposing first and second surfaces;

[0008] The first chip is located on the second side of the first packaging substrate and is connected to the wiring in the first packaging substrate.

[0009] The first molding layer is located on the side of the first packaging substrate and the first chip away from the second surface;

[0010] The second packaging substrate is located on the side of the first molding layer away from the first packaging substrate. The second packaging substrate includes a third side and a fourth side opposite to each other. The second packaging substrate is connected to the second side of the first packaging substrate through a copper pillar penetrating the first molding layer. The second packaging substrate includes a redistribution layer.

[0011] The second chip is located on the fourth side of the second packaging substrate and is connected to the traces in the second packaging substrate.

[0012] The second molding layer is located on the side of the second packaging substrate and the second chip away from the fourth surface.

[0013] In some possible implementations, the second packaging substrate includes an insulating layer in which traces are provided from the third surface to the fourth surface.

[0014] In some possible implementations, the first chip includes a system-on-a-chip (SoC).

[0015] In some possible implementations, the second chip includes a high-bandwidth memory chip.

[0016] In some possible implementations, the first packaging substrate includes a redistribution layer.

[0017] In some possible implementations, the materials used for the first and second molding layers include epoxy resin.

[0018] In some possible implementations, the first chip further includes a first solder ball, through which the first chip is connected to the first packaging substrate;

[0019] The second chip also has a second solder ball, and the second chip is connected to the second packaging substrate via the second solder ball.

[0020] In some possible implementations, a third solder ball is also attached to the first side of the first packaging substrate.

[0021] In some possible implementations, the first solder ball includes a plurality of first solder balls; the second solder ball includes a plurality of second solder balls; and the third solder ball includes a plurality of third solder balls.

[0022] This application also provides an electronic device, including the chip packaging structure described in any one of the foregoing claims.

[0023] Based on any of the above aspects, this application provides a chip packaging structure and electronic device. By using a redistribution layer to replace the traditional adapter board design in the packaging structure, the packaging structure can handle smaller pin pitches, meaning more components can be integrated within the same package space, thus achieving higher integration and richer functionality. Simultaneously, the redistribution layer also provides more input / output interfaces, further enhancing the connectivity and data transmission efficiency of the packaging structure. This solution enables the packaging structure to maintain high performance while achieving smaller size and lighter weight. For modern electronic devices, this not only meets users' demands for miniaturization and portability but also provides more possibilities for product design and manufacturing. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this application;

[0026] Figure 2 A schematic diagram of the first packaging unit provided in an embodiment of this application;

[0027] Figure 3 This is a second schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0028] Figure 4 This is the third schematic diagram of the chip packaging structure provided in the embodiments of this application.

[0029] Icons: 10 - Chip package structure; 100 - First packaging unit; 110 - First packaging substrate; 111 - First side; 112 - Second side; 113 - Third solder ball; 114 - Copper pillar; 120 - First chip; 121 - First solder ball; 130 - First molding compound layer; 200 - Second packaging unit; 210 - Second packaging substrate; 211 - Third side; 212 - Fourth side; 213 - Wiring trace; 214 - Insulating layer; 220 - Second chip; 221 - Second solder ball; 230 - Second molding compound layer. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0033] In the description of this application, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The inventors discovered that while adapter boards are commonly used as a connection solution for High Bandwidth Memory (HBM) chips in existing technologies, they have several significant disadvantages. The use of adapter boards increases the complexity and size of the package structure, while current electronic products strive for miniaturization and thinness. Furthermore, with continuous advancements in semiconductor technology, component sizes are shrinking, and pin pitches are also decreasing. However, due to design and manufacturing limitations, adapter boards often struggle to accommodate these small pin pitches. This leads to difficulties in connecting components during the packaging process, potentially resulting in poor connections or short circuits. Adapter boards cannot accommodate even smaller pin pitches and more input / output interfaces, failing to meet the demands of higher integration and richer functionality.

[0036] This application provides a chip packaging structure 10, please refer to... Figure 1 ,include:

[0037] A first packaging substrate 110 includes a first surface 111 and a second surface 112 facing each other; a first chip 120 is located on the second surface 112 of the first packaging substrate 110 and is connected to a trace 213 in the first packaging substrate 110; and a first molding layer 130 is located on the side of the first packaging substrate 110 and the first chip 120 away from the second surface 112.

[0038] A second packaging substrate 210 is located on the side of the first molding compound 130 away from the first packaging substrate 110. The second packaging substrate 210 includes a third surface 211 and a fourth surface 212 opposite to each other. The second packaging substrate 210 is connected to the second surface 112 of the first packaging substrate 110 through a copper pillar 114 penetrating the first molding compound 130. The second packaging substrate 210 includes a redistribution layer; a second chip 220 is located on the fourth surface 212 of the second packaging substrate 210 and is connected to a trace 213 in the second packaging substrate 210; and a second molding compound 230 is located on the side of the second packaging substrate 210 and the second chip 220 away from the fourth surface 212.

[0039] In this embodiment, the second packaging substrate 210 uses a redistribution layer to replace the original adapter board, and the second chip 220 is connected to its fourth side 212. The second chip 220 uses a high-bandwidth memory chip, enabling the chip packaging structure 10 to handle smaller pin pitches, that is, more components can be integrated within the same packaging space, thereby achieving higher integration and richer functionality. Simultaneously, the redistribution layer on the second packaging substrate 210 also provides more input / output interfaces, further enhancing the connectivity and data transmission efficiency of the chip packaging structure 10. This embodiment enables the packaging structure to maintain high performance while achieving a smaller size and lighter weight. For modern electronic devices, this not only meets users' needs for miniaturization and portability but also provides more possibilities for product design and manufacturing.

[0040] Optionally, the chip package structure 10 can be formed using the following method.

[0041] First, please refer to Figure 2A first packaging substrate 110 is prepared, which includes traces 213 for electrical connection. A first chip 120 is placed on the second surface 112 of the first packaging substrate 110. The contact points of the first chip 120 are electrically connected to the traces 213 in the first packaging substrate 110 using a conductive material. A liquid or semi-solid molding compound is applied to the first packaging substrate 110 and the side of the first chip 120 away from the second surface 112, and the molding compound is cured by heating or other curing methods to form a first molding layer 130. At this time, a first packaging unit 100 is formed.

[0042] Next, a second packaging substrate 210 is prepared, which has a redistribution layer.

[0043] Subsequently, a second chip 220 is prepared, which has a second solder ball 221.

[0044] Finally, please refer to Figure 3 The traces 213 on the third surface 211 of the second packaging substrate 210 are connected to the first packaging unit 100 via copper pillars 114. The traces 213 on the fourth surface 212 of the second packaging substrate 210 are connected to the second chip 220 via second solder balls 221. A liquid or semi-solid molding compound is applied to the side of the second packaging substrate 210 and the second chip 220 away from the fourth surface 212. The molding compound is cured by heating or other curing methods to form a second molding layer 230. A third solder ball 113 is formed on the first surface 111 of the first packaging substrate 110. At this time, the chip packaging structure of this embodiment is formed.

[0045] Alternatively, the following methods can also be used to form the chip package structure 10.

[0046] First, please refer to Figure 2 A first packaging substrate 110 is prepared, which includes traces 213 for electrical connection. A first chip 120 is placed on the second surface 112 of the first packaging substrate 110. The contact points of the first chip 120 are electrically connected to the traces 213 in the first packaging substrate 110 using a conductive material. A liquid or semi-solid molding compound is applied to the first packaging substrate 110 and the side of the first chip 120 away from the second surface 112, and the molding compound is cured by heating or other curing methods to form a first molding layer 130. At this time, a first packaging unit 100 is formed.

[0047] Next, a second packaging substrate 210 is prepared, which includes traces 213 for electrical connections, using a redistribution layer. A second chip 220 is placed on the fourth surface 212 of the second packaging substrate 210. The contacts of the second chip 220 are electrically connected to the traces 213 in the second packaging substrate 210 using a conductive material. A liquid or semi-solid molding compound is applied to the side of the second packaging substrate 210 and the second chip 220 away from the fourth surface 212, and the molding compound is cured by heating or other curing methods to form a second molding layer 230. At this point, a second packaging unit 200 is formed.

[0048] Finally, please refer to Figure 4 The copper pillar 114 is connected to the trace 213 on the second packaging substrate 210, thereby connecting the first packaging unit 100 and the second packaging unit 200. A third solder ball 113 is formed on the first surface 111 of the first packaging substrate 110. At this time, the chip packaging structure in this embodiment is formed.

[0049] In some possible implementations, please refer to Figure 1 The second packaging substrate 210 includes an insulating layer 214, in which a trace 213 is provided, extending from the third surface 211 to the fourth surface 212.

[0050] In this embodiment, an insulating layer 214 is embedded within the second packaging substrate 210 to provide good electrical isolation while maintaining sufficient mechanical strength to cope with complex and changing working environments. Numerous traces 213 are arranged within the insulating layer 214, extending from the third surface 211 to the fourth surface 212. These traces 213 are not only used for signal transmission but also ensure minimal signal loss and interference within the highly integrated packaging structure. The second chip 220 and the first packaging substrate 110 are connected via the traces 213.

[0051] In some possible implementations, the first chip 120 includes a system-on-a-chip (SoC).

[0052] In this embodiment, the first chip 120 is a system-on-a-chip (SoC). A SoC is a highly integrated circuit that integrates multiple functional modules such as processors, memory, and input / output ports onto a single chip, thereby greatly improving the system's integration and performance. By being disposed on the second side 112 of the first packaging substrate 110, such a SoC can not only achieve efficient signal processing and data transmission, but also seamlessly connect to external devices or systems through the traces 213 in the first packaging substrate 110.

[0053] In some possible implementations, the second chip 220 includes a high-bandwidth memory chip.

[0054] In this embodiment, the second chip 220 uses a high-bandwidth memory chip. High-bandwidth memory chips have good data transmission speed and low latency characteristics, making them suitable for high-performance computing, graphics processing, and artificial intelligence fields that require processing large amounts of data. By being disposed on the fourth surface 212 of the second packaging substrate 210, the high-bandwidth memory chip is closely connected to the traces 213 in the second packaging substrate 210, thereby ensuring high-speed data transmission and real-time processing.

[0055] In some possible implementations, the first packaging substrate 110 includes a redistribution layer.

[0056] In this embodiment, the first packaging substrate 110 further includes a redistribution layer, which enables the chip packaging structure 10 to better handle smaller pin pitches. Simultaneously, the redistribution layer on the first packaging substrate 110 provides more input / output interfaces, further enhancing the connectivity and data transmission efficiency of the chip packaging structure 10. This chip packaging structure 10 can be seamlessly connected to external devices or systems through the traces 213 in the first packaging substrate 110. This embodiment achieves a smaller size and lighter weight while maintaining high performance in the packaging structure.

[0057] In some possible implementations, the materials used for the first molding layer 130 and the second molding layer 230 include epoxy resin.

[0058] Epoxy resin, as a thermosetting plastic, possesses excellent insulating properties, effectively isolating the internal circuitry from direct contact with the external environment, preventing electrical short circuits and electromagnetic interference, and ensuring the normal operation of the internal chip and wiring 213 within the package structure. Simultaneously, it provides robust physical protection, preventing the chip from mechanical damage, moisture erosion, and chemical corrosion, extending the chip's lifespan and improving the overall reliability of the package structure. Furthermore, epoxy resin exhibits good thermal stability, capable of withstanding high and low temperature environments within a certain range without performance changes. Therefore, in this embodiment, epoxy resin is selected as the molding layer material for both the first molding layer 130 and the second molding layer 230.

[0059] In some possible implementations, please refer to Figure 1 The first chip 120 also has a first solder ball 121, and the first chip 120 is connected to the first packaging substrate 110 via the first solder ball 121; the second chip 220 also has a second solder ball 221, and the second chip 220 is connected to the second packaging substrate 210 via the second solder ball 221.

[0060] In this embodiment, the first chip 120 is electrically and mechanically connected to the first packaging substrate 110 via the first solder ball 121, while the second chip 220 is connected to the second packaging substrate 210 via the second solder ball 221. This connection method not only provides a reliable electrical path but also ensures a stable connection between the chip and the packaging substrate. The solder ball connection effectively disperses stress, reducing the risk of connection failure caused by temperature changes or mechanical vibration. Furthermore, the solder ball connection facilitates automated production and testing, improving production efficiency.

[0061] In some possible implementations, please refer to Figure 1 The first surface 111 of the first packaging substrate 110 is also connected to a third solder ball 113.

[0062] In this embodiment, a third solder ball 113 is also connected to the first surface 111 of the first packaging substrate 110. These third solder balls 113 can be used for electrical connection with external devices or systems, thereby expanding the functionality and application range of the packaging structure. Through the third solder balls 113, the packaging structure can be easily connected to other electronic components or circuit boards to achieve more complex system integration.

[0063] In some possible implementations, please refer to Figure 1 The first solder ball 121 includes a plurality of first solder balls 121; the second solder ball 221 includes a plurality of second solder balls 221; and the third solder ball 113 includes a plurality of third solder balls 113.

[0064] In this embodiment, the first solder ball 121, the second solder ball 221, and the third solder ball 113 are all multiple. This design can further increase the number of connection points, improving the reliability and stability of the electrical connection. Multiple solder balls can also distribute current and heat, reducing the risk of failure due to single-point overload or overheating. In addition, multiple solder ball connections provide greater flexibility, allowing the position and number of connection points to be adjusted as needed.

[0065] This application also provides an electronic device including the chip packaging structure 10 described in any of the foregoing claims. The electronic device in this embodiment not only boasts high performance but also achieves smaller size and lighter weight.

[0066] In summary, this application provides a chip packaging structure 10 and an electronic device. The chip packaging structure 10 includes: a first packaging substrate 110; a first chip 120 located on a second surface 112 of the first packaging substrate 110 and connected to a trace 213 in the first packaging substrate 110; a first molding compound 130 located on the side of the first packaging substrate 110 and the first chip 120 away from the second surface 112; and a second packaging substrate 210 located on the first molding compound 130. On the side away from the first packaging substrate 110, the second packaging substrate 210 is connected to the second surface 112 of the first packaging substrate 110 via a copper pillar 114 penetrating the first molding compound 130. The second packaging substrate 210 includes a redistribution layer; a second chip 220 located on the fourth surface 212 of the second packaging substrate 210 and connected to traces 213 in the second packaging substrate 210; and a second molding compound 230 located on the side of the second packaging substrate 210 and the second chip 220 away from the fourth surface 212. This application uses a redistribution layer in the packaging structure to replace the traditional adapter board design, enabling the packaging structure to accommodate smaller pin pitches and more input / output interfaces.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip packaging structure, characterized in that, include: A first packaging substrate, the first packaging substrate including opposing first and second surfaces; The first chip is located on the second side of the first packaging substrate and is connected to the wiring in the first packaging substrate. The first molding layer is located on the side of the first packaging substrate and the first chip away from the second surface; The second packaging substrate is located on the side of the first molding layer away from the first packaging substrate. The second packaging substrate includes a third side and a fourth side opposite to each other. The second packaging substrate is connected to the second side of the first packaging substrate through a copper pillar penetrating the first molding layer. The second packaging substrate includes a redistribution layer. The second chip is located on the fourth side of the second packaging substrate and is connected to the traces in the second packaging substrate. The second molding layer is located on the side of the second packaging substrate and the second chip away from the fourth surface.

2. The chip packaging structure according to claim 1, characterized in that, The second packaging substrate includes an insulating layer, in which traces are provided from the third surface to the fourth surface.

3. The chip packaging structure according to claim 1, characterized in that, The first chip includes a system-on-a-chip (SoC).

4. The chip packaging structure according to claim 1, characterized in that, The second chip includes a high-bandwidth memory chip.

5. The chip packaging structure according to claim 1, characterized in that, The first packaging substrate includes a redistribution layer.

6. The chip packaging structure according to claim 1, characterized in that, The materials used in the first and second molding layers include epoxy resin.

7. The chip packaging structure according to claim 1, characterized in that, The first chip also has a first solder ball, and the first chip is connected to the first packaging substrate via the first solder ball; The second chip also has a second solder ball, and the second chip is connected to the second packaging substrate via the second solder ball.

8. The chip packaging structure according to claim 1, characterized in that, A third solder ball is also connected to the first side of the first packaging substrate.

9. The chip packaging structure according to any one of claims 7-8, characterized in that, The chip packaging structure includes multiple first solder balls, multiple second solder balls, and / or multiple third solder balls.

10. An electronic device, characterized in that, Includes the chip packaging structure described in any one of claims 1-9.

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