Defect test structure of gate oxide layer
By setting a gate oxide layer defect testing structure within the wafer dicing channel and using an electron beam gun to scan and detect gate oxide layer defects, the problem of not being able to detect defect locations in advance in existing technologies is solved, achieving online detection and resource saving.
Patent Information
- Application Number
- CN202423070509.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-12-11
AI Technical Summary
Existing technologies cannot detect the location of defects in the gate oxide layer in the early stages of wafer fabrication, leading to resource waste and device performance degradation.
A gate oxide defect test structure is set in the dicing channel of the wafer, including a first shallow trench isolation region, a test active region and a metal gate structure, and the gate oxide defect is detected by scanning with an electron beam gun.
This technology enables online detection of defects in the gate oxide layer during semiconductor device fabrication, avoiding resource waste caused by discovering defects only after device fabrication is complete, and improving the accuracy and efficiency of detection.
Smart Images
Figure CN223501876U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of testing in semiconductor device fabrication, and more particularly to a defect testing structure for gate oxide layers. Background Technology
[0002] In the advanced HKMG (High-k Metal Gate) process, the gate material of the transistor is replaced from polysilicon to a high-dielectric-constant metal, which not only improves the performance of the device but also reduces its power consumption.
[0003] Although device performance has been significantly improved, the requirements for gate oxide quality are becoming increasingly stringent due to the continuous reduction in gate oxide thickness. Defects in the gate oxide layer can lead to gate leakage, thereby affecting the device's switching control capability. Therefore, defect detection in the gate oxide layer is crucial.
[0004] However, current technologies for detecting defects in the gate oxide layer typically involve electrical testing after wafer fabrication, using the leakage current of the gate to determine if defects exist. The problems with existing testing methods are: 1. They cannot distinguish the location of defects in the gate oxide layer; 2. Defects are only discovered after wafer fabrication, leading to significant resource waste.
[0005] Therefore, providing a test structure that can detect defective regions in the gate oxide layer in advance has become a technical problem that the industry urgently needs to solve. Utility Model Content
[0006] This invention provides a defect testing structure for a gate oxide layer to detect defective regions in advance.
[0007] To address the aforementioned technical problems, the present invention provides a defect testing structure for a gate oxide layer. This defect testing structure is disposed within a dicing channel of a wafer and includes:
[0008] A first shallow trench isolation area and a test active area are both located within the cutting channel. The first shallow trench isolation area and the test active area have a preset step height, and the first shallow trench isolation area surrounds the test active area.
[0009] A gate oxide layer, wherein the gate oxide layer is located on the surface of the test active region;
[0010] At least one first metal gate structure is disposed in the boundary region between the first shallow trench isolation region and the test active region, and each first metal gate structure includes a first metal gate.
[0011] At least one second metal gate structure is disposed on the surface of the gate oxide layer within the test active region, and each second metal gate structure includes a second metal gate.
[0012] Optionally, the structure may also include:
[0013] The second shallow trench isolation area is located inside the test active area and is surrounded by the test active area;
[0014] At least one third metal gate structure is disposed in the boundary region between the second shallow trench isolation region and the test active region, and each of the third metal gate structures includes a third metal gate.
[0015] The areas of the first shallow trench isolation zone and the second shallow trench isolation zone are different.
[0016] Optionally, the number of the first metal gate structures includes at least four, and the at least four first metal gate structures are respectively disposed on the four sides of the boundary region between the first shallow trench isolation region and the test active region;
[0017] The first metal gate structures disposed on the first and third sides are arranged at intervals along the first direction, and the first metal gate structures disposed on the second and fourth sides are arranged at intervals along the second direction, wherein the first direction and the second direction are perpendicular to each other.
[0018] Optionally, the number of the second metal gate structures includes at least four, and the at least four second metal gate structures are respectively disposed on the four sides of the test active region;
[0019] The second metal gate structures disposed on the first and third sides are arranged at intervals along the first direction, and the second metal gate structures disposed on the second and fourth sides are arranged at intervals along the second direction.
[0020] Optionally, the number of the third metal gate structures includes at least four, and the at least four third metal gate structures are respectively disposed on the four sides of the boundary region between the second shallow trench isolation region and the test active region;
[0021] The third metal gate structures disposed on the first and third sides are arranged at intervals along the first direction, and the third metal gate structures disposed on the second and fourth sides are arranged at intervals along the second direction.
[0022] Optionally, the spacing between each metal gate structure is greater than or equal to the first threshold.
[0023] Optionally, each of the first metal gate structure, each of the second metal gate structure and each of the third metal gate structure further includes a first sidewall, which is attached to the sidewall of the corresponding metal gate and located on the corresponding gate oxide layer.
[0024] Optionally, each of the first metal gate structure, each of the second metal gate structure and each of the third metal gate structure further includes a second sidewall, which is attached to the corresponding first sidewall and located on the corresponding gate oxide layer.
[0025] Optionally, the defect testing structure further includes: a silicide barrier layer, an etch stop layer, and a second silicon oxide layer;
[0026] The silicide barrier layer covers the test active region surface, the first shallow trench isolation region surface, and the second shallow trench isolation region surface between each of the first metal gate structure, each of the second metal gate structure, and each of the third metal gate structure. The silicide barrier layer is also attached to the second sidewall of each of the first metal gate structure, each of the second metal gate structure, and each of the third metal gate structure.
[0027] The etching stop layer covers the surface of the silicide barrier layer;
[0028] The second silicon oxide layer covers the surface of the etch stop layer;
[0029] Each of the metal gates is exposed.
[0030] Optionally, the silicide barrier layer comprises a third silicon dioxide layer and a third silicon nitride layer stacked sequentially.
[0031] The third silicon dioxide layer covers the test active region surface, the first shallow trench isolation region surface, and the second shallow trench isolation region surface between each first metal gate structure, each second metal gate structure, and each third metal gate structure. The third silicon dioxide layer is also attached to the second sidewall of each first metal gate structure, each second metal gate structure, and each third metal gate structure.
[0032] The third silicon nitride layer covers the surface of the third silicon dioxide layer;
[0033] Each of the metal gates is exposed.
[0034] Compared with the prior art, the technical solution provided by this utility model has the following beneficial effects:
[0035] The gate oxide defect testing structure provided by this utility model includes a first shallow trench isolation region and a test active region, wherein the first shallow trench isolation region surrounds the test active region. By setting at least one first metal gate structure and at least one second metal gate structure in the boundary region between the first shallow trench isolation region and the test active region, and within the test active region, the defect status of the gate oxide layer in the test structure can be determined by scanning the metal gate structure with an electron beam gun. Furthermore, because the test structure is fabricated simultaneously with the actual semiconductor device, the defect status of the gate oxide layer in the test structure reflects the defect status of the gate oxide layer in the actual device. Moreover, this test structure enables online detection during semiconductor device fabrication, avoiding wafer waste caused by performing defect detection only after device fabrication is completed.
[0036] Furthermore, the defect testing structure also includes: a second shallow trench isolation region and at least one third metal gate structure; the second shallow trench isolation region is surrounded by the test active region, and the at least one third metal gate structure is disposed at the boundary region between the second shallow trench isolation region and the test active region. Because the areas of the first shallow trench isolation region and the second shallow trench isolation region are different, the stress applied to the gate oxide layer by the first shallow trench isolation region and the stress applied to the gate oxide layer by the second shallow trench isolation region are different. Therefore, the impact of the different stresses applied to the gate oxide layer on the gate oxide layer quality can be compared.
[0037] Furthermore, by setting at least four of the first metal gate structures, each located on one of the four sides of the boundary region between the first shallow trench isolation region and the test active region, and by setting at least four of the third metal gate structures, each located on one of the four sides of the boundary region between the second shallow trench isolation region and the test active region, it is possible to avoid situations where, due to overlay errors, neither the first metal gate structure nor the third metal gate structure in the first or second direction can simultaneously contact the test active region and the corresponding shallow trench isolation region. In this case, the gate oxide defect detection can be completed through the first metal gate structure and the third metal gate structure in the other direction. Attached Figure Description
[0038] Figure 1 This is a simplified cross-sectional schematic diagram of an embodiment of a semiconductor device layer;
[0039] Figure 2 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 1 ;
[0040] Figure 3 yes Figure 2 The diagram shows a simplified cross-sectional view of the defect test structure of the gate oxide layer along the first section.
[0041] Figure 4 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 2 ;
[0042] Figure 5 yes Figure 4 The diagram shows a simplified cross-sectional view of the defect test structure of the gate oxide layer along the first section.
[0043] Figure 6 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 3 ;
[0044] Figure 7 A flowchart illustrating the method for preparing a defect testing structure for the gate oxide layer provided in this embodiment of the invention;
[0045] Figures 8 to 15 These are simplified cross-sectional schematic diagrams of the preparation method of the gate oxide layer defect test structure provided in this utility model embodiment at different preparation stages. Detailed Implementation
[0046] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model. The terms "first", "second", "third", "fourth", etc. (if present) in the specification, claims and the above-mentioned drawings of the present utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present utility model described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.
[0047] Figure 1 This is a simplified cross-sectional schematic diagram of an embodiment of a semiconductor device layer.
[0048] Please refer to Figure 1An embodiment of the semiconductor device layer includes a first active region 100, a second active region 101, a gate oxide layer 102 and a polysilicon layer 103 sequentially stacked on the first active region 100, a shallow trench isolation region 104 for isolating the first active region 100, a first contact hole 105 and a first metal interconnect layer 106 located on the polysilicon layer 103, and a second contact hole 107 and a second metal interconnect layer 108 located on the second active region 101. Figure 1 It can be seen that the gate oxide layer 102 covers the second active region 101 and the boundary area between the second active region 101 and the shallow trench isolation region 104.
[0049] In the actual process, before filling the shallow trench with silicon dioxide, a silicon nitride film is first formed on the surface of the active region to protect the surface. Subsequently, the silicon dioxide is polished to bring the deposited silicon dioxide and the silicon nitride film to the same horizontal plane. Then, a patterned mask layer is used to etch the silicon nitride film to expose the active region. Therefore, the silicon dioxide in the shallow trench isolation region 104 will naturally be higher than the surface of the first active region 102 by the thickness of the silicon nitride film, forming a certain step height difference. This causes greater stress on the gate oxide layer 102 at the interface between the shallow trench isolation region 104 and the second active region 101, making the gate oxide layer 102 grown in this interface region more prone to quality problems and resulting in gate leakage. Therefore, when performing defect detection on the gate oxide layer 102, in addition to detecting whether there are defects in the gate oxide layer 102, it is also crucial to distinguish whether the defects in the gate oxide layer 102 are in the active region or in the boundary area between the shallow trench isolation region and the active region.
[0050] However, as described in the background section, existing technologies perform electrical testing on the test structure only after the semiconductor device fabrication is complete, and determine whether there are defects in the gate oxide layer 102 solely by testing the leakage current of the gate. Therefore, Figure 1 Taking the illustrated embodiment as an example, the existing solution has the following problems:
[0051] 1. It can only test whether there are defects in the gate oxide layer 102 of the device layer, but it cannot determine whether the defect in the gate oxide layer 102 is inside the first active region 100 or in the boundary region between the first active region 100 and the gate oxide layer 102, so it is impossible to adjust the process according to the defect location of the gate oxide layer 102.
[0052] 2. Since the existing solution performs defect detection on the gate oxide layer 102 only after the device fabrication is completed, the discovery of defects in the gate oxide layer 102 will render the semiconductor device formed through multiple processes unusable, resulting in a large waste of resources.
[0053] In view of this, the present invention provides a new defect testing structure for the gate oxide layer, which is disposed within the dicing channel of the wafer to effectively solve the problems existing in the prior art.
[0054] in, Figure 2 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 1 . Figure 3 yes Figure 2 The diagram shows a simplified cross-sectional view of the defect test structure of the gate oxide layer along the first section.
[0055] Please refer to Figure 2 and Figure 3 The defect testing structure for the gate oxide layer provided in this embodiment of the present invention includes:
[0056] The first shallow trench isolation area 200 and the test active area 201 are both located within the cutting channel. The first shallow trench isolation area 200 and the test active area 201 have a preset step height, and the first shallow trench isolation area 200 surrounds the test active area 201.
[0057] As an example, for the 55nm process node, the step height between the first shallow trench isolation region 200 and the test active region 201 is 100A-200A. For the 28nm process node, the step height between the first shallow trench isolation region 200 and the test active region 201 is 50A-100A. Therefore, the step height varies for different process nodes and is not limited here.
[0058] Gate oxide layer 208, the gate oxide layer 208 being located on the surface of the test active region;
[0059] At least one first metal gate structure 203, the at least one first metal gate structure 203 being located at the boundary region between the first shallow trench isolation region 200 and the test active region 201, each of the first metal gate structures 203 including a first metal gate; at least one second metal gate structure 204, the at least one second metal gate structure 204 being located on the surface of the gate oxide layer 208 within the test active region 201, each of the second metal gate structures 204 including a second metal gate.
[0060] Specifically, the metal gate structure is located at the boundary between the first shallow trench isolation region 200 and the test active region 201, that is, a part of the first metal gate structure is located on the surface of the gate oxide layer 208 of the test active region 201, and another part of the first metal gate structure is located on the surface of the first shallow trench isolation region.
[0061] Through the above-described technical means, this embodiment of the invention can detect defect regions in the gate oxide layer during the fabrication of semiconductor devices. The specific reasons are as follows:
[0062] The defect testing structure simulates the positional relationship between the shallow trench isolation region and the active region in the device region by setting a first shallow trench isolation region 200 and a test active region 201, with the first shallow trench isolation region 200 surrounding the test active region 201. The defect testing structure simulates the presence of defects in the gate oxide layer 208 located in the boundary region between the first shallow trench isolation region 200 and the test active region 201 by setting at least one first metal gate structure 203, each including a first metal gate, on the gate oxide layer surface. The defect testing structure further simulates the presence of defects in the gate oxide layer 208 located in the active region of the device region by setting at least one second metal gate structure 204 on the gate oxide layer surface within the test active region 201, each including a second metal gate. Therefore, the defect status of the gate oxide layer 208 in the testing structure can reflect the defect status of the gate oxide layer 208 in the actual device.
[0063] An online-controlled electron beam gun scans each metal gate structure, and the electron beam receiver collects charge from each metal gate structure, displaying the collected charge as bright or dark. Finally, based on the sign of the charge output by the electron beam gun and the brightness of the display, metal gate structures with defects in the gate oxide layer 208 can be detected. Furthermore, based on the location of the metal gate structure with the defective gate oxide layer 208, the defective region of the gate oxide layer 208 in the device layer can be determined. The specific principle is as follows:
[0064] If a region of a metal gate structure lacks a defect in the gate oxide layer 208, the negative charges emitted by the electron beam gun will not be released to the substrate but will accumulate within the metal gate, thus being collected by the electron beam receiver and brightening the display. Conversely, if a metal gate structure has a defect in the gate oxide layer 208, the negative charges emitted by the electron beam gun will be released to the substrate and will not accumulate within the metal gate, thus failing to be collected by the electron beam receiver and dimming the display.
[0065] When the electron beam gun fires a negative charge to scan the first metal gate structure 203 located at the boundary between the first shallow trench isolation region 200 and the test active region 201; if the display brightens, it indicates that there are no defects in the gate oxide layer 208 in the area where the first metal gate structure 203 is located, and thus it indicates that there are no defects in the gate oxide layer 208 located at the boundary between the shallow trench isolation region and the active region in the device region; if the display dims, it indicates that there are defects in the gate oxide layer 208 in the area where the first metal gate structure 203 is located, and thus it indicates that there are defects in the gate oxide layer 208 located at the boundary between the shallow trench isolation region and the active region in the device region.
[0066] When the electron beam gun fires a negative charge to scan the second metal gate structure 204 located in the test active region 201; if the display brightens, it indicates that there are no defects in the gate oxide layer 208 in the area where the second metal gate structure 204 is located, and thus it indicates that there are no defects in the gate oxide layer 208 located in the active region of the device region; if the display dims, it indicates that there are defects in the gate oxide layer 208 in the area where the second metal gate structure 204 is located, and thus it indicates that there are defects in the gate oxide layer 208 located in the active region of the device region.
[0067] Of course, if the charge emitted by the electron beam gun is positive, then the criteria for judging the defects of the gate oxide layer 208 are the opposite of those for negative charges, which will not be elaborated here.
[0068] In addition to detecting defect areas in the gate oxide layer 208, since the test structure is usually fabricated simultaneously with the semiconductor device, the electron beam gun can be controlled online to detect defect areas in the gate oxide layer 208 after the metal gate fabrication of the semiconductor device is completed. Compared to existing technologies that perform defect detection after the entire device fabrication is completed, this embodiment of the invention avoids the waste of the entire back-end process due to defects in the gate oxide layer 208, thereby avoiding the scrapping of a large number of wafers.
[0069] It should be noted that, Figure 2 or Figure 3The defect testing structure shown only includes one first metal gate structure 203 and one second metal gate structure 204 because, theoretically, even with only one first metal gate structure 203 and one second metal gate structure 204, defects in the gate oxide layer 208 can be detected. Since the gate oxide layer 208 is actually fabricated using non-directional processes such as thermal oxidation or chemical vapor deposition, the probability of defects in the gate oxide layer 208 grown on different sides of the active region 201 is theoretically the same. Similarly, the probability of defects in the gate oxide layer 208 grown on different sides of the first boundary region is also theoretically the same. Therefore, theoretically, by placing one second metal gate structure 204 on either side of the active region 201, defects in the gate oxide layer 208 grown within the active region 201 can be detected. Similarly, theoretically, placing a first metal gate structure 203 on either side of the boundary between the first shallow trench isolation region 200 and the test active region 201 could also detect whether there are defects in the gate oxide layer 208 grown at the boundary between the first shallow trench isolation region 200 and the test active region 201. Of course, to eliminate other factors affecting the accuracy of the test, Figure 2 or Figure 3 The defect detection structure shown can also include several first metal gate structures and second metal gate structures. Each first metal gate structure is located at the boundary between the first shallow trench isolation region and the test active region. Each second metal gate structure is located within the test active region and corresponds one-to-one with the first metal gate structure. The first metal gate structures can be equidistantly arranged. The number and arrangement of the first and second metal gate structures are not limited here; those skilled in the art can choose according to the actual situation, and will not be elaborated further.
[0070] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.
[0071] in, Figure 4 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 2 . Figure 5 yes Figure 4 The diagram shows a simplified cross-sectional view of the defect test structure of the gate oxide layer along the first section.
[0072] Please refer to Figure 4 and Figure 5 As one specific implementation, the defect testing structure for the gate oxide layer provided in this embodiment of the present invention further includes:
[0073] The second shallow trench isolation area 207 is located inside the test active area 201 and is surrounded by the test active area 201;
[0074] At least one third metal gate structure 205 is located on the surface of the gate oxide layer 208 at the boundary between the second shallow trench isolation region 200 and the test active region 201, and each of the third metal gate structures 205 includes a third metal gate.
[0075] The areas of the first shallow trench isolation region and the second shallow trench isolation region are different. Because the areas of the first shallow trench isolation region 200 and the second shallow trench isolation region 207 are different, the stress applied to the gate oxide layer 208 at the boundary between the first shallow trench isolation region 200 and the test active region 201 is different from the stress applied to the gate oxide layer 208 at the boundary between the second shallow trench isolation region 207 and the test active region 201. This can lead to quality differences between the gate oxide layer located at the boundary between the first shallow trench isolation region and the test active region and the gate oxide layer located at the boundary between the second shallow trench isolation region and the test active region. Therefore, this test structure allows for comparison of the influence of the stress magnitude at the interface between the shallow trench isolation region and the test active region of different areas on the quality of the gate oxide layer at the interface.
[0076] in, Figure 4 or Figure 5 The reason why only one of the third metal gate structures 205 is set in the defect test structure shown is the same as the reason why only one of the first metal gate structures 203 is set, and will not be repeated here.
[0077] in, Figure 6 This is a top view of the defect testing structure for the gate oxide layer provided in this embodiment of the utility model. Figure 3 .
[0078] Please refer to Figure 6 In one specific embodiment, the number of each of the first metal gate structure 203, the second metal gate structure 204, and the third metal gate structure 205 is 12. Three spaced-apart first metal gate structures 203 are respectively disposed on the four sides of the boundary region between the first shallow trench isolation region 200 and the test active region 201. Three spaced-apart second metal gate structures 204 are respectively disposed on the four sides of the test active region 201. Three spaced-apart third metal gate structures 204 are respectively disposed on the four sides of the boundary region between the second shallow trench isolation region 207 and the test active region 201.
[0079] The first metal gate structure 203, the second metal gate structure 204, and the third metal gate structure 204 located on the first and third sides of the boundary region are all arranged at intervals along the first direction A, A. The first metal gate structure 203, the second metal gate structure 204, and the third metal gate structure 204 located on the second and fourth sides of the boundary region are all arranged at intervals along the second direction B, B. The first direction A, A and the second direction B, B are perpendicular to each other.
[0080] Specifically, the spacing between each metal gate structure located in the boundary region between the first shallow trench isolation region 200 and the test active region 201, and in the boundary region between the test active region 201 and the second shallow trench isolation region 207 and the test active region 201, is greater than or equal to a first threshold. The specific value of the first threshold depends on the minimum spacing specified in the design rules of semiconductor devices. However, the design rules of semiconductor devices can vary due to differences in processes, manufacturers, or design requirements. Therefore, the specific value of the first threshold is not limited here.
[0081] Compared to setting only one metal gate structure in the boundary region between the first shallow trench isolation region 200 and the test active region 201, and in the boundary region between the test active region 201 and the second shallow trench isolation region 207 and the test active region 201, setting spaced metal gate structures on all four sides of the boundary region between the first shallow trench isolation region 200 and the test active region 201, on all four sides of the test active region 201, and on all four sides of the boundary region between the second shallow trench isolation region 207 and the test active region 201 greatly increases the detection area for defect detection of the gate oxide layer 208. This effectively avoids situations where the gate oxide layer 208 has special defects that cannot be detected due to process errors or environmental temperature factors, thereby greatly reducing the possibility of missing defects in the gate oxide layer 208.
[0082] Meanwhile, in order to achieve defect detection of the gate oxide layer 208 between the shallow trench isolation region and the active region, it is necessary to ensure that the gate oxide layer 208 simultaneously contacts the test active region 201 and the first shallow trench isolation region 200, and also to ensure that the gate oxide layer 208 simultaneously contacts the test active region 201 and the second shallow trench isolation region 207. However, in the actual process, the fabricated gate oxide layer 208 may be offset in the first direction A'A or the second direction B'B due to overlay errors. This results in the gate oxide layer 208 failing to simultaneously contact the test active region 201 and the corresponding trench isolation region in both the first direction A'A and the second direction B'B, thereby causing the first metal gate structure 203 and the third metal gate structure 205 in the corresponding directions to lose their defect detection function. Because the overlay deviation of the gate oxide layer 208 only affects the metal gate structure in one direction, by providing the first metal gate structure 203 on all four sides of the boundary region between the first shallow trench isolation region 200 and the test active region 201, and by providing the third metal gate structure 205 on all four sides of the boundary region between the second shallow trench isolation region 207 and the test active region 201, it is ensured that when the gate oxide layer 208 is offset towards the first direction A`A or the second direction B, B, defects in the gate oxide layer 208 between the shallow trench isolation region and the active region in the device region can be detected by the first metal gate structure 203 and the third metal gate structure 205 in the other direction.
[0083] certainly, Figure 6 The top view shown is only a specific embodiment of a defect testing structure. In practice, the defect testing structure can also be configured with corresponding metal gate structures on opposite sides, adjacent sides, or any three sides of each region, depending on requirements. This is not limited here. Furthermore, the number of metal gate structures on each side is not limited to three; as long as it conforms to the design rules, any number of metal gate structures can be set according to requirements, and this is also not limited here.
[0084] The following describes the preparation method of the defect testing structure of the gate oxide layer provided in this embodiment of the invention, taking the example that the first metal gate structure, the second metal gate structure, and the third metal gate structure are all disposed on only one side:
[0085] in, Figure 7 A flowchart illustrating the method for preparing a defect testing structure for the gate oxide layer provided in this embodiment of the present invention. Figures 8 to 15 These are simplified cross-sectional schematic diagrams of the preparation method of the gate oxide layer defect test structure provided in this utility model embodiment at different preparation stages.
[0086] Please refer to Figure 7The method for preparing the defect testing structure of the gate oxide layer provided in this embodiment of the present invention specifically includes the following steps:
[0087] S1: Provide a P-type silicon substrate, such as Figure 8 As shown.
[0088] S2: A first shallow trench isolation region 200 is formed in a first region of the P-type silicon substrate, a test active region 201 is formed in a second region of the P-type silicon substrate, and a second shallow trench isolation region 207 is formed in a third region of the P-type silicon substrate; wherein the first region, the second region, and the third region are sequentially adjacent, and the second region surrounds the third region, and the first region surrounds the second region, as shown. Figure 9 As shown.
[0089] Specifically, step S2 includes:
[0090] S211: A pre-oxide layer and a silicon nitride layer are sequentially stacked on the P-type silicon substrate.
[0091] S212: A patterned first mask layer is formed on the silicon nitride layer, the patterned first mask layer comprising: a test active region 201 blocking pattern region, a first shallow trench window region, and a second shallow trench window region. The test active region 201 blocking pattern region corresponds to a second region of the P-type silicon substrate, the first shallow trench window region corresponds to a first region of the P-type silicon substrate, and the second shallow trench window region corresponds to a third region of the P-type silicon substrate.
[0092] S212: Using the patterned first mask layer as a mask, the silicon nitride layer is dry etched, and the etching endpoint is stopped at the front oxide layer.
[0093] S213: Remove the first mask layer.
[0094] S215: Using the etched silicon nitride layer as a hard mask, the pre-oxide layer and the P-type silicon substrate in the first shallow trench window area and the second shallow trench window area are etched sequentially, and the etching endpoint is stopped inside the P-type silicon substrate to form the first shallow trench and the second shallow trench.
[0095] S216: Clean the wafer surface and thermally oxidize the first shallow trench and the second shallow trench.
[0096] Specifically, the thermal oxidation of the first shallow trench and the second shallow trench involves generating an oxide film on the sidewalls of the first shallow trench and the second shallow trench respectively through thermal oxidation in a furnace tube.
[0097] S217: Deposit a silicon dioxide layer to fill the first shallow trench and the second shallow trench and cover the silicon nitride layer. The process for depositing the silicon dioxide layer is high-density plasma chemical vapor deposition (HDP CVD).
[0098] S218: Using a patterned second mask layer as a mask, etch the silicon dioxide layer on the silicon nitride layer to ensure that no silicon dioxide layer remains on the silicon nitride layer.
[0099] S219: Perform chemical mechanical polishing on the silicon dioxide layer, with the polishing endpoint resting on the silicon nitride layer to form the first shallow trench isolation region 200 and the second shallow trench isolation region 207.
[0100] S220: Cleaning the wafer surface using an acid bath.
[0101] S221: After cleaning the wafer, the silicon nitride layer is wet-etched using an etching solution with a high etch selectivity to silicon nitride to remove the silicon nitride layer. The etching solution may be phosphoric acid at 180°C and a concentration of 91.5%.
[0102] S225: The pre-oxide layer is removed by wet etching, with the etching endpoint remaining on the surface of the P-type silicon substrate. A sacrificial oxide layer is then regrown on the exposed surface of the P-type silicon substrate.
[0103] S226: Using patterned third and fourth mask layers as masks, NW ion implantation and PW ion implantation are performed on the P-type silicon substrate under the sacrificial oxide layer to form NW well regions and PW well regions, respectively.
[0104] S227: Perform rapid thermal annealing on the sacrificial oxide layer.
[0105] S228: The sacrificial oxide layer is removed by wet etching to form the test active region 201.
[0106] The above is the specific preparation process for step S2. The remaining steps for preparing the defect test structure of the gate oxide layer are explained below:
[0107] S3: A first metal gate structure is formed at the boundary between the first shallow trench isolation region and the test active region, a second metal gate structure is formed in the test active region, and the third metal gate structure is formed in the second shallow trench isolation region and the test active region.
[0108] Specifically, step S3 includes:
[0109] S311: A gate oxide layer 208 is formed on the test active region 201 by thermal oxidation using a furnace tube, such as... Figure 10 As shown.
[0110] S312: Deposit a polysilicon layer on the wafer, wherein the polysilicon layer covers the gate oxide layer, the first shallow trench isolation region, and the second shallow trench isolation region.
[0111] S313: A patterned fourth mask layer is formed on the surface of the polysilicon layer. The fourth mask layer includes a first gate blocking pattern, a second gate blocking pattern, and a third gate blocking pattern. The first gate blocking pattern corresponds to the region where the first metal gate structure is located, the second gate blocking pattern corresponds to the region where the second metal gate structure is located, and the third gate blocking pattern corresponds to the region where the third metal gate structure is located.
[0112] S314: Using the patterned fourth mask layer as a mask, the polysilicon layer is etched to form the first polysilicon gate 209, the second polysilicon gate 210, and the third polysilicon gate 211, as shown. Figure 11 As shown.
[0113] S315: A first sidewall 212 and a second sidewall 213 are sequentially formed on the sidewalls of the first polysilicon gate 209, the second polysilicon gate 210, and the third polysilicon gate 211, as follows: Figure 12 As shown.
[0114] Specifically, step S315 includes the following steps:
[0115] S3151: A first silicon dioxide layer and a first silicon nitride layer are sequentially deposited on the surface of the wafer.
[0116] S3152: Using the patterned fifth mask layer as a mask, the first silicon nitride layer and the first silicon dioxide layer are sequentially dry etched to form first sidewalls on the sidewalls of the first polysilicon gate, the second polysilicon gate, and the third polysilicon gate, respectively; the first sidewall includes a first silicon dioxide layer and a first silicon nitride layer, the first silicon dioxide layer is attached to the sidewall of the corresponding polysilicon gate, and the first silicon nitride layer is attached to the corresponding first silicon dioxide layer.
[0117] S3153: A second silicon dioxide layer and a second silicon nitride layer are sequentially deposited on the surface of the wafer.
[0118] S3154: Using the patterned sixth mask layer as a mask, the second silicon nitride layer and the second silicon dioxide layer are sequentially dry etched to form second sidewalls on the first sidewalls of the first polysilicon gate, the second polysilicon gate, and the third polysilicon gate, respectively; the second sidewall includes a second silicon dioxide layer and a second silicon nitride layer, the second silicon dioxide layer is attached to the corresponding first silicon nitride layer, and the second silicon nitride layer is attached to the corresponding second silicon dioxide layer.
[0119] After completing step S315, the subsequent steps also include:
[0120] S316: A silicide barrier layer, an etch stop layer, and a second silicon oxide layer are sequentially formed on the surface of the test active region, the surface of the first shallow trench isolation region, the surface of the second shallow trench isolation region, the surface of the first polysilicon gate, the surface of the second polysilicon gate, and the surface of the third polysilicon gate.
[0121] The silicide barrier layer comprises a third silicon dioxide layer and a third silicon nitride layer stacked sequentially. The third silicon dioxide layer covers the test active region surface, the first shallow trench isolation region surface, and the second shallow trench isolation region surface between each first metal gate structure, each second metal gate structure, and each third metal gate structure. The third silicon dioxide layer is also bonded to the second sidewall of each of the first metal gate structure, each second metal gate structure, and each third metal gate structure. The third silicon nitride layer covers the surface of the third silicon dioxide layer. The third silicon dioxide layer and the third silicon nitride layer are used to prevent the formation of metal silicides on the test active region surface, the first polysilicon gate surface, the second polysilicon gate surface, and the third polysilicon gate surface. The thickness of the third silicon nitride layer and the etch stop layer are different.
[0122] S317: The second silicon oxide layer 216, the etch stop layer 215, and the silicide barrier layer 214 are sequentially polished until the first polysilicon gate 209, the second polysilicon gate 210, and the third polysilicon gate 211 are exposed. Figure 13 As shown.
[0123] S318: Using the patterned seventh mask layer as a mask, the first polysilicon gate 209, the second polysilicon gate 210, and the third polysilicon gate 211 are etched to form a first etch trench, a second etch trench, and a third etch trench. The etching endpoints all stop at the corresponding gate oxide layer 208. Figure 14 As shown.
[0124] S322: Deposit gate metal to fill the first etched trench, the second etched trench and the third etched trench, and cover the surface of the second silicon oxide layer.
[0125] S323: The gate metal is ground down to the surface of the second silicon oxide layer 216 to form the first metal gate, the second metal gate, and the third metal gate, as shown below. Figure 13 As shown, Figure 15 As shown.
[0126] After the fabrication of the aforementioned test structures is completed, the first metal gate structure, the second metal gate structure, and the third metal gate structure are scanned using an electron beam gun to detect whether there are defects in the gate oxide layer in contact with the first shallow trench isolation region, whether there are defects in the gate oxide layer located in the test active region, and whether there are defects in the gate oxide layer in contact with the second shallow trench isolation region. Furthermore, based on the presence or absence of defects in the gate oxide layers in different regions, it is determined whether there are defects in the gate oxide layer at the boundary with the shallow trench isolation structure in the device region, and whether there are defects in the gate oxide layer located in the active region. The method of using an electron beam gun to determine whether there are defects in the corresponding gate oxide layer has been explained above and will not be repeated here.
[0127] Since steps 2, S311, S312, S317 to S323 can all share the same process as the fabrication of semiconductor devices, the process cost of fabricating test structures is saved.
[0128] In summary, the gate oxide defect testing structure provided by this embodiment includes a first shallow trench isolation region and a test active region, wherein the first shallow trench isolation region surrounds the test active region. By setting at least one first metal gate structure and at least one second metal gate structure in the boundary region between the first shallow trench isolation region and the test active region, and within the test active region, the defect status of the gate oxide layer in the test structure can be determined by scanning the metal gate structure with an electron beam gun. Furthermore, because the test structure is fabricated simultaneously with the actual semiconductor device, the defect status of the gate layer in the test structure can reflect the defect status of the gate layer in the actual device. Moreover, this test structure enables online detection, avoiding wafer waste caused by performing defect detection only after device fabrication is completed.
[0129] Furthermore, the defect testing structure also includes: a second shallow trench isolation region and at least one third metal gate structure; the second shallow trench isolation region is surrounded by the test active region and forms a boundary region with the test active region, and at least one third metal gate structure is disposed in the boundary region between the second shallow trench isolation region and the test active region. Because the areas of the first shallow trench isolation region and the second shallow trench isolation region are different, the stress applied to the gate oxide layer in the boundary region between the first shallow trench isolation region and the test active region is different from the stress applied to the gate oxide layer in the boundary region between the second shallow trench isolation region and the test active region. Therefore, the influence of different stresses applied to the gate oxide layer in different boundary regions on the quality of the gate oxide layer can be compared.
[0130] Furthermore, by providing the first metal gate structure on all four sides of the boundary region between the first shallow trench isolation region and the test active region, and by providing the third metal gate structure on all four sides of the second shallow trench isolation region and the test active region, in order to avoid the situation where the first metal gate structure and the third metal gate structure in the first or second direction cannot simultaneously contact the test active region and the corresponding shallow trench isolation region due to overlay error, the gate oxide defect detection can be completed through the first metal gate structure and the third metal gate structure in the other direction.
[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. A defect testing structure for a gate oxide layer, characterized in that, The defect testing structure is disposed within the dicing channel of the wafer, and the defect testing structure includes: A first shallow trench isolation area and a test active area are both located within the cutting channel. The first shallow trench isolation area and the test active area have a preset step height, and the first shallow trench isolation area surrounds the test active area. The gate oxide layer is located on the surface of the test active region; At least one first metal gate structure is disposed in the boundary region between the first shallow trench isolation region and the test active region, and each first metal gate structure includes a first metal gate. At least one second metal gate structure is disposed on the surface of the gate oxide layer within the test active region, and each second metal gate structure includes a second metal gate.
2. The defect testing structure for the gate oxide layer according to claim 1, characterized in that, The structure also includes: The second shallow trench isolation area is located inside the test active area and is surrounded by the test active area; At least one third metal gate structure is disposed in the boundary region between the second shallow trench isolation region and the test active region, and each of the third metal gate structures includes a third metal gate. The areas of the first shallow trench isolation zone and the second shallow trench isolation zone are different.
3. The defect testing structure for the gate oxide layer according to claim 2, characterized in that, The number of the first metal gate structures includes at least four, and the at least four first metal gate structures are respectively disposed on the four sides of the boundary region between the first shallow trench isolation region and the test active region; The first metal gate structures disposed on the first and third sides are arranged at intervals along the first direction, and the first metal gate structures disposed on the second and fourth sides are arranged at intervals along the second direction, wherein the first direction and the second direction are perpendicular to each other.
4. The defect testing structure for the gate oxide layer according to claim 3, characterized in that, The number of the second metal gate structures includes at least four, and the at least four second metal gate structures are respectively disposed on the four sides of the test active region; The second metal gate structures disposed on the first side and the third side are arranged at intervals along the first direction, and the second metal gate structures disposed on the second side and the fourth side are arranged at intervals along the second direction.
5. The defect testing structure for the gate oxide layer according to claim 4, characterized in that, The number of the third metal gate structures includes at least four, and the at least four third metal gate structures are respectively disposed on the four sides of the boundary region between the second shallow trench isolation region and the test active region. The third metal gate structures disposed on the first and third sides are arranged at intervals along the first direction, and the third metal gate structures disposed on the second and fourth sides are arranged at intervals along the second direction.
6. The defect testing structure for the gate oxide layer according to claim 5, characterized in that, The spacing between each metal gate structure is greater than or equal to the first threshold.
7. The defect testing structure for the gate oxide layer according to any one of claims 2 to 6, characterized in that, Each of the first metal gate structure, each of the second metal gate structure and each of the third metal gate structure further includes a first sidewall, which is attached to the sidewall of the corresponding metal gate and is located on the corresponding gate oxide layer.
8. The defect testing structure for the gate oxide layer according to claim 7, characterized in that, Each of the first metal gate structure, each of the second metal gate structure and each of the third metal gate structure further includes a second sidewall, which is attached to the corresponding first sidewall and located on the corresponding gate oxide layer.
9. The defect testing structure for the gate oxide layer according to claim 8, characterized in that, The defect testing structure also includes: a silicide barrier layer, an etch stop layer, and a second silicon oxide layer; The silicide barrier layer covers the test active region surface, the first shallow trench isolation region surface, and the second shallow trench isolation region surface between each of the first metal gate structure, each of the second metal gate structure, and each of the third metal gate structure. The silicide barrier layer is also attached to the second sidewall of each of the first metal gate structure, each of the second metal gate structure, and each of the third metal gate structure. The etching stop layer covers the surface of the silicide barrier layer; The second silicon oxide layer covers the surface of the etch stop layer; Each of the metal gates is exposed.
10. The defect testing structure for the gate oxide layer according to claim 9, characterized in that, The silicide barrier layer comprises a third silicon dioxide layer and a third silicon nitride layer stacked sequentially. The third silicon dioxide layer covers the test active region surface, the first shallow trench isolation region surface, and the second shallow trench isolation region surface between each first metal gate structure, each second metal gate structure, and each third metal gate structure. The third silicon dioxide layer is also attached to the second sidewall of each first metal gate structure, each second metal gate structure, and each third metal gate structure. The third silicon nitride layer covers the surface of the third silicon dioxide layer.