Audio signal acquisition device and system

Abstract

The utility model discloses an audio signal acquisition device and system. The device comprises a plurality of latches which are triggered according to a unified clock signal; the plurality of judgment units are electrically connected with the plurality of latches and are used for acquiring initial output signals of the plurality of latches and determining final output signals according to the initial output signals under the condition that the plurality of latches are triggered; and the multiplexing device is electrically connected with the plurality of latches and is used for receiving the final output signals output by the plurality of latches, and the multiplexing device comprises a plurality of paths of audio signal input pins and is used for periodically switching the audio signal input pins according to the final output signals. The multi-channel audio signal acquisition device can solve the problem that a multi-channel audio signal acquisition device in the prior art is easy to generate high-frequency interference.

Description

Technical Field

[0001] This application relates to the field of circuit device technology, and more specifically to an audio signal acquisition device and system. Background Technology

[0002] Existing multi-channel microphone acquisition devices employ a separate filtering circuit for each acquisition channel, significantly increasing the overall hardware complexity, especially when dealing with a large number of channels, requiring a controller for unified management. However, the controller is prone to generating high-frequency noise interference during signal processing, negatively impacting surrounding circuits. This high-frequency interference not only affects signal acquisition accuracy but also degrades electromagnetic compatibility (EMC) performance. In complex electromagnetic environments, the stability and reliability of the circuitry are difficult to guarantee, greatly limiting the application of this multi-channel acquisition device in certain electromagnetically sensitive scenarios.

[0003] utility model

[0004] The purpose of this application is to provide an audio signal acquisition device and system to solve the problem that multi-channel audio signal acquisition devices in the prior art are prone to high-frequency interference.

[0005] To achieve the above objectives, the first aspect of this application provides an audio signal acquisition device, which includes:

[0006] Multiple latches, triggered by a unified clock signal;

[0007] Multiple judgment units are electrically connected to multiple latches, and are used to acquire the initial output signals of multiple latches and determine the final output signal based on the initial output signals when multiple latches are triggered.

[0008] A multiplexer is electrically connected to multiple latches to receive the final output signal from the multiple latches. The multiplexer includes multiple audio signal input pins for periodically switching the audio signal input pins according to the final output signal.

[0009] In the embodiments of this application, the plurality of latches include a first latch, a second latch, and a third latch. The first latch, the second latch, and the third latch all include a clock signal input pin, a data input pin, a positive data output pin, and an inverted data output pin opposite to the positive data output pin.

[0010] In this embodiment, the multiple determination units include: a first determination unit, including a first AND gate element, a second AND gate element, and a first XOR gate element; a second determination unit, including a third AND gate element, a fourth AND gate element, a fifth AND gate element, and a second XOR gate element; a third determination unit, including a sixth AND gate element, a seventh AND gate element, and a third XOR gate element; the first AND gate element is electrically connected to the positive data output pin of the third latch and the inverted data output pin of the first latch, and the second AND gate element is electrically connected to the positive data output pin of the second latch and the positive data output pin of the first latch; the first AND gate element and the second AND gate element are respectively electrically connected to the first XOR gate element, and the first XOR gate element is electrically connected to the data input pin of the third latch.

[0011] In this embodiment, the third AND gate element is electrically connected to the inverted data output pin of the first latch and the non-inverted data output pin of the second latch; the fourth AND gate element is electrically connected to the inverted data output pin of the second latch and the non-inverted data output pin of the first latch; the second XOR gate element is electrically connected to the third, fourth, and fifth AND gate elements; and the fifth AND gate element is electrically connected to the inverted data output pin of the third latch and the data input pin of the second latch.

[0012] In this embodiment, the sixth AND gate element is electrically connected to the positive data output pin of the third latch and the negative data output pin of the second latch; the seventh AND gate element is electrically connected to the negative data output pin and the data input pin of the first latch; and the third XOR gate element is electrically connected to the negative data output pin of the third latch and the seventh AND gate element.

[0013] In this embodiment, each of the multiple latches is provided with a reset data pin and a set data pin; the reset data pin is used to reset the positive data output pin and the inverted data output pin opposite to the positive data output pin of the corresponding latch.

[0014] In this embodiment, the set data pin is used to force the positive data output of the corresponding latch to a high level.

[0015] In this embodiment of the application, the device further includes a clock generation circuit and a waveform shaping circuit, wherein the clock generation circuit is used to generate a clock signal, and the waveform shaping circuit is used to shape the clock signal generated by the clock generation circuit.

[0016] In this embodiment of the application, the device further includes: an audio input circuit electrically connected to a multi-channel audio signal input pin, used to provide multiple audio signals.

[0017] A second aspect of this application provides an audio signal acquisition system, which includes the aforementioned audio signal acquisition device.

[0018] Through the above technical solution, multiple judgment units acquire the initial output signals of multiple latches when multiple latches are triggered by a unified clock signal, and perform logical operations based on the initial output signals to output the final output signals through the multiple latches themselves; after receiving the final output signals from multiple latches, the multiplexing device periodically switches the signals among the multiple audio signal input pins according to the final output signals, thereby achieving the effect of acquiring multiple audio signals.

[0019] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings:

[0021] Figure 1 The schematic diagram illustrates a circuit diagram of a plurality of latches and a plurality of decision units according to an embodiment of the present application;

[0022] Figure 2 A circuit diagram of a multiplexing device according to an embodiment of this application is shown schematically;

[0023] Figure 3 A signal level diagram according to an embodiment of this application is illustrated schematically;

[0024] Figure 4 A circuit diagram of a clock generator according to an embodiment of this application is shown schematically;

[0025] Figure 5 A circuit diagram of an indicator light according to an embodiment of this application is shown schematically;

[0026] Figure 6 The diagram schematically illustrates a circuit diagram of a microphone input according to an embodiment of this application;

[0027] Figure 7 A circuit diagram of a phantom power supply according to an embodiment of this application is shown schematically. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0030] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0031] In the embodiments of this application, the latch can be a 74HC74 model, the AND gate can be a 74HC08 model, and the XOR gate can be a 74HC32 model.

[0032] Figure 1 The schematic diagram illustrates a circuit diagram of a plurality of latches and a plurality of decision units according to an embodiment of the present application; Figure 2 A circuit diagram of a multiplexing device according to an embodiment of this application is shown schematically. Figure 1 and Figure 2 As shown in the figure, this application provides an audio signal acquisition device, which may include:

[0033] Multiple latches U7, U3, and U10 are triggered according to a unified clock signal;

[0034] Multiple judgment units are electrically connected to multiple latches, and are used to acquire the initial output signals of multiple latches and determine the final output signal based on the initial output signals when multiple latches are triggered.

[0035] A multiplexer is electrically connected to multiple latches to receive the final output signal from the multiple latches. The multiplexer includes multiple audio signal input pins for periodically switching the audio signal input pins according to the final output signal.

[0036] In this embodiment, the multiple latches may include a first latch U7, a second latch U3, and a third latch U10. Each of the first latch U7, second latch U3, and third latch U10 includes a clock signal input pin CLK, a data input pin D, a positive data output pin Q, and an inverted data output pin opposite to the positive data output pin Q.

[0037] Through the above technical solution, when the clock signal input pins CLK of multiple latches are triggered by a unified clock signal, multiple judgment units can obtain the positive data output pins Q and negative data output pins of multiple latches. The initial output signal is obtained, and logical operations are performed based on the initial output signal. The final output signal is transmitted to multiple latches through the data input pins D of multiple latches. After the multiplexer receives the final output signal output from the positive data output pins Q of multiple latches through S0, S1 and S2, it periodically switches the signal between the multiple audio signal input pins (Y0~Y5) according to the final output signal, thereby achieving the effect of multiple audio signal acquisition.

[0038] In the embodiments of this application, such as Figure 2As shown, U23 is a multiplexer of model 74HC4051, which supports up to 8 channels. The U23 multiplexer is used to output one of the input signals from Y0 to Y5 at a given moment to the Z terminal, controlled by selection signals S0, S1, and S2. Y0 to Y7 are channels for 8 microphone input signals; in this embodiment, only Y0 to Y5 (6 channels) are connected, receiving six microphone input signals. Each channel can be considered an independent microphone signal source. S0, S1, and S2: By controlling the states of these three signals, the output terminal selects which signal from Y0 to Y5 to be transmitted to the Z output terminal. Based on the periodic changes of the Q0 to Q2 signal bus, the U23 multiplexer cyclically selects different input channels, causing the output signal to exhibit periodic switching. Driven by the control signals, the Z terminal outputs the signal of one of the currently selected Y0 to Y5 channels. R42 (2KΩ) and R43 (22KΩ) are used for signal matching and current limiting. R42 (2KΩ) and R43 (22KΩ) stabilize the signal level and limit current, preventing voltage surges from impacting subsequent operational amplifiers. They can also be used to adjust the signal amplitude, ensuring signal integrity during transmission. U9 is a TS912 operational amplifier, configured as a voltage follower in this embodiment to provide high input impedance and low output impedance for signal buffering and driving. The U9 operational amplifier output closely follows changes in the input voltage but has stronger driving capability. The U9 operational amplifier takes the output (i.e., Z-terminal) of the U23 multiplexer as its input to receive the selected microphone signal. The U9 operational amplifier outputs a buffered signal OUT, providing a stable, low-impedance signal that can be transmitted to subsequent circuits. V5 provides power (typically 5V) to the U23 multiplexer, ensuring its proper operation. V18 provides the operating voltage (typically 5V) to the U9 operational amplifier, ensuring the circuit operates normally at the appropriate voltage. Using the above technical solution, the Q0-Q2 signals periodically drive the selection pins S0-S2 of the U23 multiplexer, causing the six microphone signals Y0-Y5 to be output sequentially to the Z terminal. Then, the Z-terminal output signal, after being adjusted by the resistor network R42 and R43, enters the input terminal of the U9 operational amplifier. The U9 operational amplifier, acting as a voltage follower, enhances the signal driving capability and outputs the signal as OUT. Finally, the OUT signal becomes a stable microphone acquisition output signal, which can be supplied to subsequent circuits for processing.

[0039] Those skilled in the art will understand that even if the application scenario involves more than 8 channels, it can still be implemented using the technical solution claimed in this application. Specifically, the maximum supported number of channels is a power of 2, where the power represents the number of judgment units. For example, the embodiments of this application provide 3 judgment units, i.e., 2 to the power of 3, supporting a maximum of 8 channel inputs. To support signal inputs exceeding 8 channels, this can be achieved by adding the required number of judgment units and the corresponding number of latches.

[0040] In this embodiment, the multiple judgment units may include: a first judgment unit, including a first logic AND gate element U11, a second logic AND gate element U12, and a first logic XOR gate element U14; a second judgment unit, including a third logic AND gate element U13, a fourth logic AND gate element U15, a fifth logic AND gate element U16, and a second logic XOR gate element U17; a third judgment unit, including a sixth logic AND gate element U20, a seventh logic AND gate element U18, and a third logic XOR gate element U19; the first logic AND gate element U11 is electrically connected to the positive data output pin Q2 of the third latch and the inverted data output pin Q0_N of the first latch, the second logic AND gate element U12 is electrically connected to the positive data output pin Q1 of the second latch and the positive data output pin Q0 of the first latch; the first logic AND gate element U11 and the second logic AND gate element U12 are respectively electrically connected to the first logic XOR gate element U14, and the first logic XOR gate element U14 is electrically connected to the data input pin D2 of the third latch.

[0041] In this embodiment, the third AND gate element U13 is electrically connected to the inverted data output pin Q0_N of the first latch and the non-inverted data output pin Q1 of the second latch; the fourth AND gate element U15 is electrically connected to the inverted data output pin Q1_N of the second latch and the non-inverted data output pin Q0 of the first latch; the second XOR gate element U17 is electrically connected to the third AND gate element U13, the fourth AND gate element U15 and the fifth AND gate element U16; the fifth AND gate element U16 is electrically connected to the inverted data output pin Q2_N of the third latch and the data input pin D1 of the second latch.

[0042] In this embodiment, the sixth AND gate element U20 is electrically connected to the positive data output pin Q2 of the third latch and the inverted data output pin Q1_N of the second latch; the seventh AND gate element U18 is electrically connected to the inverted data output pin Q0_N and the data input pin D0 of the first latch; and the third XOR gate element U19 is electrically connected to the inverted data output pin Q2_N of the third latch and the seventh AND gate element U18.

[0043] Figure 3 A signal level diagram according to an embodiment of this application is illustrated schematically, such as... Figure 3 As shown in this embodiment, the horizontal axis represents time, and the vertical axis represents voltage. A voltage of 0 indicates a low level, and a non-zero voltage indicates a high level. Before 150ms, the latches are not initialized, so the output level signals are irregular. Starting from 150ms, multiple latches are initialized by the signal received through the reset data pin CLR. Multiple latches then begin to receive a unified clock signal through their respective clock signal input pin CLK and perform corresponding operations. Each time the first latch U7, the second latch U3, and the third latch U10 receive a clock signal through their respective clock signal input pin CLK, i.e. Figure 3 On the rising edge of V(clk), the binary encoded bus [Q0, Q1, and Q2] will switch to a new state. The switching process is as follows: Figure 3 The diagram shows the sequence [0,0,0]->[1,0,0]->[0,1,0]->[1,1,0]->[0,0,1]->[1,0,1]->[0,0,0]. This means the output levels of the signal buses [Q0, Q1, and Q2] are respectively... Figure 3 The level signals of V(d0), V(d1), and V(d2).

[0044] In this embodiment, each of the plurality of latches is provided with a reset data pin CLR and a set data pin PRE; the reset data pin CLR is used to reset the corresponding latch's positive data output pin Q and the inverted data output pin opposite to the positive data output pin.

[0045] In this embodiment, when the reset data pin CLR is triggered, the corresponding inverted data output pin Q of the latch outputs a low-level signal (0), and the inverted data output pin opposite to the inverted data output pin... Output a high-level signal (1). When the reset data pin CLR is not triggered, the above three latches normally receive a unified clock signal through the clock signal input pin CLK and perform corresponding operations according to the clock signal.

[0046] In this embodiment, the set data pin can be used to force the positive data output of the corresponding latch to a high level.

[0047] In this embodiment, when the set data pin PRE is triggered, the corresponding positive data output pin Q of the latch outputs a low-level signal (0), and the inverted data output pin opposite to the positive data output pin... Output a high-level signal (1).

[0048] In this embodiment of the application, the device may further include: a clock generation circuit and a waveform shaping circuit, wherein the clock generation circuit is used to generate a clock signal, and the waveform shaping circuit is used to shape the clock signal generated by the clock generation circuit.

[0049] Figure 4 A circuit diagram of a clock generator according to an embodiment of this application is schematically shown, such as... Figure 4 As shown in this embodiment, U22 is an LT1001 operational amplifier used to filter and integrate the input signal to generate a smooth voltage signal. The input of the U22 operational amplifier consists of a feedback network composed of resistors R2 (47KΩ), R3 (47KΩ), and capacitor C2 (2.2μF), which obtains the signal from the input voltage (node ​​A). A potentiometer R4 (47KΩ) is connected in the feedback network of the U22 operational amplifier, which can adjust the time constant of the integrating circuit, thereby controlling the frequency and waveform of the integrated output. Figure 4The resistance values ​​and corresponding times indicated in the diagram can adjust the period of the output signal. R5 (22KΩ) is used to limit the current flowing from the op-amp output to the subsequent circuit, protecting the input of the subsequent transistor from excessive voltage. C2 (2.2μF) is the integrating capacitor, which, together with the U22 operational amplifier, forms the integrating circuit, determining the smoothness and frequency of the output signal. The value of C2 (2.2μF) and the resistance value of R4 (47KΩ) together affect the frequency of the output signal. Q11 is a BC847C transistor, an amplifier circuit used for signal shaping. It further amplifies and converts the output voltage from the op-amp integrating circuit, making it closer to a square wave or triangular wave, providing a stable transition signal to the next stage transistor Q12. The input capacitor C3 (2.2nF) of the Q11 transistor is used to filter out high-frequency noise and prevent unstable signals from affecting the normal operation of the Q11 transistor. R6 (1MΩ) is a bias resistor, used to provide bias current to the Q11 transistor, ensuring that the BC847C transistor operates in the amplification region, facilitating signal amplification and shaping. R7 (47KΩ) and R9 (10KΩ) are used. R7 is the collector load resistor for transistor Q11, providing the output current path. R9 (10KΩ) is the bias resistor between the bases of transistors Q11 and Q12, ensuring bias matching between the two transistors and improving signal transmission stability. Transistor Q12, a BC847C model, is used for final signal shaping, converting the amplified signal into a stable clock pulse output (CLK_OUT). When transistor Q12 is on, the output is low; when transistor Q12 is off, the output is high, thus forming a square wave signal. R8 (47KΩ) is the collector load resistor for transistor Q12, providing a stable current path and ensuring the level conversion effect of the collector output of transistor Q12. R10 (10KΩ) is the base bias resistor for transistor Q12, used to stabilize the base voltage and ensure that transistor Q12 can turn on and off at appropriate times. V1 and V2 are voltage sources. V1 is 2.5V, providing bias voltage to the integrating circuit of the U22 operational amplifier to ensure stable output signal. V2 is 5V, providing power to the transistor-level circuit to ensure normal operation. CLK_OUT is the output terminal of this circuit, generating a shaped square wave signal, which is output as a clock signal to external circuits (such as the CLK pin of a latch).

[0050] Figure 5 A circuit diagram of an indicator light according to an embodiment of this application is shown schematically, such as... Figure 5As shown, in one embodiment, the above solution may further include a circuit diagram of an indicator light for driving the LEDs of the corresponding channel to display the real-time acquired corresponding channel. U30 is a 74HC138 decoder. The U30 decoder receives three binary input signals A0, A1, and A2 and converts them into one of a low-level output (Y0~Y7). A0, A1, and A2 serve as selection pins, receiving control signals from the signal bus [Q0, Q1, Q2], activating different output pins according to different combinations of binary signals. E1, E2, and E3 serve as enable pins; applying a high or low level to these pins enables the decoder to operate, ensuring the output is valid. Y0~Y7 are the output pins of the U30 decoder, each output corresponding to a selection combination. For example, when A0, A1, and A2 are [0,0,0], Y0 output is valid; when they are [0,0,1], Y1 output is valid, and so on. Figure 5 In the circuit shown, Y0 to Y5 correspond to six LED control channels. R46 to R51 (1KΩ) are used as current-limiting resistors to prevent excessive current from flowing through the LEDs and protect them from burning out. U31 to U36 (LEDs) are light-emitting diodes used to display the corresponding output signal status.

[0051] In this embodiment of the application, the device may further include: an audio input circuit electrically connected to a multi-channel audio signal input pin for providing multiple audio signals.

[0052] Figure 6 This schematically illustrates a circuit diagram of a microphone input according to an embodiment of the present application, such as... Figure 6As shown in this embodiment, M2 represents the input audio signal source. The output of this signal source includes the audio signal as well as some possible DC bias and high-frequency noise. Capacitor C26 (10μF) is used to isolate the DC component, allowing only the AC audio signal to pass through, thereby removing the DC bias in the input signal. R532 (50KΩ) reintroduces the audio signal to a DC bias level to match the input level of the subsequent operational amplifier, making it operate in the linear range and avoiding amplifier distortion. R53 (2.1KΩ) and R54 (3.32KΩ) are impedance matching resistors, and R53 (2.1KΩ) and R54 (3.32KΩ) form part of the filter, helping to control the cutoff frequency and attenuation characteristics of the filter. C24 (1nF) and C25 (1.4nF) are filter capacitors, and C24 (1nF), C25 (1.4nF), R53 (2.1KΩ), and R54 (3.32KΩ) form a second-order Butterworth low-pass filter. The combination of C24 (1nF) and C25 (1.4nF) determines the cutoff frequency of the filter. The Butterworth filter has a flat passband response, thus effectively preserving the characteristics of the original signal within the audio range. U2 is a TS92X operational amplifier, serving as the core component of the active filter. U2 provides gain amplification, and together with external resistors and capacitors, forms a second-order Butterworth low-pass filter. By amplifying and smoothing the signal, it helps remove high-frequency components above 20kHz, ensuring that only signals within the audio frequency range are retained. R55 (5KΩ) is used to control the output signal current, preventing excessive current from damaging subsequent circuitry and also helping to protect the U2 operational amplifier.

[0053] Figure 7 A circuit diagram of a phantom power supply according to an embodiment of this application is illustrated schematically, such as... Figure 7As shown, in one embodiment, V10 provides a 48V DC bias voltage, which is the power supply for the microphone bias circuit, providing a stable power supply voltage to the microphone. R56 (60Ω) is a current-limiting resistor, used to limit the maximum output current and prevent excessive current from damaging the microphone. When the current flowing through R56 (60Ω) causes the voltage drop across it to exceed 0.6V, R56 (60Ω) will cause transistors Q13 and Q14 to form a constant current source. Q13 and Q14 are 2SAR514P5 transistors. The combination of Q13 and Q14 transistors forms a current source used to control the switching between current mode and voltage mode. When the voltage drop across R56 (60Ω) exceeds 0.6V, transistors Q13 and Q14 will generate a constant output current, keeping the phantom power supply output current stable and entering constant current mode, thus preventing interference from current fluctuations. When the voltage drop across R56 (60Ω) falls below 0.6V, transistor Q14 turns on, and the circuit output enters constant voltage mode, providing a stable voltage for the microphone. R57 (100KΩ) is a bias resistor, used to ensure that the base current of transistor Q13 is appropriate, thus ensuring that transistor Q13 is stably turned on or off under suitable operating conditions. C31 (22μF) is a filter capacitor, used to filter out AC interference components in the power supply, ensuring the purity of the phantom power signal (48V_Phantom_Power), reducing noise introduction, and improving the microphone signal quality and the overall circuit's anti-interference capability.

[0054] This application also provides an audio signal acquisition system, which may include the audio signal acquisition device described above.

[0055] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0056] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An audio signal acquisition device, characterized in that, include: Multiple latches, which are triggered according to a unified clock signal; Multiple judgment units, electrically connected to the multiple latches, are used to acquire the initial output signals of the multiple latches and determine the final output signal based on the initial output signals when the multiple latches are triggered; A multiplexing device, electrically connected to the plurality of latches, is used to receive the final output signal output by the plurality of latches. The multiplexing device includes multiple audio signal input pins for periodically switching the audio signal input pins according to the final output signal.

2. The apparatus according to claim 1, characterized in that, The plurality of latches include a first latch, a second latch, and a third latch. Each of the first latch, the second latch, and the third latch includes a clock signal input pin, a data input pin, a positive data output pin, and an inverted data output pin opposite to the positive data output pin.

3. The apparatus according to claim 1, characterized in that, The plurality of determination units include: The first decision unit includes a first logical AND gate element, a second logical AND gate element, and a first logical XOR gate element; The second decision unit includes a third logical AND gate element, a fourth logical AND gate element, a fifth logical AND gate element, and a second logical XOR gate element; The third decision unit includes the sixth logical AND gate element, the seventh logical AND gate element, and the third logical XOR gate element; The first AND gate element is electrically connected to the positive data output pin of the third latch and the inverted data output pin of the first latch; the second AND gate element is electrically connected to the positive data output pin of the second latch and the positive data output pin of the first latch; the first AND gate element and the second AND gate element are respectively electrically connected to the first XOR gate element; the first XOR gate element is electrically connected to the data input pin of the third latch.

4. The apparatus according to claim 3, characterized in that, The third AND gate is electrically connected to the inverted data output pin of the first latch and the non-inverted data output pin of the second latch; the fourth AND gate is electrically connected to the inverted data output pin of the second latch and the non-inverted data output pin of the first latch; the second XOR gate is electrically connected to the third AND gate, the fourth AND gate, and the fifth AND gate; the fifth AND gate is electrically connected to the inverted data output pin of the third latch and the data input pin of the second latch.

5. The apparatus according to claim 3, characterized in that, The sixth AND gate element is electrically connected to the positive data output pin of the third latch and the negative data output pin of the second latch; the seventh AND gate element is electrically connected to the negative data output pin and the data input pin of the first latch; the third XOR gate element is electrically connected to the negative data output pin of the third latch and the seventh AND gate element.

6. The apparatus according to claim 1, characterized in that, Each of the plurality of latches is provided with a reset data pin and a set data pin; the reset data pin is used to reset the positive data output pin corresponding to the latch and the inverted data output pin opposite to the positive data output pin.

7. The apparatus according to claim 6, characterized in that, The set data pin is used to force the positive data output of the corresponding latch to be high.

8. The apparatus according to claim 1, characterized in that, The device further includes: A clock generator includes a clock generation circuit and a waveform shaping circuit. The clock generation circuit generates a clock signal, and the waveform shaping circuit shapes the clock signal generated by the clock generation circuit.

9. The apparatus according to claim 1, characterized in that, The device further includes: An audio input circuit, electrically connected to the multi-channel audio signal input pin, is used to provide multiple audio signals.

10. An audio signal acquisition system, characterized in that, Includes the audio signal acquisition device according to any one of claims 1 to 9.

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