Power device
By setting a first contact hole in the power device that communicates with the floating P-region, the problem of uncontrolled gate caused by the floating P-region is solved, achieving low on-state voltage drop and high energy utilization, and reducing switching losses and current overshoot risk.
Patent Information
- Application Number
- CN202422885050.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-11-25
AI Technical Summary
In power devices, a floating P-type region causes the gate to be uncontrolled by the applied voltage, resulting in a large displacement current, poor EMI and turn-on losses, and is prone to current overshoot and increased turn-on losses.
In power devices, by setting multiple first contact holes at intervals along a first direction to communicate with the floating P region, the holes accumulated in the floating P region are diverted away, the displacement current is reduced, and the carrier injection effect is retained in the area where no contact holes are set, thereby enhancing the gate's control over EMI and turn-on losses.
It reduces the on-state voltage drop, decreases switching and conduction losses, improves energy efficiency, avoids current overshoot and device damage, and enhances the controllability of current change rate.
Smart Images
Figure CN223503280U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a power device. Background Technology
[0002] In power device design, a floating p-base region can be configured to reduce the on-state voltage drop, saturation current, and short-circuit withstand capability. However, the p-base region collects a large number of holes, causing its potential to rise. This results in a significant displacement current between the floating p-base region and the gate, making the gate uncontrollable by the applied voltage and deteriorating the relationship between EMI and turn-on losses. Utility Model Content
[0003] This application aims to address at least one of the technical problems existing in the prior art. Therefore, this application provides a power device.
[0004] The power device according to the embodiments of this application includes:
[0005] The silicon layer includes a floating P-region and a plurality of first trenches and second trenches extending along a first direction. Along the second direction, the first trenches and the second trenches are distributed in parallel with intervals. The floating P-region is located between the first trenches or between the first trenches and the second trenches.
[0006] An insulating dielectric layer is stacked on the silicon layer. The insulating dielectric layer is etched to form a plurality of first contact holes that communicate with the floating P region. The plurality of first contact holes are spaced apart along a first direction.
[0007] An emitter metal layer is stacked on the insulating dielectric layer, and the emitter metal layer is connected to the silicon layer at least partially through the first contact hole.
[0008] In some embodiments, along the first direction, the ratio of the length of the first contact hole to the distance between two adjacent first contact holes ranges from 1 / 20 to 1 / 4.
[0009] In some embodiments, the over-etched area of the first contact hole ranges from 0.1 micrometers to 1 micrometer along a third direction.
[0010] In some embodiments, the silicon layer further includes a P-body region located between the second trenches, the insulating dielectric layer is etched to form a plurality of second contact holes extending along a first direction, the second contact holes communicating with the P-body region, and the emitter metal layer at least partially passing through the second contact holes and connecting to the silicon layer.
[0011] In some embodiments, along a first direction, the length of the second contact hole is greater than the length of the first contact hole, and along a third direction, the depth of the first contact hole is equal to the depth of the second contact hole.
[0012] In some embodiments, the power device further includes:
[0013] The dummy gate is located within the first trench;
[0014] The main gate is located within the second trench.
[0015] In some embodiments, the silicon layer further includes:
[0016] The N+ emitter region is located in the P-body region.
[0017] In some embodiments, the silicon layer further includes:
[0018] The drift region has its upper surface etched downwards to form the first trench and the second trench.
[0019] In some embodiments, the silicon layer further includes a buffer region and a collector region, the buffer region being located between the drift region and the collector region;
[0020] The power device further includes a collector metal layer located on the side of the collector region away from the buffer zone.
[0021] In some implementations, it is an insulated gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.
[0022] In the power device of this application embodiment, by providing multiple first contact holes at intervals along a first direction that communicate with the floating P region, the first contact holes can conduct away the holes accumulated in the floating P region, reduce the displacement current, enhance the control of the gate on EMI and turn-on losses, and avoid the problem of current overshoot and increased turn-on losses caused by excessive current change rate due to rapid charging of the gate capacitor, or even damage to the power device. At the same time, in the area where the first contact holes are not provided, the floating P region can retain the effect of carrier injection, resulting in a lower on-state voltage drop. Thus, switching losses and conduction losses can be reduced, thereby improving energy utilization.
[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:
[0025] Figure 1 This is a top view schematic diagram of the power device according to an embodiment of this application.
[0026] Figure 2 yes Figure 1 A cross-sectional schematic diagram of AA.
[0027] Figure 3 yes Figure 1 A cross-sectional view of BB.
[0028] Figure 4 Another top view schematic diagram of the power device according to the embodiments of this application.
[0029] Figure 5 A schematic diagram comparing the on-state voltage of the power device in this application embodiment with that of other power devices.
[0030] Figure 6 A schematic diagram comparing the current change rate of the power device in this application embodiment with that of other power devices.
[0031] Explanation of key component symbols:
[0032] 10-Power device, 11-Silicon layer, 111-First trench, 112-Second trench, 113-Drift region, 114-Floating P-region, 115-P-body region, 116-N+ emitter region, 117-Buffer zone, 118-Collector region, 12-Insulating dielectric layer, 121-First contact hole, 122-Second contact hole, 13-Main gate, 14-Dummy gate, 15-Emitter metal layer, 16-Collector metal layer, X-First direction, Y-Second direction, Z-Third direction. Detailed Implementation
[0033] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0034] Please see Figure 1-4This application provides a power device 10, which includes a silicon layer 11, an insulating dielectric layer 12, and an emitter metal layer 15. The silicon layer 11 includes a floating P-region 114, a first trench 111, and a second trench 112. Both the first trench 111 and the second trench 112 extend along a first direction. Along a second direction Y, the first trench 111 and the second trench 112 are spaced parallel to each other. The floating P-region 114 is located between the first trenches 111 or between the first trench 111 and the second trench 112. The insulating dielectric layer 12 is stacked on the silicon layer 11. The insulating dielectric layer 12 is etched to form multiple first contact holes 121 communicating with the floating P-region 114. Along the first direction X, the multiple first contact holes 121 are spaced apart. The emitter metal layer 15 is stacked on the insulating dielectric layer 12, and the emitter metal layer 15 at least partially passes through the first contact holes 121 and connects to the silicon layer 11.
[0035] In the power device 10 of this application embodiment, a plurality of first contact holes 121 communicating with the floating P region 114 are provided at intervals along the first direction X. The first contact holes 121 can conduct away the holes accumulated in the floating P region 114, reduce the displacement current, enhance the control of the gate on EMI and turn-on losses, and avoid the problem of current overshoot and increased turn-on losses caused by excessive current change rate due to rapid charging of the gate capacitor, or even damage to the power device 10. At the same time, in the area where the first contact holes 121 are not provided, the floating P region 114 can retain the effect of carrier injection, resulting in a lower on-state voltage drop. Thus, the switching loss and conduction loss of the power device 10 can be reduced, and the energy utilization rate can be improved.
[0036] It should be noted that the power device 10 can be either an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, this embodiment of the application can be described using an IGBT as an example. Furthermore, the power device 10 can be an N-type power device or a P-type power device.
[0037] The first direction X intersects with the second direction Y, and the plane containing the first direction X and the second direction Y can be parallel to the power device 10. For example, in this embodiment, the first direction X is perpendicular to the second direction Y, wherein the first direction X can be the horizontal direction of the power device 10, and the second direction Y can be the vertical direction of the power device 10.
[0038] The silicon layer 11 is made primarily of silicon, which has medium to high resistivity. The silicon layer 11 may include a first trench 111, a second trench 112, a drift region 113, a floating p-base region 114, and a p-base region 115. The first trench 111 and the second trench 112 are formed by etching downwards onto the upper surface of the drift region 113, and the first trench 111 and the second trench 112 extend along a first direction X. Multiple first trenches 111 and second trenches 112 may be included, and they are arranged parallel to each other and spaced apart along a second direction Y. The arrangement of the first trenches 111 and the second trenches 112 along the second direction Y can be configured according to actual conditions. For example, in some examples, a first trench 111 is provided between two adjacent second trenches 112 along the second direction Y; or, for another example, two first trenches 111 are provided between two adjacent second trenches 112 along the second direction Y. The width and depth of the first groove 111 and the second groove 112 may be the same or different, and this utility model does not limit them here.
[0039] Please see Figure 1 and Figure 4 Along the second direction Y, the floating P-region 114 is located between the first trench 111 and / or between the first trench 111 and the second trench 112. The floating P-region 114 is used to enhance carrier injection efficiency, thereby improving conduction capability and switching speed. Along the second direction Y, the P-body region 115 is located between the second trench 112 and serves to connect and control current flow.
[0040] Please see Figure 1-3 Furthermore, the power device 10 also includes a dummy gate 14 and a main gate 13, wherein the dummy gate 14 is located in a first trench 111 and the main gate 13 is located in a second trench 112. The dummy gate 14 and the main gate 13 can be formed in the first trench 111 and the second trench 112 respectively using physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. The main gate 13 and the dummy gate 14 can be made of polycrystalline silicon or doped polycrystalline silicon material.
[0041] An insulating dielectric layer 12 is stacked on a silicon layer 11. The insulating dielectric layer 12 can be formed on the surface of the silicon layer 11 and the inner surface of the first trench 111 and the second trench 112 by means of, but not limited to, thermal oxidation, physical vapor deposition or chemical vapor deposition processes. The insulating dielectric layer 12 can be made of silicon dioxide.
[0042] The insulating dielectric layer 12 is etched to form a first contact hole 121 and a second contact hole 122. The lengths of both the first contact hole 121 and the second contact hole 122 extend along a first direction X, with the length of the second contact hole 122 being greater than the length of the first contact hole 121. Along a second direction Y, the widths of the first contact hole 121 and the second contact hole 122 can be equal. Along a third direction Z, the depth of the first contact hole 121 is equal to the depth of the second contact hole 122. Here, the third direction Z is the stacking direction of the silicon layer 11 and the insulating dielectric layer 12.
[0043] The first contact hole 121 may include multiple holes, and the lengths of different first contact holes 121 may be the same or different.
[0044] The first contact hole 121 communicates with the floating P region 114 and is used to guide away the cavities accumulated in the floating P region 114. Along the second direction Y, the first contact hole 121 is located between the first groove 111 or between the first groove 111 and the second groove 112. Multiple first contact holes 121 communicating with the floating P region 114 are provided between each adjacent first groove 111 and the second groove 112. And / or, multiple first contact holes 121 communicating with the floating P region 114 are provided between each adjacent first groove 111 and the second groove 112. Along the first direction X, multiple first contact holes 121 are spaced apart and all communicate with the floating P region 114. Furthermore, along the first direction X, the lengths of the multiple spaced first contact holes 121 can be the same or different.
[0045] Understandably, the floating P-region 114 will collect a large number of holes, causing its potential to rise. This results in a significant displacement current between the floating P-region 114 and the virtual gate 14, leading to the gate becoming uncontrollable by the applied voltage and a poor relationship between electromagnetic interference (EMI) and turn-on losses. Therefore, by providing multiple first contact holes 121 at intervals along the first direction X, communicating with the floating P-region 114, the accumulated holes in the floating P-region 114 can be discharged. In areas where the first contact holes 121 are not provided, the floating P-region 114 retains the carrier injection effect, resulting in a lower on-state voltage drop. Thus, while reducing the on-state voltage drop, the displacement current can be reduced, enhancing the gate's control over EMI and turn-on losses.
[0046] The second contact hole 122 communicates with the P-body region 115. Along the second direction Y, the second contact hole 122 is located between the second grooves 112 and the second grooves 112. Furthermore, each adjacent second groove 112 contains only one second contact hole 122 that communicates with the P-body region 115.
[0047] An emitter metal layer 15 is stacked on the insulating dielectric layer 12. The emitter metal layer 15 can be made of a conductive metal material, for example, it can be made of aluminum. The emitter metal layer 15 serves as the output electrode of the power device 10, used to output current.
[0048] Please refer to further information. Figure 1 and Figure 2 The emitter metal layer 15 at least partially passes through the first contact hole 121 and connects to the floating P-region 114. Holes accumulated in the area where the floating P-region 114 connects to the first contact hole 121 are conducted away through the emitter metal layer within the first contact hole 121. The emitter metal layer 15 also at least partially passes through the second contact hole 122 and connects to the P-body region 115. The P-body region 115, through its interaction with the main gate 13, controls the on / off state of the power device 10. When a positive voltage is applied to the main gate 13, a conductive channel is formed at the interface between the P-body region 115 and the main gate 13, turning on the power device 10. Conversely, when the gate voltage decreases or reverses, the conductive channel closes, and the power device 10 is turned off.
[0049] The emitter metal layer 15, main gate 13, P-body region 115, and drift region 113 form effective cells. When a voltage is applied to the main gate 13, electrons can flow in the electron mobility channel formed by the emitter metal layer 15, N+ emitter region 116, P-body region 115, and drift region 113. The emitter metal layer 15, floating P-region 114, dummy gate 14, and drift region 113 form dummy gate cells. Understandably, the effective cells and dummy gate cells can be configured as needed, and the specific structural features are not limited.
[0050] Please see Figure 5 , Figure 5 This diagram compares the on-state voltage Vce of power devices employing a full-hole structure, a floating P-structure, and the power device 10 of this proposal in related technologies. At a current density of 500 A / cm², the on-state voltages Vce of the full-hole structure, the floating P-structure, and this application are 2.10 V, 1.77 V, and 1.83 V, respectively. Therefore, compared to the full-hole structure, the on-state voltage Vce of this application is significantly reduced.
[0051] Please see Figure 6 , Figure 6 This diagram illustrates a comparison of the current change rate di / dt of power devices employing full contact hole structures, power devices employing floating P-structures, and the power device 10 proposed in this invention. Figure 6As can be seen, when the driving resistor Rg increases from 10Ω to 100Ω, the current change rate di / dt of the floating P-structure power device decreases from 615A / us to 510A / us, a decrease of only 17%. In contrast, the current change rate di / dt of the power device 10 in this application decreases from 393A / us to 190A / us, a decrease of 51.6%. Therefore, the power device 10 in this application can maintain a small current change rate di / dt, and it can be significantly adjusted by the gate resistor Rg. In other words, the current change rate di / dt of the power device 10 in this application has good controllability.
[0052] Please see Figure 1 or Figure 4 In some embodiments, along the first direction X, the ratio of the length L1 of the first contact hole 121 to the distance L between two adjacent first contact holes 121 ranges from 1 / 20 to 1 / 4, that is, 1 / 20 ≤ L1 / L ≤ 1 / 4. For example, L1 / L can be 1 / 20, 1 / 18, 15 / 1, 1 / 12, 1 / 10, 1 / 8, 1 / 5, or 1 / 4, etc. It is understood that the ratio of the length L1 of the first contact hole 121 to the distance L between two adjacent first contact holes 121 can be adjusted according to actual needs.
[0053] Thus, by limiting the ratio of the length of the first contact hole 121 to the spacing between two adjacent first contact holes 121, the problem of current overshoot and increased turn-on loss caused by excessive current change rate due to rapid charging of the gate capacitor is avoided, and even damage to the power device 10 is prevented. At the same time, in the area where the first contact hole 121 is not provided, the floating P region 114 can retain the effect of carrier injection, resulting in a lower on-state voltage drop.
[0054] Please see Figure 2 In some embodiments, along the third direction Z, the over-etched area H1 of the first contact hole 121 ranges from 0.1 micrometers to 1 micrometer. Optionally, the over-etched area H1 of the first contact hole 121 can be 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.5 micrometers, 0.7 micrometers, 0.8 micrometers, or 1 micrometer, etc.
[0055] It should be noted that the third direction Z refers to the stacking direction of the silicon layer 11 and the insulating dielectric layer 12, which is also the direction of electron flow. The first direction X, the second direction Y, and the third direction Z intersect each other, and the third direction Z is perpendicular to the first direction X and the second direction Y. Over-etching refers to a phenomenon where the etching line extends beyond a predetermined range during the etching process. During the etching of the insulating dielectric layer 12 to form the first contact hole 121, the over-etching region can be the area extending beyond the insulating dielectric layer 12, that is, the area where the silicon layer 11 is etched.
[0056] In this way, by limiting the over-etched area H1 of the first contact hole 121, it is ensured that the first contact hole 121 can be connected to the floating P region 114, so that the holes accumulated in the floating P region 114 can be conducted away through the first contact hole 121. This avoids the problem of current overshoot and increased turn-on loss caused by the rapid charging of the gate capacitor, which leads to an excessively large current change rate di / dt, and even damage to the power device 10.
[0057] Please see Figure 2 or Figure 3 In some embodiments, the silicon layer 11 further includes an N+ emitter region 116, which is located in the P-body region 115.
[0058] Specifically, the N+ emitter region 116 is a highly doped N-type semiconductor material region in the power device 10, located on top of the P-body region 115 and adjacent to the main gate 13. The main gate 13, together with the N+ emitter region 116, the emitter metal layer 15, the P-body region 115, and the drift region 113, constitute an effective cell. The N+ emitter region 116 is used to inject electrons into the P-body region 115. These electrons are controlled within the P-body region 115 and partially transferred to the collector region, thereby amplifying the current.
[0059] Please refer to further information. Figure 2 or Figure 3 In some embodiments, the silicon layer 11 further includes a buffer zone 117 and a collector region 118, with the buffer zone 117 located between the drift region 113 and the collector region 118. The power device 10 also includes a collector metal layer 16 located on the side of the collector region 118 opposite to the buffer zone 117.
[0060] It should be noted that the buffer zone 117 is made of highly doped N-type silicon material and is used to prevent some holes from being injected from the collector region into the drift region 113 when the power device 10 is in the off state, thereby reducing turn-off losses. Simultaneously, the buffer zone 117 also serves to cut off the electric field of the drift region 113. The collector region 118 is made of highly doped P-type silicon material and serves as the anode of the power device 10, collecting the hole current injected from the drift region 113 and discharging it to the external circuit. When the IGBT is turned on, holes are injected from the P-type collector region through the drift region 113 and the P-body region 115 into the N+ emitter region 116, recombine with electrons to form a current. The collector metal layer 16 is used for output current.
[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0062] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A power device, characterized in that, include: The silicon layer includes a floating P-region and a plurality of first trenches and second trenches extending along a first direction. Along the second direction, the first trenches and the second trenches are distributed in parallel with intervals. The floating P-region is located between the first trenches or between the first trenches and the second trenches. An insulating dielectric layer is stacked on the silicon layer. The insulating dielectric layer is etched to form a plurality of first contact holes that communicate with the floating P region. The plurality of first contact holes are spaced apart along a first direction. An emitter metal layer is stacked on the insulating dielectric layer, and the emitter metal layer is connected to the silicon layer at least partially through the first contact hole.
2. The power device according to claim 1, characterized in that, Along the first direction, the ratio of the length of the first contact hole to the distance between two adjacent first contact holes ranges from 1 / 20 to 1 / 4.
3. The power device according to claim 2, characterized in that, Along the third direction, the over-etched area of the first contact hole ranges from 0.1 micrometers to 1 micrometer.
4. The power device according to claim 2, characterized in that, The silicon layer further includes a P-body region located between the second trenches. The insulating dielectric layer is etched to form a plurality of second contact holes extending along a first direction. The second contact holes communicate with the P-body region. The emitter metal layer at least partially passes through the second contact holes and is connected to the silicon layer.
5. The power device according to claim 4, characterized in that, Along the first direction, the length of the second contact hole is greater than the length of the first contact hole, and along the third direction, the depth of the first contact hole is equal to the depth of the second contact hole.
6. The power device according to claim 5, characterized in that, The power device further includes: The dummy gate is located within the first trench; The main gate is located within the second trench.
7. The power device according to claim 4, characterized in that, The silicon layer further includes: The N+ emitter region is located in the P-body region.
8. The power device according to claim 1, characterized in that, The silicon layer further includes: The drift region has its upper surface etched downwards to form the first trench and the second trench.
9. The power device according to claim 8, characterized in that, The silicon layer further includes a buffer zone and a collector region, wherein the buffer zone is located between the drift region and the collector region; The power device further includes a collector metal layer located on the side of the collector region away from the buffer zone.
10. The power device according to claim 1, characterized in that, The power device includes either an insulated gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.