Groove type power MOS device
By designing doped N-type contacts and optimizing the structural ratio in trench power MOS devices, the problem of high high-frequency switching losses has been solved, resulting in improved high-frequency response speed and reduced losses, thus expanding the application range.
Patent Information
- Application Number
- CN202421675167.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-07-16
AI Technical Summary
Existing trench-type power MOS devices have high switching losses during high-frequency switching, making it difficult to meet the high-frequency application requirements of thin, light, and small products.
By designing a heavily doped N-type source region in a trench-type power MOS device, surrounding and under the trench end with a medium-doped N-type contact, and using a conductive polysilicon gate, optimizing the ratio of the P-type well region to the trench, and using an aluminum or copper metal layer, the high-frequency switching response speed can be improved.
This improves the high-frequency switching response speed of trench power MOS devices and reduces losses at high frequencies, thereby expanding the application range of the devices.
Smart Images
Figure CN223503282U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of MOS devices, and in particular to a trench-type power MOS device. Background Technology
[0002] Trench-type power MOSFETs offer advantages such as high integration, low on-resistance, fast switching speed, and low switching losses. They have largely replaced planar power trench-type power MOSFETs in low- and medium-voltage applications and are widely used in various power management and switching circuits. The current development direction for power trench-type power MOSFETs is to achieve high-performance, high-reliability products using fewer lithography steps and simpler process flows.
[0003] In particular, as product applications move towards thinner, lighter, and smaller designs, achieving these goals requires increasing the switching frequency of the entire system. This leads to increasingly significant switching losses in trench power MOS devices. Therefore, improving the switching speed and reducing switching losses of these devices is of great importance. Summary of the Invention
[0004] The purpose of this invention is to provide a trench-type power MOS device, which improves the response speed of high-frequency switching and reduces losses in high-frequency applications, thereby expanding the application range of the device.
[0005] To achieve the above objectives, the technical solution adopted by this utility model is: a trench-type power MOS device, comprising: an N-type silicon substrate and an N-type epitaxial layer located on the upper surface of the N-type silicon substrate, wherein the lower surface of the N-type silicon substrate has a heavily doped N-type drain region, and the surface of the heavily doped N-type drain region opposite to the N-type silicon substrate has a first metal layer.
[0006] The upper part of the N-type epitaxial layer has a P-type well region, and a trench located in the P-type well region extends into the N-type epitaxial layer. The upper part of the P-type well region and the periphery of the trench have a heavily doped N-type source region. The trench has a gate portion, and an insulating layer is provided between the gate portion and the inner wall of the trench.
[0007] The heavily doped N-type source region is surrounded and covered by a medium-doped N-type contact at the periphery and below the end away from the trench. The upper end of the medium-doped N-type contact is flush with the upper end of the P-type well region and contacts a second metal layer. The region below the medium-doped N-type contact is the area of the P-type well region. An insulating dielectric layer is located above the trench and covers the gate portion. The second metal layer is located on the insulating dielectric layer and the heavily doped N-type source region.
[0008] The following are further improvements to the above technical solution:
[0009] 1. In the above scheme, the depth ratio of the P-type well region to the medium-doped N-type contact region is 10:6~8.
[0010] 2. In the above scheme, the gate portion is conductive polycrystalline silicon.
[0011] 3. In the above scheme, the height ratio of the P-type well area to the trench is 1:3~4.
[0012] 4. In the above scheme, the first metal layer and the second metal layer are aluminum metal layers or copper metal layers.
[0013] Due to the application of the above technical solution, this utility model has the following advantages compared with the prior art:
[0014] This utility model relates to a trench-type power MOS device, in which a moderately doped N-type contact is covered around and below the end of the heavily doped N-type source region away from the trench. The upper end of the moderately doped N-type contact is flush with the upper end of the P-type well region and contacts a second metal layer. The area below the moderately doped N-type contact is the region of the P-type well region. This improves the response speed of high-frequency switching, reduces the loss in high-frequency applications, and thus expands the application range of the device. Attached Figure Description
[0015] Appendix Figure 1 This is a schematic diagram of the trench-type high-power MOSFET device of this utility model.
[0016] In the above figures: 1. N-type silicon substrate; 2. N-type epitaxial layer; 3. First metal layer; 4. P-type well region; 5. Trench; 6. Gate portion; 7. Insulating layer; 8. Heavily doped N-type source region; 9. Insulating dielectric layer; 10. Second metal layer; 11. Heavily doped N-type drain region; 12. Medium doped N-type contact portion. Detailed Implementation
[0017] The present patent can be further understood through the specific embodiments given below, but they are not intended to limit the present patent.
[0018] Example 1: A trench-type power MOS device, characterized in that: it includes: an N-type silicon substrate 1 and an N-type epitaxial layer 2 located on the upper surface of the N-type silicon substrate 1, the lower surface of the N-type silicon substrate 1 having a heavily doped N-type drain region 11, and the surface of the heavily doped N-type drain region 11 opposite to the N-type silicon substrate 1 having a first metal layer 3.
[0019] The upper part of the N-type epitaxial layer 2 has a P-type well region 4, and a trench 5 located in the P-type well region 4 extends into the N-type epitaxial layer 2. The upper part of the P-type well region 4 and the periphery of the trench 5 have a heavily doped N-type source region 8. The trench 5 has a gate portion 6, and an insulating layer 7 is provided between the gate portion 6 and the inner wall of the trench 5.
[0020] The heavily doped N-type source region 8 is surrounded and covered by a medium-doped N-type contact 12 at the periphery and below the end away from the trench 5. The upper end of the medium-doped N-type contact 12 is flush with the upper end of the P-type well region 4 and contacts a second metal layer 10. The area below the medium-doped N-type contact 12 is the region of the P-type well region 4. An insulating dielectric layer 9 is located above the trench 5 and covers the gate portion 6. The second metal layer 10 is located on the insulating dielectric layer 9 and the heavily doped N-type source region 8.
[0021] The depth ratio of the P-type well region 4 to the medium-doped N-type contact 12 is 10:6~8.
[0022] The aforementioned gate portion 6 is made of conductive polysilicon.
[0023] The height ratio of the P-type trap region 4 to the trench 5 is 1:3~4.
[0024] The first metal layer 3 and the second metal layer 10 mentioned above are aluminum metal layers or copper metal layers.
[0025] Example 2: A trench-type power MOS device, characterized in that: it includes: an N-type silicon substrate 1 and an N-type epitaxial layer 2 located on the upper surface of the N-type silicon substrate 1, the lower surface of the N-type silicon substrate 1 having a heavily doped N-type drain region 11, and the surface of the heavily doped N-type drain region 11 opposite to the N-type silicon substrate 1 having a first metal layer 3.
[0026] The upper part of the N-type epitaxial layer 2 has a P-type well region 4, and a trench 5 located in the P-type well region 4 extends into the N-type epitaxial layer 2. The upper part of the P-type well region 4 and the periphery of the trench 5 have a heavily doped N-type source region 8. The trench 5 has a gate portion 6, and an insulating layer 7 is provided between the gate portion 6 and the inner wall of the trench 5.
[0027] The heavily doped N-type source region 8 is surrounded and covered by a medium-doped N-type contact 12 at the periphery and below the end away from the trench 5. The upper end of the medium-doped N-type contact 12 is flush with the upper end of the P-type well region 4 and contacts a second metal layer 10. The area below the medium-doped N-type contact 12 is the region of the P-type well region 4. An insulating dielectric layer 9 is located above the trench 5 and covers the gate portion 6. The second metal layer 10 is located on the insulating dielectric layer 9 and the heavily doped N-type source region 8.
[0028] The depth ratio of the P-type well region 4 to the medium-doped N-type contact 12 is 10:6~8.
[0029] The aforementioned gate portion 6 is made of conductive polysilicon.
[0030] The height ratio of the P-type trap region 4 to the trench 5 is 1:3~4.
[0031] The first metal layer 3 and the second metal layer 10 mentioned above are aluminum metal layers or copper metal layers.
[0032] When using the above-mentioned trench-type power MOS device, a medium-doped N-type contact is covered around and below the end of the heavily doped N-type source region away from the trench. The upper end of the medium-doped N-type contact is flush with the upper end of the P-type well region and contacts a second metal layer. The area below the medium-doped N-type contact is the region of the P-type well region. This improves the response speed of high-frequency switching, reduces the loss that is preferred for use in high-frequency conditions, and thus expands the application range of the device.
[0033] The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be included within the scope of protection of this utility model.
Claims
1. A trench-type power MOS device, characterized in that: include: The N-type silicon substrate (1) and the N-type epitaxial layer (2) located on the upper surface of the N-type silicon substrate (1) have a heavily doped N-type drain region (11) on the lower surface of the N-type silicon substrate (1) and a first metal layer (3) on the surface of the heavily doped N-type drain region (11) opposite to the N-type silicon substrate (1). The upper part of the N-type epitaxial layer (2) has a P-type well region (4), and a trench (5) located in the P-type well region (4) extends into the N-type epitaxial layer (2). The upper part of the P-type well region (4) and the periphery of the trench (5) have a heavily doped N-type source region (8). The trench (5) has a gate portion (6), and an insulating layer (7) is provided between the gate portion (6) and the inner wall of the trench (5). The heavily doped N-type source region (8) is surrounded and covered by a medium-doped N-type contact (12) at the periphery and below the end away from the trench (5). The upper end of the medium-doped N-type contact (12) is flush with the upper end of the P-type well region (4) and in contact with a second metal layer (10). The area below the medium-doped N-type contact (12) is the region of the P-type well region (4). An insulating dielectric layer (9) is located above the trench (5) and covers the gate portion (6). The second metal layer (10) is located on the insulating dielectric layer (9) and the heavily doped N-type source region (8).
2. The trench-type power MOS device according to claim 1, characterized in that: The depth ratio of the P-type well region (4) to the medium-doped N-type contact region (12) is 10:6~8.
3. The trench-type power MOS device according to claim 1 or 2, characterized in that: The gate portion (6) is made of conductive polycrystalline silicon.
4. The trench-type power MOS device according to claim 1 or 2, characterized in that: The height ratio of the P-type trap region (4) to the trench (5) is 1:3~4.
5. The trench-type power MOS device according to claim 1 or 2, characterized in that: The first metal layer (3) and the second metal layer (10) are aluminum metal layers or copper metal layers.