Vertical dual-gate insulated transistor

Abstract

A vertical dual-gate insulated transistor includes a bottom electrode and a gallium nitride semiconductor unit. The bottom electrode comprises a conductive metal substrate integrally formed by a conductive metal material; the gallium nitride semiconductor unit comprises a first P-type gallium nitride semiconductor layer located on the surface of the conductive metal substrate, a first N-type gallium nitride semiconductor layer formed on the surface of the first P-type gallium nitride semiconductor layer, and a second P-type gallium nitride semiconductor layer formed downwards from part of the top surface of the first N-type gallium nitride semiconductor layer; the second N-type gallium nitride semiconductor layer is formed downwards from part of the top surface of the second P-type gallium nitride semiconductor layer; the emitting electrode is arranged on the top surface, opposite to the bottom electrode, of the second N-type gallium nitride semiconductor layer; the grid electrode and the grid electrode dielectric layer are located on the top surface of the second P-type gallium nitride semiconductor layer; through the conductive metal substrate integrally formed by the conductive metal material, low resistance and good heat dissipation effects are achieved.

Description

Technical Field

[0001] This utility model relates to a gallium nitride device, and more particularly to a vertical dual-gate insulated transistor. Background Technology

[0002] Dual-gate insulated transistors (DGISTs) have advantages such as low startup voltage and low on-resistance, and are often used for switching control in high-power devices. Current gallium nitride (GaN) DGISTs typically use sapphire or silicon carbide as the substrate material. However, because sapphire is an insulating material, it limits the structural design of DGISTs. Furthermore, sapphire's poor heat dissipation results in difficulty in dissipating heat during operation when using sapphire as the substrate.

[0003] Therefore, effectively utilizing the vertical space of components and avoiding the accumulation of heat during operation are crucial considerations. Utility Model Content

[0004] The purpose of this invention is to provide a vertical dual-gate insulated transistor with low resistance and good heat dissipation.

[0005] The present invention relates to a vertical dual-gate insulated transistor, comprising a bottom electrode and a gallium nitride semiconductor unit.

[0006] The bottom electrode includes a conductive metal substrate integrally formed of conductive metal material.

[0007] The gallium nitride semiconductor unit includes a first P-type gallium nitride semiconductor layer located on the surface of the conductive metal substrate, a first N-type gallium nitride semiconductor layer formed on the surface of the first P-type gallium nitride semiconductor layer, a second P-type gallium nitride semiconductor layer formed downward from a portion of the top surface of the first N-type gallium nitride semiconductor layer, a second N-type gallium nitride semiconductor layer formed downward from a portion of the top surface of the second P-type gallium nitride semiconductor layer, wherein the side of the second N-type gallium nitride semiconductor layer adjacent to the second P-type gallium nitride semiconductor layer has a channel spacing parallel to the top surface of the first N-type gallium nitride semiconductor layer, an emitter disposed on the top surface of the second N-type gallium nitride semiconductor layer opposite to the bottom electrode, and the emitter is in contact with the surface of the second N-type gallium nitride semiconductor layer away from the channel spacing, a gate located on the top surface of the second P-type gallium nitride semiconductor layer, and the gate is correspondingly located above the channel spacing, and a gate dielectric layer between the gate and the channel spacing.

[0008] Preferably, in the vertical dual-gate insulated transistor of the present invention, the bottom electrode further includes a conductive protective layer covering the surface of the conductive metal substrate opposite to the gallium nitride semiconductor cell.

[0009] Preferably, the vertical dual-gate insulated transistor of the present invention further includes a bonding metal layer between the conductive metal substrate and the gallium nitride semiconductor unit, and is made of either gold or indium.

[0010] Preferably, the vertical dual-gate insulated transistor of the present invention further includes an ohmic metal layer between the bonding metal layer and the gallium nitride semiconductor unit, wherein the gallium nitride semiconductor unit is located on the surface of the ohmic metal layer opposite to the bonding metal layer and is ohmic contact connected to the ohmic metal layer.

[0011] The beneficial effects of this utility model are as follows: it provides a vertical double-gate insulated transistor, and by making the bottom electrode of the vertical double-gate insulated transistor integrally formed of conductive metal material, it can achieve low resistance and good heat dissipation. Attached Figure Description

[0012] Figure 1 This is a side sectional view illustrating an embodiment of the vertical dual-gate insulated transistor of this invention;

[0013] Figure 2 This is a side sectional view, showing the first semi-finished product provided in the providing step;

[0014] Figure 3 This is a side cross-sectional view, showing the structure obtained from the temporary substrate formation step;

[0015] Figure 4 This is a side cross-sectional view, showing the structure obtained after the substrate removal step;

[0016] Figure 5 This is a side cross-sectional view, showing the second semi-finished product formed in the metal layer formation step;

[0017] Figure 6 This is a side cross-sectional view, showing the third semi-finished product formed in the bonding step. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Before this utility model is described in detail, it should be noted that similar elements are represented by the same reference numerals in the following description.

[0020] The relevant technical content, features, and effects of this utility model will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. Furthermore, it should be noted that the accompanying drawings are only for illustrating the structural and / or positional relationships between components and are not related to the actual dimensions of each component.

[0021] See Figure 1 An embodiment of the vertical dual-gate insulated transistor of the present invention includes a bottom electrode 2, a bonding metal layer 3, an ohmic metal layer 4, and a gallium nitride semiconductor unit 5.

[0022] The bottom electrode 2 includes a conductive metal substrate 21 integrally formed of conductive metal material, and a conductive protective layer 22 covering the surface of the conductive metal substrate 21.

[0023] The bonding metal layer 3 completely covers the conductive metal substrate 21 and is opposite to the other surface of the conductive protective layer 22, and the constituent material of the bonding metal layer 3 is selected from gold and indium.

[0024] The ohmic metal layer 4 fully covers and contacts the surface of the bottom electrode 2 opposite to the bonding metal layer 3.

[0025] The gallium nitride semiconductor unit 5 is located on the surface of the ohmic metal layer 4 opposite to the bonding metal layer 3 and is ohmic contact connected to the ohmic metal layer 4. It includes a first P-type gallium nitride semiconductor layer 51 formed on the surface of the ohmic metal layer 4, a first N-type gallium nitride semiconductor layer 52 formed on the surface of the first P-type gallium nitride semiconductor layer 51, a second P-type gallium nitride semiconductor layer 53 formed downward from a portion of the top surface of the first N-type gallium nitride semiconductor layer 52, a second N-type gallium nitride semiconductor layer 54 formed downward from a portion of the top surface of the second P-type gallium nitride semiconductor layer 53, an emitter 55 disposed on the top surface of the second N-type gallium nitride semiconductor layer 54 opposite to the bottom electrode 2, a gate 56 located on the top surface of the second P-type gallium nitride semiconductor layer 53, and a gate dielectric layer 57.

[0026] As described above, the adjacent sides of the second N-type gallium nitride semiconductor layer 54 and the second P-type gallium nitride semiconductor layer 53 have a lateral channel spacing parallel to the top surface of the first N-type gallium nitride semiconductor layer 52. The emitter 55 is in contact with the surface of the second N-type gallium nitride semiconductor layer 54 away from the channel spacing. The gate 56 is located above the channel spacing, and the gate dielectric layer 57 is located between the gate 56 and the channel spacing.

[0027] The conductive metal substrate 21 is selected from tungsten, copper, tungsten-copper alloy, or molybdenum.

[0028] The conductive protective layer 22 is selected from gold or titanium.

[0029] The ohmic metal layer 4 is selected from titanium, titanium tungsten, chromium, or gold.

[0030] The vertical dual-gate insulated transistor of this invention utilizes the conductive metal substrate 21 integrally formed of conductive metal material as the electrode (collector) for external connection of the vertical dual-gate insulated transistor. In addition to having low resistance, it can also achieve good heat dissipation effect.

[0031] The manufacturing method of the vertical dual-gate insulated transistor of this utility model is described below.

[0032] The method for fabricating the vertical dual-gate insulated transistor includes a provisioning step, a temporary substrate formation step, a substrate removal step, a metal layer formation step, a bonding step, and a temporary substrate removal step.

[0033] See Figure 2 First, the provision step is performed to provide a first semi-finished product 101. The first semi-finished product 101 includes a sapphire substrate 900 and a gallium nitride semiconductor unit 5 formed on the surface of the sapphire substrate 900. The gallium nitride semiconductor unit 5 has the structure described above. Since the relevant processes for forming the gallium nitride semiconductor unit 5 are known to those skilled in the art, they will not be described in detail here.

[0034] Next, the temporary substrate formation step is performed, in which the glass substrate 901 is bonded to the surface of the gallium nitride semiconductor unit 5 on the sapphire substrate 900 using paraffin wax 902, to obtain the following: Figure 3 The structure shown.

[0035] Then, the substrate removal step is performed, and the sapphire substrate 900 of the first semi-finished product 101 is removed by laser peeling, exposing the gallium nitride semiconductor unit 5 on the surface of the glass substrate 901, resulting in the following: Figure 4 The structure shown.

[0036] Next, the metal layer formation step is performed, in which an ohmic metal layer 4 and a bonding metal layer 3a are sequentially sputtered onto the exposed surface of the gallium nitride semiconductor unit 5, forming as shown in the figure. Figure 5 The second semi-finished product 102 shown.

[0037] Next, the bonding step is performed to provide a bonding conductive plate 20. The bonding conductive plate 20 has a conductive metal substrate 21 integrally formed of a conductive metal material, a bonding metal layer 3b covering the surface of the conductive metal substrate 21, and a conductive protective layer 22 covering the surface of the conductive metal substrate 21 opposite to the bonding metal layer 3b. Then, the bonding metal layer 3b of the bonding conductive plate 20 and the bonding metal layer 3a of the second semi-finished product 102 are bonded together by metal bonding to obtain... Figure 6 The third semi-finished product 103 is shown.

[0038] As mentioned above, the ohmic metal layer 4 is composed of titanium, titanium-tungsten, chromium, or gold; the conductive metal substrate 21 is composed of tungsten, copper, tungsten-copper alloy, or molybdenum. The bonding metal layer 3a and the bonding metal layer 3b are made of the same material, and after bonding, the bonding metal layer 3a and the bonding metal layer 3b together constitute the bonding metal layer 3.

[0039] Finally, the temporary substrate removal step is performed again. The paraffin 902 is melted using a thermal melting method to separate the glass substrate 901 from the gallium nitride semiconductor unit 5, thus obtaining the product shown below. Figure 1 The vertical dual-gate insulated transistor shown.

[0040] In summary, the vertical dual-gate insulated transistor of this invention uses metal bonding to bond the semiconductor material to the conductive metal substrate 21, thus completing the substrate transfer of the vertical dual-gate insulated transistor (from the sapphire substrate 900 to the conductive metal substrate 21). The vertical dual-gate insulated transistor obtained after substrate transfer achieves low resistance and good heat dissipation because the bottom electrode 2 (collector) in contact with the gallium nitride semiconductor unit 5 is entirely composed of conductive metal material, thereby effectively achieving the purpose of this invention.

[0041] However, the above description is merely an embodiment of this utility model and should not be construed as limiting the scope of this utility model. Any simple equivalent changes and modifications made in accordance with the claims and description of this utility model shall still fall within the scope of this utility model.

Claims

1. A vertical dual-gate insulated transistor, characterized in that, Include, The bottom electrode includes a conductive metal substrate integrally formed of a conductive metal material; and A gallium nitride semiconductor cell includes a first P-type gallium nitride semiconductor layer located on the surface of the conductive metal substrate, a first N-type gallium nitride semiconductor layer formed on the surface of the first P-type gallium nitride semiconductor layer, a second P-type gallium nitride semiconductor layer formed downward from a portion of the top surface of the first N-type gallium nitride semiconductor layer, a second N-type gallium nitride semiconductor layer formed downward from a portion of the top surface of the second P-type gallium nitride semiconductor layer, wherein the side of the second N-type gallium nitride semiconductor layer adjacent to the second P-type gallium nitride semiconductor layer has a channel spacing parallel to the top surface of the first N-type gallium nitride semiconductor layer, an emitter disposed on the top surface of the second N-type gallium nitride semiconductor layer opposite to the bottom electrode, and the emitter is in contact with the surface of the second N-type gallium nitride semiconductor layer away from the channel spacing, a gate located on the top surface of the second P-type gallium nitride semiconductor layer, and the gate is correspondingly located above the channel spacing, and a gate dielectric layer between the gate and the channel spacing.

2. The vertical dual-gate insulated transistor according to claim 1, characterized in that, The bottom electrode also includes a conductive protective layer covering the surface of the conductive metal substrate facing the gallium nitride semiconductor cell.

3. The vertical dual-gate insulated transistor according to claim 1, characterized in that, The vertical dual-gate insulated transistor further includes a bonding metal layer between the conductive metal substrate and the gallium nitride semiconductor unit, and is made of either gold or indium.

4. The vertical dual-gate insulated transistor according to claim 3, characterized in that, The vertical dual-gate insulated transistor further includes an ohmic metal layer between the bonding metal layer and the gallium nitride semiconductor cell, wherein the gallium nitride semiconductor cell is located on the surface of the ohmic metal layer opposite to the bonding metal layer and is ohmic contact connected to the ohmic metal layer.

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