Communication and power supply collinear interlocking protection system

Abstract

The utility model relates to the technical field of communication circuits, in particular to a communication and power supply collinear interlocking protection system, which comprises a host circuit and a slave circuit. The host circuit is composed of a host transmit-receive circuit, a triode Q3, a triode Q4 and a plurality of resistors. And the triode Q4 is connected to a + 5V voltage end, a 24Vi n power supply and a 5V voltage end through a series of resistors. Meanwhile, the 5V voltage end is connected with the host transceiver circuit and the third end of the triode Q4. The triode Q3 is connected with the 485EN end through a resistor R36 and is grounded through a resistor R33, the second end of the triode Q3 is grounded, and the third end of the triode Q3 is connected with the first end of the triode Q4 through a resistor R43. And the slave circuit comprises a slave receiving and transmitting circuit, an energy storage circuit, a connector, a fuse F1, a voltage-regulator tube D1 and a 5V voltage end. And the 5V voltage end is connected with the slave receiving and transmitting circuit and the energy storage circuit. According to the system, slave communication and power supply share the bus, an additional power supply line is not needed, and the cost is reduced.

Description

Technical Field

[0001] This utility model relates to the field of communication circuit technology, and more particularly to a communication and power supply co-line interlocking protection system. Background Technology

[0002] In wired communication between electric valves and temperature control panels, the host (temperature control panel) and the slave (electric valve) need to communicate via two buses and be powered by two other lines, resulting in complex wiring and high costs. Utility Model Content

[0003] To address the aforementioned issues, this invention provides a communication and power supply co-line interlocking protection system, which enables slave communication and power supply to share a bus, eliminating the need for additional power supply lines, simplifying the system's wiring structure, and reducing system costs.

[0004] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0005] A communication and power supply co-line interlocking protection system includes: a master circuit, a slave circuit, and a 485 bus. The master circuit is connected to the slave circuit via the 485 bus.

[0006] The host circuit includes:

[0007] The main unit transceiver circuit includes transistors Q3 and Q4, resistors R23, R33, R36, R38, R39, and R4.

[0008] Terminal 1 of transistor Q4 is connected to the +5V voltage terminal via resistors R4 and R38 in sequence. Terminal 1 of transistor Q4 is connected to terminal 2 of transistor Q4 via resistor R4. Terminal 2 of transistor Q4 is connected to the 24Vin power supply via resistor R39. Terminal 2 of transistor Q4 is connected to the 5V voltage terminal via resistor R23. The 5V voltage terminal is connected to the host transceiver circuit and terminal 3 of transistor Q4.

[0009] The first terminal of transistor Q3 is connected to the 485EN terminal through resistor R36, the first terminal of transistor Q3 is grounded through resistor R33, the second terminal of transistor Q3 is grounded, and the third terminal of transistor Q3 is connected to the first terminal of transistor Q4 through resistor R43.

[0010] The slave circuit includes:

[0011] The system includes a slave transceiver circuit, an energy storage circuit, a connector, a fuse F1, a Zener diode D1, and a 5V voltage terminal. The first pin of the connector is connected to the positive terminal of the Zener diode D1 and grounded. The second pin of the connector is connected to the 5V voltage terminal through the fuse F1. The negative terminal of the Zener diode D1 is connected to the 5V voltage terminal. The 5V voltage terminal is connected to the slave transceiver circuit and the energy storage circuit.

[0012] Furthermore, the main circuit also includes: fuse F2, and the third terminal of transistor Q4 is connected to the 5V voltage terminal through fuse F2.

[0013] Furthermore, the main circuit also includes: Zener diode D4, with the negative terminal of Zener diode D4 connected to the 5V voltage terminal and the positive terminal of Zener diode D4 grounded.

[0014] Furthermore, the host transceiver circuit includes: transistors Q1, Q2, Q6, and Q7; resistors R3, R5, R27, R29, R34, R37, R40, R44, R45, R46, and R47; and diode D5.

[0015] The first terminal of transistor Q1 is connected to the TXD terminal of the host microcontroller through resistor R5. The first terminal of transistor Q1 is connected to the second terminal of transistor Q1 through resistor R34. The second terminal of transistor Q1 is connected to the 3.3V voltage terminal through resistor R3. The 3.3V voltage terminal is connected to the TXD terminal of the host microcontroller through resistor R29.

[0016] The third terminal of transistor Q1 is connected to the first terminal of transistor Q2 through resistor R37. The first terminal of transistor Q2 is connected to the second terminal of transistor Q2 through resistor R40 and grounded. The third terminal of transistor Q2 is connected to the 5V voltage terminal.

[0017] The third terminal of transistor Q7 is connected to the first terminal of transistor Q6 through resistor R45. The third terminal of transistor Q6 is connected to the RXD terminal of the microcontroller of the host computer. The RXD terminal of the microcontroller of the host computer is connected to the 3.3V voltage terminal through resistor R27. The second terminal of transistor Q6 is grounded.

[0018] The second terminal of transistor Q7 is connected to the 3.3V voltage terminal. The second terminal of transistor Q7 is connected to the positive terminal of diode D5 through resistor R47. The negative terminal of diode D5 is connected to the 5V voltage terminal. The negative terminal of diode D5 is connected to the RXD terminal of the microcontroller of the host through resistor R44.

[0019] Terminal 1 of transistor Q7 is connected to the positive terminal of diode D5 through resistor R46.

[0020] Furthermore, the energy storage circuit includes: resistor R4, diode D2, capacitor C2, capacitor C3, and capacitor C4. The positive terminal of diode D2 is connected to the 5V voltage terminal through resistor R4, and the negative terminal of diode D2 is connected to the VDD voltage terminal. The positive terminals of capacitors C2, C3, and C4 are connected to the VDD voltage terminal, and the negative terminals of capacitors C2, C3, and C4 are grounded.

[0021] Furthermore, the energy storage circuit also includes: capacitor C1, with the first end of capacitor C1 connected to the VDD voltage terminal and the second end of capacitor C1 grounded.

[0022] Furthermore, the slave transceiver circuit includes: transistor Q2, transistor Q3, resistors R2, R3, R5, R6, R7, and diode D3. The first terminal of transistor Q2 is connected to the TXD terminal of the slave microcontroller through resistor R5, the second terminal of transistor Q2 is connected to the 5V voltage terminal through resistor R2, and the first terminal of transistor Q2 is connected to the second terminal of transistor Q2 through resistor R3.

[0023] The third terminal of transistor Q2 is connected to the first terminal of transistor Q3 through resistor R6. The first terminal of transistor Q3 is grounded through resistor R7. The second terminal of transistor Q3 is grounded. The third terminal of transistor Q3 is connected to the 5V voltage terminal. The positive terminal of diode D3 is connected to the RXD terminal of the slave microcontroller. The negative terminal of diode D3 is connected to the 5V voltage terminal.

[0024] The beneficial effects of this utility model are as follows:

[0025] The host circuit of this invention includes a host transceiver circuit, transistors Q3 and Q4, etc. Transistor Q4 is connected to different voltage terminals through multiple resistors to provide power; while transistor Q3 is connected to the 485EN terminal through a resistor to provide communication control. Transistors Q3 and Q4, etc., implement hardware interlock protection for communication and power supply. The slave circuit includes a slave transceiver circuit, an energy storage circuit, etc., and connectors and Zener diode D1, etc., working together to provide power supply and communication functions for the slave. Specifically, the host supplies power to the bus when idle, waiting for slave communication; when the host initiates communication, it cuts off the bus power supply, waiting for the slave to reply; the slave replies promptly upon receiving the signal, relying on the energy storage circuit to maintain operation without needing bus power. In other words, the slave and host of this system share the bus, reducing the use of power lines, saving power line resources, and lowering system costs. Attached Figure Description

[0026] Figure 1 This is the circuit diagram of the host circuit of this utility model.

[0027] Figure 2 This is the circuit diagram of the slave circuit of this utility model. Detailed Implementation

[0028] Please see Figure 1 and 2 As shown, this utility model relates to a communication and power supply co-line interlocking protection system, comprising: a master circuit, a slave circuit, and a 485 bus. The master circuit is connected to the slave circuit via the 485 bus.

[0029] The host circuit includes:

[0030] The main unit transceiver circuit includes transistors Q3 and Q4, resistors R23, R33, R36, R38, R39, and R4.

[0031] Terminal 1 of transistor Q4 is connected to the +5V voltage terminal via resistors R4 and R38 in sequence. Terminal 1 of transistor Q4 is connected to terminal 2 of transistor Q4 via resistor R4. Terminal 2 of transistor Q4 is connected to the 24Vin power supply via resistor R39. Terminal 2 of transistor Q4 is connected to the 5V voltage terminal via resistor R23. The 5V voltage terminal is connected to the host transceiver circuit and terminal 3 of transistor Q4.

[0032] The first terminal of transistor Q3 is connected to the 485EN terminal through resistor R36, the first terminal of transistor Q3 is grounded through resistor R33, the second terminal of transistor Q3 is grounded, and the third terminal of transistor Q3 is connected to the first terminal of transistor Q4 through resistor R43.

[0033] The slave circuit includes:

[0034] The system includes a slave transceiver circuit, an energy storage circuit, a connector CN1, a fuse F1, a Zener diode D1, and a 5V voltage terminal. The first pin of the connector CN1 is connected to the positive terminal of the Zener diode D1 and grounded. The second pin of the connector CN1 is connected to the 5V voltage terminal through the fuse F1. The negative terminal of the Zener diode D1 is connected to the 5V voltage terminal. The 5V voltage terminal is connected to the slave transceiver circuit and the energy storage circuit.

[0035] In the above scheme, the master circuit includes a master transceiver circuit, transistors Q3 and Q4, etc. Transistor Q4 is connected to different voltage terminals through multiple resistors to provide power; while transistor Q3 is connected to the 485EN terminal through a resistor to provide communication control. Transistors Q3 and Q4, etc., implement hardware interlock protection for communication and power supply. The slave circuit includes a slave transceiver circuit, an energy storage circuit, etc., and connector CN1 and Zener diode D1 work together to provide power supply and communication functions for the slave. Specifically, the master supplies power to the bus when idle, waiting for slave communication; when the master initiates communication, it cuts off the bus power supply and waits for the slave's response; the slave responds promptly upon receiving the signal, relying on the energy storage circuit to maintain operation without needing bus power. In other words, the slave and master of this system share the bus, reducing the use of power lines, saving power line resources, and lowering system costs.

[0036] Furthermore, the main circuit also includes: fuse F2, and the third terminal of transistor Q4 is connected to the 5V voltage terminal through fuse F2. The addition of fuse F2, transistor Q4, and related resistors to the main circuit protects it from damage when the main circuit is short-circuited. Resistors R4 and R38 connect the +5V voltage to the first terminal of transistor Q4, and fuse F2 blows.

[0037] Furthermore, the main circuit also includes a Zener diode D4, with its negative terminal connected to the 5V voltage terminal and its positive terminal grounded. Zener diode D4 plays a role in stabilizing the voltage in this main circuit, ensuring the stable voltage required for the normal operation of other components. Through its reverse breakdown characteristic, it automatically adjusts the voltage according to load changes, keeping the output stable at a preset value.

[0038] Furthermore, the host transceiver circuit includes: transistors Q1, Q2, Q6, and Q7; resistors R3, R5, R27, R29, R34, R37, R40, R44, R45, R46, and R47; and diode D5.

[0039] The first terminal of transistor Q1 is connected to the TXD terminal of the host microcontroller through resistor R5. The first terminal of transistor Q1 is connected to the second terminal of transistor Q1 through resistor R34. The second terminal of transistor Q1 is connected to the 3.3V voltage terminal through resistor R3. The 3.3V voltage terminal is connected to the TXD terminal of the host microcontroller through resistor R29.

[0040] The third terminal of transistor Q1 is connected to the first terminal of transistor Q2 through resistor R37. The first terminal of transistor Q2 is connected to the second terminal of transistor Q2 through resistor R40 and grounded. The third terminal of transistor Q2 is connected to the 5V voltage terminal.

[0041] The third terminal of transistor Q7 is connected to the first terminal of transistor Q6 through resistor R45. The third terminal of transistor Q6 is connected to the RXD terminal of the microcontroller of the host computer. The RXD terminal of the microcontroller of the host computer is connected to the 3.3V voltage terminal through resistor R27. The second terminal of transistor Q6 is grounded.

[0042] The second terminal of transistor Q7 is connected to the 3.3V voltage terminal. The second terminal of transistor Q7 is connected to the positive terminal of diode D5 through resistor R47. The negative terminal of diode D5 is connected to the 5V voltage terminal. The negative terminal of diode D5 is connected to the RXD terminal of the microcontroller of the host through resistor R44.

[0043] Terminal 1 of transistor Q7 is connected to the positive terminal of diode D5 through resistor R46.

[0044] This host transceiver circuit enables serial communication between the microcontroller and the host computer through a combination of transistors and other components. Its main functions include data transmission, data reception, level conversion, and signal amplification to ensure reliable data transmission.

[0045] Further, the energy storage circuit includes: resistor R4, diode D2, capacitor C2, capacitor C3, and capacitor C4. The anode of diode D2 is connected to the 5V voltage terminal through resistor R4, and the cathode of diode D2 is connected to the VDD voltage terminal. The anodes of capacitors C2, C3, and C4 are connected to the VDD voltage terminal, and the cathodes of capacitors C2, C3, and C4 are grounded. Further, the energy storage circuit also includes: capacitor C1. The first terminal of capacitor C1 is connected to the VDD voltage terminal, and the second terminal of capacitor C1 is grounded. Further, the slave circuit also includes: transistor Q1 and resistor R1. The first terminal of transistor Q1 is grounded through resistor R1, the second terminal of transistor Q1 is connected to the 5V voltage terminal and the first terminal of resistor R4, the anode of diode D2 is connected to the second terminal of resistor R4, and the cathode of diode D2 is connected to the VDD voltage terminal and the third terminal of transistor Q1. In this circuit, the energy storage section includes resistor R4, diode D2, and capacitors C2, C3, and C4. The positive terminals of capacitors C2, C3, and C4 are all connected to the VDD voltage terminal, and their negative terminals are grounded, forming a capacitor network for energy storage. A charging circuit is created through resistor R4 and diode D2, gradually charging capacitors C2, C3, and C4 and storing energy. The slave circuit also includes transistor Q1 and resistor R1. Terminal 1 of transistor Q1 is grounded through resistor R1, and terminal 2 is connected to the 5V voltage terminal and resistor R4, enabling control of the energy storage circuit. This circuit, through the combination of energy storage capacitors and the slave control section, achieves control over the storage and release of energy.

[0046] Furthermore, the slave transceiver circuit includes: transistors Q2 and Q3, resistors R2, R3, R5, R6, and R7, and diode D3. Terminal 1 of transistor Q2 is connected to the TXD terminal of the slave microcontroller via resistor R5; terminal 2 of transistor Q2 is connected to a 5V voltage terminal via resistor R2; terminal 1 of transistor Q2 is connected to terminal 2 of transistor Q2 via resistor R3; terminal 3 of transistor Q2 is connected to terminal 1 of transistor Q3 via resistor R6; terminal 1 of transistor Q3 is grounded via resistor R7; terminal 2 of transistor Q3 is grounded; and terminal 3 of transistor Q3 is connected to the 5V voltage terminal. The anode of diode D3 is connected to the RXD terminal of the slave microcontroller, and the cathode of diode D3 is connected to the 5V voltage terminal. This slave transceiver circuit, through the combination of transistors, resistors, and diodes, realizes the data transmission and reception functions in the slave system. By controlling the conduction and cutoff of transistors, and utilizing the characteristics of resistors and diodes, data signals are transmitted to the host device or received from the host device.

[0047] It should be noted that the 485EN pin refers to the enable pin of the RS485 bus, used to control the transmission and reception functions of the RS485 bus; the TXD pin refers to the transmitter pin, used for transmitting data; and the RXD pin refers to the receiver pin, used for receiving data. These three terms are commonly used in serial communication to describe the different roles and functions of data transmission.

[0048] It should be emphasized that the microcontroller described in this utility model can be a 51 series microcontroller.

[0049] Compared with the prior art, the present invention has the following technical effects:

[0050] 1. The system adopts a simplex communication mode, which realizes data transmission between the slave and master machines, reduces the complexity of communication, and improves system stability.

[0051] 2. The communication and power supply functions in the system are interconnected and interlocked through hardware protection, which ensures the normal operation of communication and power supply and improves the safety and reliability of the system.

[0052] 3. The system is designed with a host short-circuit protection function. Once a host short circuit occurs, the system can respond in time to avoid damage to the host or other components.

[0053] 4. The slave device communicates with the master device and shares power supply via the bus, which saves power line resources, simplifies the system structure, and reduces system costs.

[0054] 5. The system adopts an asynchronous mechanism to realize communication and power supply control, effectively utilizing two lines to process communication and power supply in a time-sharing manner, thereby improving the system's efficiency and flexibility.

[0055] 6. When the master stops supplying power to the bus, the slave device can continue to operate for a period of time by relying on the energy stored in the energy storage circuit, ensuring that the system can operate normally in the event of a sudden power outage.

[0056] In summary, this communication and power supply co-line interlocking protection system effectively improves the system's stability, security, and reliability while reducing system costs. It is suitable for applications requiring both communication and power supply capabilities, such as wired communication between an electric valve and a temperature control panel. In some embodiments, the master circuit is connected to the temperature control panel, and the slave circuit is connected to the electric valve, enabling communication and power supply between the electric valve and the temperature control panel via two buses, eliminating the need for an additional power supply line.

[0057] The above embodiments are merely preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Various modifications and improvements made to the technical solutions of the present utility model by those skilled in the art without departing from the spirit of the present utility model should fall within the protection scope defined by the claims of the present utility model.

Claims

1. A communication and power supply co-line interlocking protection system, characterized in that, It includes: a master circuit, a slave circuit, and a 485 bus. The master circuit is connected to the slave circuit via the 485 bus. The host circuit includes: The main unit transceiver circuit includes transistors Q3 and Q4, resistors R23, R33, R36, R38, R39, and R4. Terminal 1 of transistor Q4 is connected to the +5V voltage terminal via resistors R4 and R38 in sequence. Terminal 1 of transistor Q4 is connected to terminal 2 of transistor Q4 via resistor R4. Terminal 2 of transistor Q4 is connected to the 24Vin power supply via resistor R39. Terminal 2 of transistor Q4 is connected to the 5V voltage terminal via resistor R23. The 5V voltage terminal is connected to the host transceiver circuit and terminal 3 of transistor Q4. The first terminal of transistor Q3 is connected to the 485EN terminal through resistor R36, the first terminal of transistor Q3 is grounded through resistor R33, the second terminal of transistor Q3 is grounded, and the third terminal of transistor Q3 is connected to the first terminal of transistor Q4 through resistor R43. The slave circuit includes: The system includes a slave transceiver circuit, an energy storage circuit, a connector, a fuse F1, a Zener diode D1, and a 5V voltage terminal. The first pin of the connector is connected to the positive terminal of the Zener diode D1 and grounded. The second pin of the connector is connected to the 5V voltage terminal through the fuse F1. The negative terminal of the Zener diode D1 is connected to the 5V voltage terminal. The 5V voltage terminal is connected to the slave transceiver circuit and the energy storage circuit.

2. The communication and power supply co-line interlocking protection system according to claim 1, characterized in that, The main circuit also includes: fuse F2, and the third terminal of transistor Q4 is connected to the 5V voltage terminal through fuse F2.

3. The communication and power supply co-line interlocking protection system according to claim 1, characterized in that, The main circuit also includes: Zener diode D4, with the negative terminal of Zener diode D4 connected to the 5V voltage terminal and the positive terminal of Zener diode D4 grounded.

4. The communication and power supply co-line interlocking protection system according to claim 1, characterized in that, The host transceiver circuit includes: transistors Q1, Q2, Q6, and Q7; resistors R3, R5, R27, R29, R34, R37, R40, R44, R45, R46, and R47; and diode D5. The first terminal of transistor Q1 is connected to the TXD terminal of the host microcontroller through resistor R5. The first terminal of transistor Q1 is connected to the second terminal of transistor Q1 through resistor R34. The second terminal of transistor Q1 is connected to the 3.3V voltage terminal through resistor R3. The 3.3V voltage terminal is connected to the TXD terminal of the host microcontroller through resistor R29. The third terminal of transistor Q1 is connected to the first terminal of transistor Q2 through resistor R37. The first terminal of transistor Q2 is connected to the second terminal of transistor Q2 through resistor R40 and grounded. The third terminal of transistor Q2 is connected to the 5V voltage terminal. The third terminal of transistor Q7 is connected to the first terminal of transistor Q6 through resistor R45. The third terminal of transistor Q6 is connected to the RXD terminal of the microcontroller of the host computer. The RXD terminal of the microcontroller of the host computer is connected to the 3.3V voltage terminal through resistor R27. The second terminal of transistor Q6 is grounded. The second terminal of transistor Q7 is connected to the 3.3V voltage terminal. The second terminal of transistor Q7 is connected to the positive terminal of diode D5 through resistor R47. The negative terminal of diode D5 is connected to the 5V voltage terminal. The negative terminal of diode D5 is connected to the RXD terminal of the microcontroller of the host through resistor R44. The first terminal of transistor Q7 is connected to the positive terminal of diode D5 through resistor R46.

5. The communication and power supply co-line interlocking protection system according to claim 1, characterized in that, The energy storage circuit includes: resistor R4, diode D2, capacitor C2, capacitor C3 and capacitor C4. The positive terminal of diode D2 is connected to the 5V voltage terminal through resistor R4, and the negative terminal of diode D2 is connected to the VDD voltage terminal. The positive terminals of capacitors C2, C3 and C4 are connected to the VDD voltage terminal, and the negative terminals of capacitors C2, C3 and C4 are grounded.

6. The communication and power supply co-line interlocking protection system according to claim 5, characterized in that, The energy storage circuit also includes: capacitor C1, with the first end of capacitor C1 connected to the VDD voltage terminal and the second end of capacitor C1 grounded.

7. The communication and power supply co-line interlocking protection system according to claim 1, characterized in that, The slave transceiver circuit includes: transistor Q2, transistor Q3, resistors R2, R3, R5, R6, R7 and diode D3. The first terminal of transistor Q2 is connected to the TXD terminal of the slave microcontroller through resistor R5, the second terminal of transistor Q2 is connected to the 5V voltage terminal through resistor R2, and the first terminal of transistor Q2 is connected to the second terminal of transistor Q2 through resistor R3. The third terminal of transistor Q2 is connected to the first terminal of transistor Q3 through resistor R6. The first terminal of transistor Q3 is grounded through resistor R7. The second terminal of transistor Q3 is grounded. The third terminal of transistor Q3 is connected to the 5V voltage terminal. The positive terminal of diode D3 is connected to the RXD terminal of the slave microcontroller. The negative terminal of diode D3 is connected to the 5V voltage terminal.

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