Packaging structure and power module

Abstract

The utility model provides a packaging structure and a power module. The packaging structure comprises a packaging body, a first substrate, a second substrate, a power chip and a temperature sensor, the first substrate, the second substrate, the power chip and the temperature sensor are located in the packaging body, the power chip is arranged on the first substrate, the temperature sensor is arranged on the second substrate, and the second substrate is connected to the first substrate. The temperature detection precision of the temperature sensor can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure and a power module. Background Technology

[0002] Packaging structures integrate power electronic devices together. Due to their advantages such as high integration and high reliability, packaging structures and power modules have been widely used in electric vehicles, photovoltaic power generation, wind power generation, industrial frequency conversion, and other fields. With the rapid development and popularization of new energy vehicles, it is necessary to develop packaging structures with higher reliability, higher heat dissipation capacity, and higher power density to meet market demands.

[0003] Existing compact packaging structures, due to their size limitations, require the chip to occupy a large area of ​​the metal layer on the ceramic substrate surface, making it impossible to integrate a temperature sensor within the package structure. Some current solutions involve attaching the temperature sensor to the surface of the package body; however, because the temperature sensor is located outside the package body, its temperature detection accuracy is relatively low. Utility Model Content

[0004] The purpose of this application is to provide a packaging structure and power module that can improve the temperature detection accuracy of a temperature sensor.

[0005] One aspect of this application provides a packaging structure. The packaging structure includes a package body and a first substrate, a second substrate, a power chip, and a temperature sensor located inside the package body, wherein the power chip is disposed on the first substrate, the temperature sensor is disposed on the second substrate, and the second substrate is connected to the first substrate.

[0006] Further, the first substrate includes a first upper conductive layer, a first lower conductive layer, and a first intermediate insulating layer located between the first upper conductive layer and the first lower conductive layer, and the second substrate includes a second upper conductive layer, a second lower conductive layer, and a second intermediate insulating layer located between the second upper conductive layer and the second lower conductive layer, wherein the back side of the temperature sensor is electrically connected to the second upper conductive layer of the second substrate, and the second lower conductive layer of the second substrate is connected to the first upper conductive layer of the first substrate.

[0007] Furthermore, the packaging structure also includes a first signal terminal and a second signal terminal, wherein the first signal terminal is electrically connected to the front side of the temperature sensor via a first wire, and the second signal terminal is electrically connected to the second upper conductive layer of the second substrate via a second wire.

[0008] Furthermore, the packaging structure also includes a first power terminal and a second power terminal. The first power terminal is electrically connected to a first electrode on the front side of the power chip, and the back side of the power chip is electrically connected to the first upper conductive layer of the first substrate as a second electrode. The second power terminal is electrically connected to the first upper conductive layer of the first substrate.

[0009] Furthermore, the second power terminal, the first signal terminal, and the second signal terminal are all located on the first side of the package, and the package has a creepage groove on the first side, wherein the second power terminal is located on one side of the creepage groove, and the first signal terminal and the second signal terminal are located on the opposite side of the creepage groove.

[0010] Furthermore, the packaging structure also includes a third signal terminal and a fourth signal terminal, wherein the third signal terminal is electrically connected to the control electrode on the front side of the power chip via a third wire; and the fourth signal terminal is electrically connected to the first power terminal and integrally formed with the first power terminal.

[0011] Furthermore, the first power terminal, the third signal terminal, and the fourth signal terminal are all located on the second side of the package, which is opposite to the first side.

[0012] Furthermore, the power chip includes a MOSFET, the package structure includes two MOSFETs, the first upper conductive layer of the first substrate includes a first conductive region and a second conductive region, the back sides of the two MOSFETs are connected to the first conductive region, the control electrodes on the front sides of the two MOSFETs are electrically connected to the second conductive region through corresponding third wires, and the third signal terminal is electrically connected to the second conductive region.

[0013] Furthermore, the power chip includes an IGBT, and the package structure further includes a diode located inside the package body. The back side of the diode is electrically connected to the first upper conductive layer of the first substrate, and the front side of the diode is electrically connected to the first power terminal.

[0014] Another aspect of this application provides a power module. The power module includes a main substrate and a plurality of packaging structures as described above, wherein the plurality of packaging structures are disposed on the main substrate.

[0015] The packaging structure and power module of one or more embodiments of this application add a second substrate, electrically connect the temperature sensor to the second substrate, and further connect the second substrate to the first substrate. Thus, the temperature sensor is indirectly disposed on the first substrate through the second substrate, and insulation between the temperature sensor and the first substrate is achieved, so that the temperature sensor can be directly disposed inside the package. This effectively solves the problem that the temperature sensor cannot be directly disposed on the first substrate due to insufficient insulation space on the first substrate after the power chip is disposed on the first substrate.

[0016] Furthermore, by adding a second substrate, the packaging structure of this application allows the temperature sensor to be directly placed inside the package. Since the temperature sensor is closer to the power chip, the temperature detection accuracy of the temperature sensor can be improved. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall packaging structure of one embodiment of this application.

[0018] Figure 2 for Figure 1 The top view of the packaging structure shown.

[0019] Figure 3 This is a schematic diagram of the packaging structure before packaging, according to one embodiment of this application.

[0020] Figure 4 for Figure 3 The top view of the packaging structure shown.

[0021] Figure 5 for Figure 3 The diagram shows a partial exploded view of the packaging structure.

[0022] Figure 6 A circuit diagram illustrating the packaging structure of one embodiment of this application is shown.

[0023] Figure 7 This is a partially enlarged schematic diagram of the packaging structure of one embodiment of this application before packaging.

[0024] Figure 8 This is a schematic diagram of the packaging structure before packaging, which is another embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0026] The packaging structure and power module of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Figure 1 and Figure 2 This application discloses a schematic diagram of the package structure 100 after packaging according to one embodiment of the present application. Figures 3 to 5 This document illustrates a schematic diagram of the packaging structure 100 of one embodiment of this application before packaging. (Refer to...) Figures 1 to 5 As shown, a packaging structure 100 according to one embodiment of this application includes a package body 101 and a first substrate 110, a second substrate 120, a power chip 130, and a temperature sensor 140 located inside the package body 101. The package body 101 can completely enclose the first substrate 110, the second substrate 120, the power chip 130, and the temperature sensor 140 inside it.

[0028] The power chip 130 is disposed on the first substrate 110. Figure 6 A circuit diagram of a package structure 100 according to one embodiment of this application is shown. (Referring to...) Figure 6 As shown, in one embodiment of this application, the power chip 130 may include, for example, an IGBT (Insulated Gate Bipolar Transistor) Q.

[0029] Temperature sensor 140 is disposed on the second substrate 120 and can be used to detect the overall temperature of power chip 130. For example... Figure 6 As shown, the temperature sensor 140 may include a thermistor R, which may include, for example, an NTC (Negative Temperature Coefficient) thermistor.

[0030] The second substrate 120 is connected to the first substrate 110. Thus, by means of the second substrate 120, the temperature sensor 140 can be indirectly disposed on the first substrate 110 and is insulated from the first substrate 110.

[0031] The packaging structure 100 of this application adds a second substrate 120, electrically connects the temperature sensor 140 to the second substrate 120, and further connects the second substrate 120 to the first substrate 110. Thus, the temperature sensor 140 is indirectly disposed on the first substrate 110 through the second substrate 120, and insulation between the temperature sensor 140 and the first substrate 110 is achieved, so that the temperature sensor 140 can be directly disposed inside the package 101. This effectively solves the problem that the temperature sensor 140 cannot be directly disposed on the first substrate 110 due to insufficient insulation space on the first substrate 110 after the power chip 130 is disposed on the first substrate 110.

[0032] Furthermore, by adding a second substrate 120, the packaging structure 100 of this application can directly place the temperature sensor 140 inside the package 101. Since the temperature sensor 140 is closer to the power chip 130, the temperature detection accuracy of the temperature sensor 140 can be improved.

[0033] Figure 7 This illustration shows a partially enlarged view of the packaging structure 100 of one embodiment of this application before packaging. (Refer to...) Figure 7 In some embodiments, the first substrate 110 includes a first upper conductive layer 111, a first lower conductive layer 112, and a first intermediate insulating layer 113 located between the first upper conductive layer 111 and the first lower conductive layer 112; the second substrate 120 includes a second upper conductive layer 121, a second lower conductive layer 122, and a second intermediate insulating layer 123 located between the second upper conductive layer 121 and the second lower conductive layer 122.

[0034] The first substrate 110 and the second substrate 120 may include, but are not limited to, ceramic substrates. The first upper conductive layer 111 and the first lower conductive layer 112 of the first substrate 110, and the second upper conductive layer 121 and the second lower conductive layer 122 of the second substrate 120 may be copper layers, and the first intermediate insulating layer 113 of the first substrate 110 and the second intermediate insulating layer 123 of the second substrate 120 may be ceramic layers.

[0035] The back side of the temperature sensor 140 is electrically connected to the second upper conductive layer 121 of the second substrate 120, and the second lower conductive layer 122 of the second substrate 120 is connected to the first upper conductive layer 111 of the first substrate 110. Through the second intermediate insulating layer 123 between the second upper conductive layer 121 and the second lower conductive layer 122 of the second substrate 120, the temperature sensor 140 disposed on the second upper conductive layer 121 of the second substrate 120 is insulated from the second lower conductive layer 122 of the second substrate 120, and consequently, from the first upper conductive layer 111 of the first substrate 110. This achieves insulation between the temperature sensor 140 and the first substrate 110, effectively solving the problem that the temperature sensor 140 could not be directly disposed on the first substrate 110 due to insufficient insulation space after the power chip 130 was disposed on the first substrate 110. This allows for the placement of a temperature sensor within this compact package structure.

[0036] like Figures 3 to 5 As shown, the packaging structure 100 of this application further includes a first signal terminal 151 and a second signal terminal 152. The first signal terminal 151 can be electrically connected to the front side of the temperature sensor 140 via a first wire 171, and the second signal terminal 152 can be electrically connected to the second upper conductive layer 121 of the second substrate 120 via a second wire 172.

[0037] The package structure 100 of this application further includes a first power terminal 161 and a second power terminal 162. The first power terminal 161 is electrically connected to a first electrode on the front side of the power chip 130, and the back side of the power chip 130 serves as a second electrode and is electrically connected to a first upper conductive layer 111 of the first substrate 110; the second power terminal 162 is electrically connected to the first upper conductive layer 111 of the first substrate 110. (Refer to reference...) Figure 6 When the power chip 130 is an IGBT Q, the first electrode of the power chip 130 is the emitter E of the IGBT Q, and the second electrode of the power chip 130 is the collector C of the IGBT Q. Therefore, the first power terminal 161 is electrically connected to the emitter E of the IGBT Q, and the second power terminal 162 is electrically connected to the collector C of the IGBT Q.

[0038] The package structure 100 of this application further includes a third signal terminal 153, wherein the third signal terminal 153 can be electrically connected to the control electrode on the front side of the power chip 130 via a third wire 173. (Refer to reference...) Figure 6 When the power chip 130 is an IGBT Q, the control electrode of the power chip 130 is the gate G of the IGBT Q. Therefore, the third signal terminal 153 is electrically connected to the gate G of the IGBT Q.

[0039] The front side of the temperature sensor 140 of this application can serve as the first pin T1, which is electrically connected to the first signal terminal 151 via the first wire 171. The back side of the temperature sensor 140 is electrically connected to the second upper conductive layer 121 of the second substrate 120. Therefore, the second upper conductive layer 121 of the second substrate 120 can serve as the second pin T2 of the temperature sensor 140, which is electrically connected to the second signal terminal 152 via the second wire 172. Thus, the first pin T1 and the second pin T2 of the temperature sensor 140 of this application can be in the same lead frame as other terminals, and be shaped by cutting the lead wire, thereby improving the assembly accuracy of the temperature sensor 140.

[0040] Furthermore, the temperature sensor 140 of this application is located inside the package 101. After plastic encapsulation, the connection points of the first pin T1 and the second pin T2 of the temperature sensor 140 with the first signal terminal 151 and the second signal terminal 152 are all inside the package 101. Therefore, it has sufficient mechanical strength and there is no risk of detachment, thus ensuring the reliability of the connection.

[0041] Optionally, the packaging structure 100 of this application may further include a fourth signal terminal 154. The fourth signal terminal 154 is electrically connected to and integrally formed with the first power terminal 161. That is, the fourth signal terminal 154 is formed as a branch extending outward from one side of the first power terminal 161. The fourth signal terminal 154 is also electrically connected to the emitter E of the IGBT Q, and the third signal terminal 153 and the fourth signal terminal 154 form a drive circuit.

[0042] like Figure 1 and Figure 2 As shown, after encapsulation, at least a portion of each of the first power terminal 161, the second power terminal 162, the first signal terminal, the second signal terminal 152, the third signal terminal 153, and the fourth signal terminal 154 is exposed outside the package 101.

[0043] Package 101 includes a first side and a second side opposite to each other. In some embodiments, the second power terminal 162, the first signal terminal 151, and the second signal terminal 152 are all located on the first side of package 101. A creepage groove 1011 is formed on the first side of package 101, wherein the second power terminal 162 is located on one side of creepage groove 1011, and the first signal terminal 151 and the second signal terminal 152 are located on the opposite side of creepage groove 1011.

[0044] The packaging structure 100 of this application increases the creepage distance between the first signal terminal 151, the second signal terminal 152 and the second power terminal 162 by opening a creepage groove 1011 on the first side of the package body 101, thereby ensuring electrical safety.

[0045] Optionally, the first power terminal 161, the third signal terminal 153, and the fourth signal terminal 154 are all located on the second side of the package 101.

[0046] Continue to refer to Figures 3 to 5 In some embodiments, the package structure 100 of this application further includes a diode D located inside the package body 101. The diode D is, for example, a fast recovery diode (FRD). The back side of the diode D is electrically connected to the first upper conductive layer 111 of the first substrate 110, and the front side of the diode D is electrically connected to the first power terminal 161.

[0047] Figure 8 This illustration shows a schematic diagram of the packaging structure 200 before packaging, according to another embodiment of this application. Figure 8 As shown, with Figures 3 to 5 The difference lies in another embodiment of this application, where the power chip 130 may include, for example, a MOSFET M (Metal-Oxide-Semiconductor Field-Effect Transistor). Optionally, the MOSFET M is a SiC (silicon carbide) MOSFET.

[0048] When the power chip 130 is a MOSFET M, the first electrode of the power chip 130 is the source of the MOSFET M, and the second electrode of the power chip 130 is the drain of the MOSFET M. Therefore, the first power terminal 161 is electrically connected to the source of the MOSFET M, and the second power terminal 162 is electrically connected to the drain of the MOSFET M. The control electrode of the power chip 130 is the gate G of the MOSFET M. Therefore, the third signal terminal 153 is electrically connected to the gate G of the MOSFET M.

[0049] Optionally, the packaging structure 100 of this application includes two MOS transistors M, both of which are disposed on the first substrate 110.

[0050] The first upper conductive layer 111 of the first substrate 110 includes a first conductive region 1111 and a second conductive region 1112 that are isolated from each other. The back sides of the two MOSFETs M are connected to the first conductive region 1111 as drains. The control electrodes (i.e., gates G) on the front sides of the two MOSFETs M are electrically connected to the second conductive region 1112 through corresponding third wires 173. The third signal terminal 153 is electrically connected to the second conductive region 1112. Thus, the gates G of the two MOSFETs M are electrically connected to the third conductive terminal 153 through the second conductive region 1112.

[0051] Figure 8 The packaging structure 200 shown can also have the same Figures 3 to 5 The beneficial technical effects are generally similar to those of the packaging structure 100 shown.

[0052] This application also provides a power module. The power module includes a main substrate (not shown) and multiple packaging structures 100 / 200 as described in the above embodiments. The multiple packaging structures 100 / 200 are disposed on the main substrate.

[0053] The power module of this application has beneficial technical effects that are generally similar to the packaging structure 100 / 200 described above, so it will not be described again here.

[0054] The packaging structure and power module provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the packaging structure and power module of the embodiments of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A packaging structure, characterized in that, The package includes a package body and a first substrate, a second substrate, a power chip, and a temperature sensor located inside the package body. The power chip is disposed on the first substrate, the temperature sensor is disposed on the second substrate, and the second substrate is connected to the first substrate. The first substrate includes a first upper conductive layer, a first lower conductive layer, and a first intermediate insulating layer located between the first upper conductive layer and the first lower conductive layer. The second substrate includes a second upper conductive layer, a second lower conductive layer, and a second intermediate insulating layer located between the second upper conductive layer and the second lower conductive layer. The back side of the temperature sensor is electrically connected to the second upper conductive layer of the second substrate, and the second lower conductive layer of the second substrate is connected to the first upper conductive layer of the first substrate.

2. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes a first signal terminal and a second signal terminal, wherein the first signal terminal is electrically connected to the front side of the temperature sensor via a first wire, and the second signal terminal is electrically connected to the second upper conductive layer of the second substrate via a second wire.

3. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes a first power terminal and a second power terminal. The first power terminal is electrically connected to a first electrode on the front side of the power chip, and the back side of the power chip is electrically connected to the first upper conductive layer of the first substrate as a second electrode. The second power terminal is electrically connected to the first upper conductive layer of the first substrate.

4. The packaging structure as described in claim 3, characterized in that, The second power terminal, the first signal terminal, and the second signal terminal are all located on the first side of the package. The package has a creepage groove on the first side, wherein the second power terminal is located on one side of the creepage groove, and the first signal terminal and the second signal terminal are located on the opposite side of the creepage groove.

5. The packaging structure as described in claim 4, characterized in that, The packaging structure further includes a third signal terminal and a fourth signal terminal, wherein the third signal terminal is electrically connected to the control electrode on the front side of the power chip via a third wire; the fourth signal terminal is electrically connected to the first power terminal and is integrally formed with the first power terminal.

6. The packaging structure as described in claim 5, characterized in that, The first power terminal, the third signal terminal, and the fourth signal terminal are all located on the second side of the package, which is opposite to the first side.

7. The packaging structure as described in claim 5, characterized in that, The power chip includes a MOSFET, the package structure includes two MOSFETs, the first upper conductive layer of the first substrate includes a first conductive region and a second conductive region, the back sides of the two MOSFETs are connected to the first conductive region, the control electrodes on the front sides of the two MOSFETs are electrically connected to the second conductive region through corresponding third wires, and the third signal terminal is electrically connected to the second conductive region.

8. The packaging structure as described in claim 3, characterized in that, The power chip includes an IGBT, and the package structure also includes a diode located inside the package body. The back side of the diode is electrically connected to the first upper conductive layer of the first substrate, and the front side of the diode is electrically connected to the first power terminal.

9. A power module, characterized in that, It includes a main substrate and a plurality of packaging structures as described in any one of claims 1 to 8, wherein the plurality of packaging structures are disposed on the main substrate.

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