Controllable bidirectional transceiver circuit

Abstract

The utility model discloses a controllable bidirectional transceiving circuit, which comprises a data pulse transmitting end OUT1, a data pulse receiving end IN1, a master-slave machine control mode switching end IO1, a data pulse transmitting end OUT2, a data pulse receiving end IN2 and a master-slave machine control mode switching end IO2, the data pulse transmitting end OUT1 is sequentially connected with a zero-ohm resistor element R7 and a zero-ohm resistor element R34 and then is connected with a fourth interface of the relay K2, and a third interface of the relay K2 is connected with a diode D3. According to the utility model, logic components are added to control master-slave switching, the relay is controlled through the characteristics of the logic gate so as to determine the receiving and transmitting mode of pulse data, the defects that the host can only transmit and cannot receive and cannot display the detection result are overcome, both parties can check the data of a detection line, and the detection efficiency is improved. And the detected line conditions can be mutually verified at the same time, so that the line can be replaced and overhauled more quickly, and the working efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of long-distance signal transmission, specifically a controllable bidirectional transceiver circuit. Background Technology

[0002] In long-distance transmission, locations A and B are often designated as master and slave, respectively. In the detection circuit, the master at location A sends detection pulses, and the slave at location B calculates and records the detected line conditions based on the received pulses. This works fine for short distances, but in long-distance detection, the master at location A sends, and the slave at location B receives and displays. Due to the great distance, the master at location A cannot see the detection results. Therefore, a controllable bidirectional transceiver circuit can effectively solve this problem. Upon power-on, both devices default to slave mode. After either device presses a button to become the master, it begins sending data pulses. After sending its detection pulse, the master becomes the slave, and after receiving its pulse, the slave becomes the master and sends its own detection pulse. The slave receives the data and calculates the results. Both the master and slave devices can display the data, thus making the circuit's transmission and reception controllable and allowing for master / slave selection.

[0003] Existing technical solutions such as Figure 3 As shown, one side is defined as the master responsible for sending data, and the other side as the slave receiving data. While this fixed approach is simple and straightforward, it has certain drawbacks in long-distance multi-line detection due to its one-sided display. Furthermore, relying on the master to output one or more detection signals to the slave, and considering that line detection typically involves simultaneous detection of multiple lines, if the master and slave are fixed, when the slave receives detection data, if the distance is too great, only one side can receive and display the data; the other side cannot see it. When line maintenance requires simultaneous operation of both sides, the side receiving the data needs to communicate with the other, which increases costs and time. Therefore, those skilled in the art have provided a controllable bidirectional transceiver circuit to solve the problems mentioned in the background section. Utility Model Content

[0004] The purpose of this invention is to provide a controllable bidirectional transceiver circuit to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A controllable bidirectional transceiver circuit includes a data pulse transmitter OUT1, a data pulse receiver IN1, a master-slave mode switching terminal IO1, a data pulse transmitter OUT2, a data pulse receiver IN2, and a master-slave mode switching terminal IO2. The data pulse transmitter OUT1 is connected sequentially to zero-ohm resistors R7 and R34, and then to the fourth interface of relay K2. A diode D3 is connected to the third interface of relay K2, and a power supply P1 is connected to the second interface of diode D3. The master-slave mode switching terminal IO1 is connected to resistor R9, and then to the first interface of chip U1. The fourth interface of chip U1 is connected to the first interface of chip U2 and the relay. The first interface of K2 and the fourth interface of chip U2 are connected to the second interface of the relay. The second interface of relay K2 and the first interface of relay K1 are grounded. The fourth interface of relay K1 is connected to power supply P1. The data pulse receiving terminal IN1 is connected to capacitor C10 and then grounded. It is also connected to the second and third interfaces of chip U1 and the third interface of chip U2. The data pulse receiving terminal IN1 is also connected to the fourth interface of chip U16 and diode D8. The other end of diode D8 is connected to resistor R4. The first interface of chip U16 is connected to the second interface of diode D4 and resistor R11. Resistor R11 is connected to zero-ohm resistor R5 and then connected to the third interface of relay K1.

[0007] As a further embodiment of this utility model: the data pulse transmitting terminal OUT2 is connected to the zero-ohm resistor element R6 and the zero-ohm resistor element R2 in sequence, and then connected to the fourth interface of the relay K3. The third interface of the relay K3 is connected to the diode D5, the second interface of the diode D5 is connected to the power supply P2, and the master-slave mode switching terminal IO2 is connected to the resistor R8 and then connected to the first interface of the chip U4.

[0008] As a further embodiment of this utility model: the fourth interface of chip U4 is connected to the first interface of chip U5 and the first interface of relay K3, the fourth interface of chip U5 is connected to the second interface of relay, the second interface of relay K3 and the first interface of relay K4 are grounded, the fourth interface of relay K4 is connected to power supply P2, the data pulse receiving terminal IN2 is connected to capacitor C10 and then grounded, and is connected to the second and third interfaces of chip U4 and the third interface of chip U5.

[0009] As a further embodiment of this utility model: the data pulse receiving terminal IN2 is also connected to the fourth interface of chip U3 and diode D1. The other end of diode D1 is connected to resistor R1. The first interface of chip U3 is connected to the second interface of diode D2 and resistor R13. Resistor R13 is connected to the zero-ohm resistor element R3 and then connected to the third interface of relay K4.

[0010] As a further embodiment of this utility model: the second interface of chip U16 is connected to the first interface of diode D4, and then connected to the second interface of chip U3 and the first interface of diode D2.

[0011] This invention adds logic components to control the master-slave switching and uses the characteristics of logic gates to manipulate relays to determine the transmission and reception of pulse data. It also solves the shortcomings of the master only being able to send and not receive, and not being able to display the detection results. Both parties can view the data of the detection line and can simultaneously verify the detected line conditions, so as to replace and repair more quickly and improve work efficiency. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of this utility model;

[0013] Figure 2 This is a schematic diagram illustrating the working principle of this utility model;

[0014] Figure 3 This is a diagram of the existing technology structure. Detailed Implementation

[0015] Please see Figures 1-2 A controllable bidirectional transceiver circuit includes a data pulse transmitter OUT1, a data pulse receiver IN1, a master-slave mode switching terminal IO1, a data pulse transmitter OUT2, a data pulse receiver IN2, and a master-slave mode switching terminal IO2. The data pulse transmitter OUT1 is connected sequentially to zero-ohm resistors R7 and R34, and then to the fourth interface of relay K2. A diode D3 is connected to the third interface of relay K2, and a power supply P1 is connected to the second interface of diode D3. The master-slave mode switching terminal IO1 is connected to resistor R9, and then to the first interface of chip U1. The fourth interface of chip U1 is connected to the first interface of chip U2 and the relay. The first interface of device K2 and the fourth interface of chip U2 are connected to the second interface of relay. The second interface of relay K2 and the first interface of relay K1 are grounded. The fourth interface of relay K1 is connected to power supply P1. The data pulse receiving terminal IN1 is connected to capacitor C10 and then grounded. It is also connected to the second and third interfaces of chip U1 and the third interface of chip U2. The data pulse receiving terminal IN1 is also connected to the fourth interface of chip U16 and diode D8. The other end of diode D8 is connected to resistor R4. The first interface of chip U16 is connected to the second interface of diode D4 and resistor R11. Resistor R11 is connected to zero-ohm resistor R5 and then connected to the third interface of relay K1.

[0016] The data pulse transmitting terminal OUT2 is connected to zero-ohm resistors R6 and R2 in sequence, and then to the fourth interface of relay K3. The third interface of relay K3 is connected to diode D5, and the second interface of diode D5 is connected to power supply P2. The master-slave mode switching terminal IO2 is connected to resistor R8 and then to the first interface of chip U4. The fourth interface of chip U4 is connected to the first interface of chip U5 and the first interface of relay K3. The fourth interface of chip U5 is connected to the second interface of relay K3. The second interface of relay K3 and the first interface of relay K4 are grounded. The fourth interface of relay K4 is connected to power supply P2. The data pulse receiving terminal IN2 is connected to capacitor C10 and then to ground, and is connected to the second and third interfaces of chip U4 and the third interface of chip U5. The data pulse receiving terminal IN2 is also connected to the fourth interface of chip U3 and diode D1. The other end of diode D1 is connected to resistor R1. The first interface of chip U3 is connected to the second interface of diode D2 and resistor R13. Resistor R13 is connected to zero-ohm resistor R3 and then to the third interface of relay K4.

[0017] Among them, the second interface of chip U16 is connected to the first interface of diode D4, and then connected to the second interface of chip U3 and the first interface of diode D2.

[0018] After adopting the above technical solution, the master and slave modes are determined by controlling the high and low levels of the master-slave mode switching terminal IO1, thereby switching their receiving or transmitting states. After power-on, the master-slave mode switching terminal IO1 is at a low level, the OR gate output is at a low level, the NAND gate output is at a high level, and the relay K1 is closed, indicating that the slave is in the receiving state. When the microcontroller detects that a button is pressed, it controls the master-slave mode switching terminal IO1 to switch to a high level, the OR gate output is at a high level, the NAND gate output is at a low level, the relay K2 is closed, and the relay K1 is opened, switching to the master transmitting mode.

[0019] After the master mode finishes sending data, the control master-slave mode switching terminal IO1 goes low, the OR gate outputs a low level, the NAND gate outputs a high level, relay K2 opens, relay K1 closes, and the system switches back to slave standby mode, waiting for the next switch.

[0020] By switching between master and slave modes via I / O ports, data can be sent and received between two locations even over long distances. The data detected by both sides can be verified, reducing communication costs and improving work efficiency.

[0021] The working principle of this utility model is as follows: In the controllable bidirectional transceiver circuit, the default is slave receiving state. When the button is pressed, as shown in the figure above, the master-slave mode switching terminal IO1 is at a high level, and the relay K2 is energized, switching to master transmitting state. After transmitting, it switches to slave receiving state, and vice versa. By controlling the master-slave mode switching terminal IO1, the transmission and reception are reversed, and the master and slave are switched, which improves the flexibility of the circuit, saves the manual intervention required in the detection process, and improves the verification efficiency. By adding logic components to control the master-slave switching, and using the characteristics of logic gates to control the relay to determine the transmission and reception mode of pulse data, this invention solves the shortcomings of the master only being able to transmit and not receive, and not being able to display the detection results. Both sides can view the data of the detection line and can simultaneously verify the detected line conditions, so as to replace and repair more quickly and improve work efficiency.

[0022] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A controllable bidirectional transceiver circuit, comprising a data pulse transmitting terminal OUT1, a data pulse receiving terminal IN1, a master-slave mode switching terminal IO1, a data pulse transmitting terminal OUT2, a data pulse receiving terminal IN2, and a master-slave mode switching terminal IO2, characterized in that: The data pulse transmitting terminal OUT1 is connected in sequence to zero-ohm resistor R7 and zero-ohm resistor R34, and then connected to the fourth interface of relay K2. The third interface of relay K2 is connected to diode D3, and the second interface of diode D3 is connected to power supply P1. The master-slave mode switching terminal IO1 is connected to resistor R9 and then to the first interface of chip U1. The fourth interface of chip U1 is connected to the first interface of chip U2 and the first interface of relay K2. The fourth interface of chip U2 is connected to the second interface of relay K2. The second interface of relay K2 and the first interface of relay K1 are grounded. The fourth interface of relay K1 is connected to power supply P1. The data pulse receiving terminal IN1 is connected to capacitor C10 and then grounded. It is also connected to the second and third interfaces of chip U1 and the third interface of chip U2. The data pulse receiving terminal IN1 is also connected to the fourth interface of chip U16 and diode D8. The other end of diode D8 is connected to resistor R4. The first interface of chip U16 is connected to the second interface of diode D4 and resistor R11. Resistor R11 is connected to zero-ohm resistor R5 and then to the third interface of relay K1.

2. The controllable bidirectional transceiver circuit according to claim 1, characterized in that: The data pulse transmitting terminal OUT2 is connected in sequence to zero-ohm resistor R6 and zero-ohm resistor R2, and then connected to the fourth interface of relay K3. The third interface of relay K3 is connected to diode D5, and the second interface of diode D5 is connected to power supply P2. The master-slave mode switching terminal IO2 is connected to resistor R8 and then to the first interface of chip U4.

3. The controllable bidirectional transceiver circuit according to claim 2, characterized in that: The fourth interface of chip U4 is connected to the first interface of chip U5 and the first interface of relay K3. The fourth interface of chip U5 is connected to the second interface of relay K3. The second interface of relay K3 and the first interface of relay K4 are grounded. The fourth interface of relay K4 is connected to power supply P2. The data pulse receiving terminal IN2 is connected to capacitor C10 and then grounded, and is connected to the second and third interfaces of chip U4 and the third interface of chip U5.

4. A controllable bidirectional transceiver circuit according to claim 3, characterized in that: The data pulse receiving terminal IN2 is also connected to the fourth interface of chip U3 and diode D1. The other end of diode D1 is connected to resistor R1. The first interface of chip U3 is connected to the second interface of diode D2 and resistor R13. Resistor R13 is connected to the zero-ohm resistor element R3 and then connected to the third interface of relay K4.

5. A controllable bidirectional transceiver circuit according to claim 4, characterized in that: The second interface of chip U16 is connected to the first interface of diode D4, and then connected to the second interface of chip U3 and the first interface of diode D2.

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