Signal detection circuit supporting multiple SFP light sources

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By designing a signal detection circuit that supports multiple SFP light sources, the system realizes the transmission control and data return signal detection of multiple SFP optical modules, solving the problem that existing systems cannot support multiple optical modules, improving the stability and flexibility of the communication network, reducing operating costs, and providing real-time signal quality monitoring functions.

CN223514905UActive Publication Date: 2025-11-04DONGGUAN YAOYE AUTOMATION CO LTD

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Patent Information

Application Number: CN202423122395.0
Authority / Receiving Office: CN · China
Patent Type: Utility models(China)
Current Assignee / Owner
Filing Date: 2024-12-17
Publication Date: 2025-11-04
Estimated Expiration: 2034-12-17

AI Technical Summary

Technical Problem

Existing communication systems cannot effectively support the switching of transmissions and the detection of data return signals from multiple SFP optical modules, which limits the flexibility and scalability of the system and fails to meet the needs of modern communication networks for diverse and high-performance optical communication modules.

Method used

A signal detection circuit supporting multiple SFP light sources was designed, including a main control unit, an SFP optical module control unit, and a ROSA device return signal measurement unit. The optical module interface is switched through a multiplexer chip, the signal is converted by an analog-to-digital converter chip, the differential and common-mode data acquisition modules acquire the signal, and the main control unit processes and controls the signal.

Benefits of technology

It enables the transmission control and reception signal detection of multiple SFP optical modules, ensuring the stability and reliability of data transmission, improving communication network performance, reducing operating costs, enhancing system flexibility, and monitoring the quality of data return signals in real time, providing support for network optimization and maintenance.

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Abstract

The utility model relates to the technical field of SFP light source data detection, in particular to a signal detection circuit supporting multiple SFP light sources, which comprises a main control unit, an SFP optical module control unit and an ROSA device return signal measurement unit. The SFP optical module control unit comprises a multi-way switch chip U16, an indicating lamp module and a plurality of SFP optical module interfaces, the indicating lamp module and the plurality of SFP optical module interfaces are respectively connected with the multi-way switch chip U16, and the main control unit is respectively connected with the multi-way switch chip U16 and the plurality of SFP optical module interfaces. According to the utility model, the structure is novel, the sending control of a plurality of SFP optical modules and the detection of received data return signals are realized, and the stability and reliability of data transmission are ensured; by integrating an ROSA device return signal measurement unit, the circuit can monitor the quality of a data return signal in real time, and powerful support is provided for network optimization and maintenance.

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Description

Technical Field

[0001] This utility model relates to the field of SFP light source data detection technology, and in particular to a signal detection circuit that supports multiple SFP light sources. Background Technology

[0002] In the current communications field, single-mode SFP (Small Form-factor Pluggable) optical modules are widely used in data centers, enterprise networks, and telecommunications networks as key components for high-speed data transmission. However, existing systems often only support the transmission and reception functions of a single SFP optical module, lacking an integrated system capable of switching transmissions from multiple single-mode SFP light sources and detecting received data return signals. This limits the system's flexibility and scalability, failing to meet the demands of modern communication networks for diverse, high-performance optical communication modules. Therefore, developing an integrated system capable of controlling the transmission of multiple SFP optical modules and detecting received data return signals has become an urgent problem to be solved. Summary of the Invention

[0003] This invention addresses the problems of existing technologies by providing a signal detection circuit that supports multiple SFP light sources. The circuit features a novel structure, enabling the transmission control and reception of data return signals from multiple SFP optical modules, thus ensuring the stability and reliability of data transmission. By integrating a ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, providing strong support for network optimization and maintenance. This signal detection circuit supporting multiple single-mode SFP light sources offers significant benefits in improving communication network performance, reducing operating costs, and enhancing system flexibility.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] This invention provides a signal detection circuit that supports multiple SFP light sources, which includes a main control unit, an SFP optical module control unit, and a ROSA device return signal measurement unit.

[0006] The SFP optical module control unit includes a multiplexer chip U16, an indicator light module, and multiple SFP optical module interfaces. The indicator light module and the multiple SFP optical module interfaces are respectively connected to the multiplexer chip U16. The main control unit is respectively connected to the multiplexer chip U16 and the multiple SFP optical module interfaces.

[0007] The ROSA device return signal measurement unit includes an analog-to-digital converter chip U15, a common-mode data acquisition module, and a differential-mode data acquisition module. The analog-to-digital converter chip U15, the common-mode data acquisition module, and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital converter chip U15 is connected to the differential-mode data acquisition module.

[0008] The model number of the multiplexer chip U16 is TCA9548APWR.

[0009] The analog-to-digital converter chip U15 is model number 3PA1030.

[0010] The differential data acquisition module includes operational amplifiers U14 and U18.2, resistors R40, R41, R44, R45, R46, R47, R48, R49, R52, R53, R54, and R55, capacitors C41, C42, C44, C45, C46, C47, C49, C50, C51, C52, C53, C54, C55, C56, and C57, a Zener diode D4, two Zener diodes D2, and two Zener diodes D3. One end of resistor R45 is connected to one end of capacitor C42, one end of capacitor C41, one end of resistor R40, and the first pin of operational amplifier U14. One end of resistor R46 is connected to... One end of capacitor C55, one end of resistor R53, one end of capacitor C56, one end of resistor R54, and the eighth pin of operational amplifier U14 are connected. The anode of one Zener diode D2 is connected to the cathode of another Zener diode D2 and then to the other end of resistor R45. The anode of one Zener diode D3 is connected to the cathode of another Zener diode D3 and then to the other end of resistor R46. The second pin of operational amplifier U14 is connected to one end of capacitor C44 and analog-to-digital converter chip U15. The other end of capacitor C44 is grounded. The other end of resistor R54 is connected to one end of resistor R55 and the output pin of operational amplifier U18.2. The non-inverting input of operational amplifier U18.2 is connected to analog-to-digital converter chip U15. The inverting input of operational amplifier U18.2 and the other end of resistor R55 are respectively connected to the main control unit.

[0011] The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14. The other ends of resistors R40, R44, and C41 are each connected to one end of resistor R41. The other end of resistor R41 is connected to one end of capacitor C47 and one end of capacitor C49. The other end of capacitor C47 is grounded. The third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46, and one end of resistor R52. The other end of resistor R52 is connected to the seventh pin of operational amplifier U14. The other ends of capacitors C45 and C46 are grounded. The four pins and the other end of capacitor C55 are connected to one end of resistor R47. The other ends of resistor R47, resistor R53, and capacitor C56 are connected to one end of resistor R48. The other end of resistor R48, capacitor C49, capacitor C53, and the cathode of Zener diode D4 are connected to one end of resistor R49. The other end of resistor R49 and capacitor C52 are connected to analog-to-digital converter chip U15. The other end of capacitor C52 is grounded. The sixth pin of operational amplifier U14 is connected to one end of capacitor C50 and one end of capacitor C51. The other ends of capacitor C50 and capacitor C51 are grounded.

[0012] The analog-to-digital converter chip U15 is provided with an AIN pin and a VREF pin. The AIN pin of the analog-to-digital converter chip U15 is connected to the other end of the resistor R49. The differential mode data acquisition module also includes resistors R57, R58, R59, and R61, capacitors C58, C59, C63, and C64, and operational amplifier U18.1.

[0013] The VREF pin of the analog-to-digital converter chip U15 is connected to one end of resistor R61. The other end of resistor R61 is connected to one end of resistor R62, one end of capacitor C63, one end of capacitor C64, and the non-inverting input of operational amplifier U18.1. The output of operational amplifier U18.1 is connected to the non-inverting input of U18.2. The inverting input of operational amplifier U18.1 is connected to one end of resistor R59, one end of resistor R57, and one end of capacitor C58. The other end of resistor R59 is grounded. The eighth pin of operational amplifier U18.1 is connected to one end of capacitor C59. The other end of capacitor C59 is grounded. The other ends of resistor R57 and capacitor C58 are connected to the output of operational amplifier U18.1.

[0014] The common-mode data acquisition module includes operational amplifiers U17.1 and U17.2, resistors R42, R43, R50, and R51, and capacitors C43, C48, and C54. One end of resistor R42 and one end of capacitor C48 are connected to the non-inverting input of operational amplifier U17.1, and the other end of capacitor C48 is grounded. The inverting input and output of operational amplifier U17.1 are respectively connected to one end of resistor R43. The other end is connected to the main control unit. The fourth pin of operational amplifier U17.1 is grounded, and the eighth pin of operational amplifier U17.1 is connected to one end of capacitor C43, while the other end of capacitor C43 is grounded. One end of resistor R50 and one end of capacitor C54 are connected to the non-inverting input of operational amplifier U17.2, while the other end of capacitor C54 is grounded. The inverting input and output of operational amplifier U17.2 are connected to one end of resistor R51, while the other end of resistor R51 is connected to the main control unit.

[0015] The SFP optical module interfaces include SFP1, SFP2, SFP3, and SFP4. Each SFP optical module interface includes an SFP_DIS pin and an SFP_FAULT pin. The indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7, and LED8. The SFP_DIS and SFP_FAULT pins of SFP1 are connected to LED1 and LED5, respectively. The SFP_DIS and SFP_FAULT pins of SFP2 are connected to LED2 and LED6, respectively. The SFP_DIS and SFP_FAULT pins of SFP3 are connected to LED3 and LED7, respectively. The SFP_DIS and SFP_FAULT pins of SFP4 are connected to LED4 and LED8, respectively.

[0016] The main control unit includes chip U1 and chip U2. The model of chip U1 is AX58200 and the model of chip U2 is STM32H730.

[0017] The signal detection circuit supporting multiple single-mode SFP light sources also includes a power supply circuit, which provides power to the main control unit, the SFP optical module control unit, and the ROSA device return signal measurement unit.

[0018] The beneficial effects of this utility model are:

[0019] This application features a novel structure and ingenious design. The main control unit, as the core of the entire circuit, is responsible for receiving external commands and controlling the operation of the SFP optical module control unit and the ROSA device return signal measurement unit according to these commands. The main control unit is responsible for high-speed data processing and system logic control. A multiplexer chip U16 controls the switching of multiple SFP optical module interfaces, and an indicator module displays the operating status of each SFP optical module. An analog-to-digital converter chip U15 converts the acquired analog signals into digital signals for processing by the main control unit. A differential data acquisition module acquires differential signals, and a common-mode data acquisition module acquires common-mode signals. Based on the received commands, the main control unit selects the appropriate SFP optical module for transmission control via the multiplexer chip U16. Simultaneously, the ROSA device return signal measurement unit acquires the received data return signals, including differential and common-mode signals, converts these signals into digital signals, and sends them to the main control unit for processing. The main control unit monitors the optical coupling of the differential or common-mode voltage of the receiving device based on the processing results, and controls the multiplexing of multiple light sources and the transmission data mode and frequency. Multiple interface support: This application uses multiple independent SFP optical module interfaces, improving the system's flexibility and scalability. By using multiple independent SFP optical module interfaces, multiple optical modules of different wavelengths can be connected, realizing the multiplexing of multiple light sources and improving the circuit's communication capacity and efficiency. Furthermore, the circuit of this application can realize the transmission control of multiple SFP optical modules and the detection of received data return signals, ensuring the stability and reliability of data transmission. By integrating a ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, providing strong support for network optimization and maintenance. The signal detection circuit of this application supporting multiple single-mode SFP light sources has significant beneficial effects in improving communication network performance, reducing operating costs, and enhancing system flexibility. Attached Figure Description

[0020] Figure 1 This is a circuit diagram of the main control unit of this utility model.

[0021] Figure 2 This is a circuit diagram of the SFP optical module control unit of this utility model.

[0022] Figure 3 This is a circuit diagram of the ROSA device return signal measurement unit of this utility model.

[0023] Figure 4 This is a circuit diagram of the power supply circuit of this utility model. Detailed Implementation

[0024] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention. The present invention will be described in detail below with reference to the accompanying drawings.

[0025] A signal detection circuit that supports multiple SFP light sources, such as Figures 1 to 4 As shown, it includes a main control unit, an SFP optical module control unit, and a ROSA device return signal measurement unit; wherein, the main control unit includes chip U1 and chip U2, chip U1 is model AX58200 and chip U2 is model STM32H730; the SFP optical module control unit includes a multiplexer chip U16, an indicator light module, and multiple SFP optical module interfaces, the indicator light module and the multiple SFP optical module interfaces are respectively connected to the multiplexer chip U16, and the main control unit is respectively connected to the multiplexer chip U16. The multiplexer chip U16 and multiple SFP optical module interfaces are connected; the ROSA device return signal measurement unit includes an analog-to-digital converter chip U15, a common-mode data acquisition module, and a differential-mode data acquisition module. The analog-to-digital converter chip U15, the common-mode data acquisition module, and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital converter chip U15 is connected to the differential-mode data acquisition module; wherein, the multiplexer chip U16 is model TCA9548APWR; the analog-to-digital converter chip U15 is model 3PA1030.

[0026] Specifically, in this embodiment, the main control unit, as the core of the entire circuit, is responsible for receiving external commands and controlling the operation of the SFP optical module control unit and the ROSA device return signal measurement unit according to the commands. The main control unit includes two chips: AX58200 and STM32H730, responsible for high-speed data processing and system logic control, respectively. A multiplexer chip U16 (TCA9548APWR) controls the switching of multiple SFP optical module interfaces, and an indicator light module displays the operating status of each SFP optical module. An analog-to-digital converter chip U15 converts the acquired analog signals into digital signals for processing by the main control unit. A differential data acquisition module acquires differential signals, and a common-mode data acquisition module acquires common-mode signals. The main control unit selects the appropriate SFP optical module for transmission control via the multiplexer chip U16 according to the received commands. Simultaneously, the ROSA device return signal measurement unit acquires the received data return signals, including differential and common-mode signals, converts these signals into digital signals, and sends them to the main control unit for processing. The main control unit then performs docking based on the processing results. The application features optical coupling monitoring of differential or common-mode voltage of receiving devices, multiplexing of multiple light sources, and control of transmission data modes and frequencies. It also supports multiple interfaces: employing multiple independent SFP optical module interfaces improves system flexibility and scalability; by using multiple independent SFP optical module interfaces, multiple optical modules of different wavelengths can be connected, realizing multiplexing of multiple light sources and improving the circuit's communication capacity and efficiency; furthermore, the circuit can control the transmission of multiple SFP optical modules and detect the received data return signals, ensuring the stability and reliability of data transmission; by integrating a ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, providing strong support for network optimization and maintenance; the signal detection circuit supporting multiple single-mode SFP light sources has significant beneficial effects in improving communication network performance, reducing operating costs, and enhancing system flexibility.

[0027] In this embodiment, the differential data acquisition module includes operational amplifier U14, operational amplifier U18.2, resistors R40, R41, R44, R45, R46, R47, R48, R49, R52, R53, R54, R55, capacitors C41, C42, C44, C45, C46, C47, C49, C50, C51, C52, C53, C54, C55, C56, C57, Zener diode D4, two Zener diodes D2, and two Zener diodes D3; one end of resistor R45 is connected to one end of capacitor C42, one end of capacitor C41, one end of resistor R40, and the first pin of operational amplifier U14, and one end of resistor R46... The terminals are respectively connected to one end of capacitor C55, one end of resistor R53, one end of capacitor C56, one end of resistor R54, and the eighth pin of operational amplifier U14. The anode of one Zener diode D2 is connected to the cathode of another Zener diode D2 and then to the other end of resistor R45. The anode of one Zener diode D3 is connected to the cathode of another Zener diode D3 and then to the other end of resistor R46. The second pin of operational amplifier U14 is connected to one end of capacitor C44 and analog-to-digital converter chip U15. The other end of capacitor C44 is grounded. The other end of resistor R54 is connected to one end of resistor R55 and the output pin of operational amplifier U18.2. The non-inverting input of operational amplifier U18.2 is connected to analog-to-digital converter chip U15. The inverting input of operational amplifier U18.2 and the other end of resistor R55 are respectively connected to the main control unit.

[0028] The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14. The other ends of resistors R40, R44, and C41 are each connected to one end of resistor R41. The other end of resistor R41 is connected to one end of capacitor C47 and one end of capacitor C49. The other end of capacitor C47 is grounded. The third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46, and one end of resistor R52. The other end of resistor R52 is connected to the seventh pin of operational amplifier U14. The other ends of capacitors C45 and C46 are grounded. The four pins and the other end of capacitor C55 are connected to one end of resistor R47. The other ends of resistor R47, resistor R53, and capacitor C56 are connected to one end of resistor R48. The other end of resistor R48, capacitor C49, capacitor C53, and the cathode of Zener diode D4 are connected to one end of resistor R49. The other end of resistor R49 and capacitor C52 are connected to analog-to-digital converter chip U15. The other end of capacitor C52 is grounded. The sixth pin of operational amplifier U14 is connected to one end of capacitor C50 and one end of capacitor C51. The other ends of capacitor C50 and capacitor C51 are grounded.

[0029] The analog-to-digital converter chip U15 is provided with an AIN pin and a VREF pin. The AIN pin of the analog-to-digital converter chip U15 is connected to the other end of the resistor R49. The differential mode data acquisition module also includes resistors R57, R58, R59, and R61, capacitors C58, C59, C63, and C64, and operational amplifier U18.1.

[0030] The VREF pin of the analog-to-digital converter chip U15 is connected to one end of resistor R61. The other end of resistor R61 is connected to one end of resistor R62, one end of capacitor C63, one end of capacitor C64, and the non-inverting input of operational amplifier U18.1. The other ends of resistor R62, capacitor C63, and capacitor C64 are grounded. The output of operational amplifier U18.1 is connected to the non-inverting input of U18.2. The inverting input of operational amplifier U18.1 is connected to one end of resistor R59, one end of resistor R57, and one end of capacitor C58. The other end of resistor R59 is grounded. The eighth pin of operational amplifier U18.1 is connected to one end of capacitor C59. The other end of capacitor C59 is grounded. The other ends of resistor R57 and capacitor C58 are connected to the output of operational amplifier U18.1.

[0031] Specifically, under the above settings, resistors R40, R41, R44, R45, R46, R47, R48, R49, R52, R53, R54, and R55 are mainly used to set the gain and bias current of the operational amplifier and to provide appropriate voltage division for the circuit; they are connected to the input, output, and feedback loops of the operational amplifier to control the amplitude and stability of the signal; resistors R57, R58, R59, R61, and R62 are related to operational amplifier U18.1 and are used to set the resistance values of its input, output, and feedback loops to control the gain and stability of the signal; resistor R61 is used to provide a reference voltage to the VREF pin of the analog-to-digital converter chip U15; operational amplifier U14 is used for amplification and conditioning of differential signals. It receives differential-mode signals from external sensors, amplifies them through its gain and feedback network, and then outputs them to the analog-to-digital converter chip U15 for digital processing; Operational amplifiers U18.1 and U18.2: These two operational amplifiers are used to further condition the signal, such as providing additional gain, filtering, or buffering; the output of U18.1 may be used as the input of U18.2 to form a cascaded amplification or filtering circuit; the output of U18.2 is finally connected to the analog-to-digital converter chip U15; Analog-to-digital converter chip U15: This chip is responsible for converting analog signals into digital signals; it receives the conditioned analog signals from the operational amplifiers and samples and quantizes them through its AIN pin. The digital signal is then output to subsequent digital processing circuits; the VREF pin may be used to receive a reference voltage to ensure the accuracy and stability of the analog-to-digital conversion; capacitors C41, C42, C44, C45, C46, C47, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C63, and C64: these capacitors are mainly used for filtering, decoupling, and stabilizing circuits; they, together with resistors and operational amplifiers, form a filter network to eliminate high-frequency noise and interference; at the same time, they also provide necessary decoupling and bypass capacitors for operational amplifiers and analog-to-digital conversion chips to ensure the stability and performance of the circuit.

[0032] In this embodiment, the common-mode data acquisition module includes operational amplifiers U17.1 and U17.2, resistors R42, R43, R50, and R51, capacitors C43, C48, and C54. One end of resistor R42 and one end of capacitor C48 are connected to the non-inverting input of operational amplifier U17.1, and the other end of capacitor C48 is grounded. The inverting input and output of operational amplifier U17.1 are respectively connected to one end of resistor R43. The other end of 43 is connected to the main control unit. The fourth pin of operational amplifier U17.1 is grounded. The eighth pin of operational amplifier U17.1 is connected to one end of capacitor C43, and the other end of capacitor C43 is grounded. One end of resistor R50 and one end of capacitor C54 are connected to the non-inverting input of operational amplifier U17.2, and the other end of capacitor C54 is grounded. The inverting input and output of operational amplifier U17.2 are connected to one end of resistor R51, and the other end of resistor R51 is connected to the main control unit.Specifically, the input terminals of operational amplifier U17.1 are connected in series with resistor R42 and capacitor C48 to the non-inverting input terminal. Here, capacitor C48 acts as an AC coupler, allowing AC signals to pass while blocking DC signals. Resistor R42 limits the input current. The inverting input terminal and output terminal of operational amplifier U17.1 are connected through resistor R43, forming a negative feedback loop. This connection allows the operational amplifier to operate in a voltage follower mode, meaning the output voltage follows the input voltage, but with higher input impedance and lower output impedance. The output terminal of operational amplifier U17.1 is connected to the main control unit through resistor R43. Here, resistor R43 not only limits the current but also transmits the output voltage of the operational amplifier to the main control unit for further processing. The circuit structure of operational amplifier U17.2 is similar to that of U17.1, but it processes a different common-mode signal. Resistor R50 and capacitor C54 are connected in series to the non-inverting input terminal of operational amplifier U17.2, and capacitor C54 also acts as an AC coupler. The inverting input and output of operational amplifier U17.2 are connected through resistor R51 to form a negative feedback loop, enabling U17.2 to operate in voltage follower mode. The output of operational amplifier U17.2 is connected to the main control unit through resistor R51. Capacitor C43 is connected to pin 8 of operational amplifier U17.1 (usually a power supply pin or reference voltage pin, depending on the operational amplifier model) and grounded. This is used to provide a stable power supply voltage or reference voltage, or to filter out high-frequency noise on the power line. Common-mode signal processing: In this module, operational amplifiers U17.1 and U17.2 process two common-mode signals respectively. Common-mode signals refer to the same signals that appear simultaneously on differential signal pairs. These signals may be introduced by the external environment, such as power line noise, ground potential differences, etc. Through the voltage follower function of the operational amplifiers, these common-mode signals are amplified (actually voltage followed) and transmitted to the main control unit. In the main control unit, these signals can be used to monitor the common-mode noise level of the system or for subsequent digital signal processing to eliminate common-mode interference. The main control unit receives the output signals from operational amplifiers U17.1 and U17.2 and performs further digital signal processing, such as filtering, amplification, and A / D conversion, to extract useful information or eliminate unwanted noise. The common-mode data acquisition module processes two common-mode signals through the two operational amplifiers and transmits the processed signals to the main control unit for further processing. This helps to monitor and eliminate common-mode noise in the system and improve the accuracy and reliability of data acquisition.

[0033] In this embodiment, the plurality of SFP optical module interfaces include optical module interface SFP1, optical module interface SFP2, optical module interface SFP3, and optical module interface SFP4. Each SFP optical module interface includes an SFP_DIS pin and an SFP_FAULT pin. The indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7, and LED8. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP1 are connected to LED1 and LED5, respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP2 are connected to LED2 and LED6, respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP3 are connected to LED3 and LED7, respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP4 are connected to LED4 and LED8, respectively. Specifically, this circuit comprises three parts: I2C data monitoring, data transmission control, and light source transmission enable and indication. Each channel is independent, and the monitoring interfaces also need to be independent. The circuit operates as follows: TXD+ / TXD- form complementary differential or identical voltage levels to achieve differential or common-mode data output. The frequency is controlled by the MCU using different reload and comparison values of the two complementary EPWM channels. LEDs 1 to 4 indicate whether the transmission function is normal. The SFP_DIS signal is controlled by the MCU to enable and stop data transmission, and LEDs 5 to 6 indicate whether the enable function is working properly. The monitoring interface uses an I2C analog switch; a single I2C signal is switched from I2C2 to one of the four channels, facilitating isolation between optical modules with the same device address and enabling monitoring of multiple modules. By observing the LED status, users can quickly understand the operating status of each SFP optical module interface. For example, if an LED remains lit, it may indicate that the corresponding optical module has been disabled or is faulty. This helps system administrators quickly identify and resolve optical module-related problems, thereby improving system reliability and maintainability.

[0034] In this embodiment, the signal detection circuit supporting multiple single-mode SFP light sources further includes a power supply circuit. This power supply circuit provides power to the main control unit, the SFP optical module control unit, and the ROSA device return signal measurement unit. Specifically, the power supply circuit primarily uses a 24V power supply to power this application, including the SFP power supply, the main control unit, and the analog power supply. Chips U3, U6, U8, and U11 form a buck converter module. One MCU power supply uses U3 to step down to 4.5V, then uses U4 for linear regulation to step down to 3.3V to power the AX58200 processor. The other supply uses U3 to step down to 4.5V, then uses U5 for linear regulation to step down to 3.3V to power the STM32H730 processor. This effectively reduces overall power consumption, heat generation, and ripple. The SFP power supply is provided by two DC-DC power supplies, each of which powers a separate linear regulator, ensuring each SFP power supply provides a stable maximum of 800mA at 3.3V. A D1 (transient voltage suppressor) and an F1 (resetting fuse) are added after the 24V input to ensure the input current does not exceed 1.1A and the input voltage does not exceed 26V.

[0035] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present utility model without departing from the scope of the present utility model shall fall within the scope of the present utility model.

Claims

1. A signal detection circuit supporting multiple SFP light sources, characterized in that: Includes a main control unit, an SFP optical module control unit, and a ROSA device return signal measurement unit; The SFP optical module control unit includes a multiplexer chip U16, an indicator light module, and multiple SFP optical module interfaces. The indicator light module and the multiple SFP optical module interfaces are respectively connected to the multiplexer chip U16. The main control unit is respectively connected to the multiplexer chip U16 and the multiple SFP optical module interfaces. The ROSA device return signal measurement unit includes an analog-to-digital converter chip U15, a common-mode data acquisition module, and a differential-mode data acquisition module. The analog-to-digital converter chip U15, the common-mode data acquisition module, and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital converter chip U15 is connected to the differential-mode data acquisition module.

2. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The multiplexer chip U16 is model number TCA9548APWR.

3. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The analog-to-digital converter chip U15 is model number 3PA1030.

4. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The differential data acquisition module includes operational amplifiers U14 and U18.2, resistors R40, R41, R44, R45, R46, R47, R48, R49, R52, R53, R54, and R55, capacitors C41, C42, C44, C45, C46, C47, C49, C50, C51, C52, C53, C54, C55, C56, and C57, a Zener diode D4, two Zener diodes D2, and two Zener diodes D3. One end of resistor R45 is connected to one end of capacitor C42, one end of capacitor C41, one end of resistor R40, and the first pin of operational amplifier U14. One end of resistor R46 is connected to... One end of capacitor C55, one end of resistor R53, one end of capacitor C56, one end of resistor R54, and the eighth pin of operational amplifier U14 are connected. The anode of one Zener diode D2 is connected to the cathode of another Zener diode D2, and then connected to the other end of resistor R45. The anode of one Zener diode D3 is connected to the cathode of another Zener diode D3, and then connected to the other end of resistor R46. The second pin of operational amplifier U14 is connected to one end of capacitor C44 and analog-to-digital converter chip U15. The other end of capacitor C44 is grounded. The other end of resistor R54 is connected to one end of resistor R55 and the output pin of operational amplifier U18.

2. The non-inverting input of operational amplifier U18.2 is connected to analog-to-digital converter chip U15. The inverting input of operational amplifier U18.2 and the other end of resistor R55 are respectively connected to the main control unit. The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14. The other ends of resistors R40, R44, and C41 are each connected to one end of resistor R41. The other end of resistor R41 is connected to one end of capacitor C47 and one end of capacitor C49. The other end of capacitor C47 is grounded. The third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46, and one end of resistor R52. The other end of resistor R52 is connected to the seventh pin of operational amplifier U14. The other ends of capacitors C45 and C46 are grounded. The four pins and the other end of capacitor C55 are connected to one end of resistor R47. The other ends of resistor R47, resistor R53, and capacitor C56 are connected to one end of resistor R48. The other end of resistor R48, capacitor C49, capacitor C53, and the cathode of Zener diode D4 are connected to one end of resistor R49. The other end of resistor R49 and capacitor C52 are connected to analog-to-digital converter chip U15. The other end of capacitor C52 is grounded. The sixth pin of operational amplifier U14 is connected to one end of capacitor C50 and one end of capacitor C51. The other ends of capacitor C50 and capacitor C51 are grounded.

5. A signal detection circuit supporting multiple SFP light sources according to claim 4, characterized in that: The analog-to-digital converter chip U15 is provided with an AIN pin and a VREF pin. The AIN pin of the analog-to-digital converter chip U15 is connected to the other end of the resistor R49. The differential mode data acquisition module also includes resistors R57, R58, R59, and R61, capacitors C58, C59, C63, and C64, and operational amplifier U18.

1. The VREF pin of the analog-to-digital converter chip U15 is connected to one end of resistor R61. The other end of resistor R61 is connected to one end of resistor R62, one end of capacitor C63, one end of capacitor C64, and the non-inverting input of operational amplifier U18.

1. The output of operational amplifier U18.1 is connected to the non-inverting input of U18.

2. The inverting input of operational amplifier U18.1 is connected to one end of resistor R59, one end of resistor R57, and one end of capacitor C58. The other end of resistor R59 is grounded. The eighth pin of operational amplifier U18.1 is connected to one end of capacitor C59. The other end of capacitor C59 is grounded. The other ends of resistor R57 and capacitor C58 are connected to the output of operational amplifier U18.

1.

6. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The common-mode data acquisition module includes operational amplifiers U17.1 and U17.2, resistors R42, R43, R50, and R51, and capacitors C43, C48, and C54. One end of resistor R42 and one end of capacitor C48 are connected to the non-inverting input of operational amplifier U17.1, and the other end of capacitor C48 is grounded. The inverting input and output of operational amplifier U17.1 are respectively connected to one end of resistor R43, and the other end of resistor R43... One end is connected to the main control unit. The fourth pin of operational amplifier U17.1 is grounded. The eighth pin of operational amplifier U17.1 is connected to one end of capacitor C43, and the other end of capacitor C43 is grounded. One end of resistor R50 and one end of capacitor C54 are connected to the non-inverting input of operational amplifier U17.2, and the other end of capacitor C54 is grounded. The inverting input and output of operational amplifier U17.2 are connected to one end of resistor R51, and the other end of resistor R51 is connected to the main control unit.

7. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The plurality of SFP optical module interfaces include optical module interface SFP1, optical module interface SFP2, optical module interface SFP3 and optical module interface SFP4. Each of the SFP optical module interfaces includes an SFP_DIS pin and an SFP_FAULT pin. The indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP1 are connected to LED1 and LED5 respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP2 are connected to LED2 and LED6 respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP3 are connected to LED3 and LED7 respectively. The SFP_DIS pin and SFP_FAULT pin of optical module interface SFP4 are connected to LED4 and LED8 respectively.

8. The signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The main control unit includes chip U1 and chip U2. The model of chip U1 is AX58200 and the model of chip U2 is STM32H730.

9. A signal detection circuit supporting multiple SFP light sources according to claim 1, characterized in that: The signal detection circuit supporting multiple single-mode SFP light sources also includes a power supply circuit, which provides power to the main control unit, the SFP optical module control unit, and the ROSA device return signal measurement unit.