Integrated circuit

Abstract

The embodiment of the utility model relates to an integrated circuit. An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate, and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate defined by a lateral isolation region. The memory cell includes a lateral isolation region thickness (in width) dimension between sidewalls of a vertical gate of the buried transistor and the second active region.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2311932, filed on 2 November 2023, the contents of which are hereby incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The embodiments and implementations relate to non-volatile memory integrated circuits, specifically to memories capable of being programmed and erased at a granularity of one bit. Background Technology

[0004] Non-volatile memory that can be programmed and erased at a granular level in memory cells has been proposed in technologies that include memory cells, which are provided with vertical gate select transistors buried in a semiconductor substrate and floating gate state transistors.

[0005] In this type of architecture, an interface exists between the gate of the select transistor and the active region that supports the erase condition, designed to utilize the floating gate of the state transistor to achieve, for example, the Fowler-Nordheim effect. Specifically, this is the case in the so-called "split voltage" technique.

[0006] In fact, in the split voltage technique, potentials with opposite signs are typically generated on either side of the floating gate; for example, essentially -8V in the control gate of the state transistor and essentially +8V in the active region, while the gate of the select transistor is typically at 0V.

[0007] Under this type of condition, the interface between the gate of the selection transistor and the active region (which typically includes a gate dielectric layer) withstands a voltage of 8V.

[0008] Therefore, the interface must be able to withstand 8V of pressure at each erase cycle throughout the product's entire lifespan.

[0009] On the other hand, space charge regions can be formed at the interface between the gate and the active region of the select transistor, which leads to a loss of erase efficiency.

[0010] Increasing the thickness of the gate dielectric layer at the interface between the gate and the active region of the select transistor can increase the voltage resistance and limit the efficiency loss of the erase operation.

[0011] However, it is beneficial to co-integrate the fabrication of capacitive elements (capacitors) while manufacturing the buried vertical gate.

[0012] However, increasing the thickness of the gate dielectric layer of the select transistor leads to an increase in the thickness of the dielectric layer at the capacitor interface in the case of co-integration, and thus a decrease in capacitor performance (lower capacitance value).

[0013] In a vertical gate structure, the dissociation of two dielectric layers to obtain two different thicknesses leads to increased manufacturing costs and a loss of the advantages of synergistic integration.

[0014] Therefore, it is necessary to remedy the above-mentioned shortcomings, namely, to increase the voltage resistance of the buried vertical gate and improve the efficiency of the erase operation of the memory cell without causing any performance loss or increase in production cost of the co-integrated capacitor components. Utility Model Content

[0015] The embodiments and implementations defined below propose the production of memory cells in which the thickness of the dielectric interface between the vertical gate and the second active region is increased without increasing the thickness of the gate dielectric of the dielectric interface of the co-integrated capacitor elements and without adversely affecting the co-integration or causing additional costs.

[0016] Therefore, according to one aspect, an integrated circuit is proposed, the integrated circuit including a semiconductor substrate and at least one memory cell, the at least one memory cell being provided with a vertical gate select transistor buried in the substrate and a floating gate state transistor, the floating gate state transistor covering a first active region and a second active region of the substrate defined by a lateral isolation region; wherein, the memory cell includes a lateral isolation region thickness between the sidewall of the vertical gate of the buried transistor and the second active region.

[0017] For example, lateral isolation areas belong to the shallow trench isolation type.

[0018] Given that almost all technologies offer lateral isolation areas, this aspect provides a free solution that is compatible with almost all manufacturing methods.

[0019] According to one embodiment, the vertical gate of the selection transistor includes a dielectric shell on the sidewalls and bottom of a trench filled with conductive regions in a substrate, wherein the thickness of the lateral isolation region between the sidewalls of the vertical gate and the second active region is at least 5 times the thickness of the dielectric shell.

[0020] According to one embodiment, the integrated circuit further includes a capacitor element having a vertically conductive electrode buried in a substrate, the vertically conductive electrode having the same structure and composition as the vertical gate of the selection transistor.

[0021] According to one embodiment, the second active region includes the implantation of a dopant of the type opposite to that of the substrate, which occupies the volume below the floating gate of the occupied state transistor.

[0022] It should be noted that the thickness of the lateral isolation region between the sidewall of the vertical gate of the buried transistor and the second active region further provides the aforementioned advantages, injecting additional robustness of alignment in the second active region.

[0023] According to one embodiment, the integrated circuit further includes a write circuit configured to generate programming conditions and erase conditions, the programming conditions and erase conditions being adjusted to cause charge transfer of a first symbol between a floating gate and a first active region, and charge transfer of a second symbol between a floating gate and a second active region, respectively.

[0024] According to another aspect, a method for manufacturing at least one memory cell of an integrated circuit includes: forming a lateral isolation region in a semiconductor substrate, the lateral isolation region defining a first active region and a second active region; forming a vertical gate select transistor, the vertical gate select transistor being buried in the substrate and positioned such that the thickness of the lateral isolation region lies between the sidewall of the vertical gate and the second active region; and forming a floating gate state transistor, the floating gate state transistor covering the first active region and the second active region.

[0025] According to one implementation, forming the vertical gate of a selection transistor includes: etching a trench in a substrate; forming a dielectric shell on the sidewalls and bottom of the trench; and forming a conductive region that fills the remainder of the trench. The etching of the trench is positioned opposite a lateral isolation region to maintain, after etching, the thickness of the lateral isolation region between the sidewalls of the vertical gate and a second active region, the thickness of the lateral isolation region being at least five times the thickness of the dielectric shell.

[0026] In one implementation, the formation of the vertical gate of the selection transistor is performed concurrently with the formation of the vertical conductive electrode buried in the substrate of the capacitor element. Therefore, the electrode specifically has the same structure and composition as the vertical gate of the selection transistor.

[0027] According to one implementation, the method further includes implanting a dopant of the opposite type to that of the substrate in a second active region, the dopant of the opposite type to that of the substrate occupying a volume below the future floating gate in the second active region.

[0028] According to one implementation, the method further includes forming a write circuit configured to generate programming and erasing conditions, the programming and erasing conditions being adjusted to cause charge transfer of a first symbol between a floating gate and a first active region, and charge transfer of a second symbol between a floating gate and a second active region, respectively. Attached Figure Description

[0029] Other advantages and features of this disclosure will become apparent upon examination of the detailed description of the non-limiting embodiments and implementations, and from the accompanying drawings, in which:

[0030] Figure 1A , Figure 1B and Figure 1C The illustration shows a first example of a memory cell;

[0031] Figure 2A and Figure 2B The illustration shows a second example of a memory cell;

[0032] Figures 3 to 8 The illustration depicts the steps of a method for manufacturing a memory cell, which facilitates co-integration manufacturing with capacitor elements; and

[0033] Figure 9 The table of values ​​illustrates examples of voltage conditions on the control gate, drain, vertical gate, and isolated source plane of the selected transistor, thereby enabling programming and erasing operations in the memory cell. Detailed Implementation

[0034] Figure 1A , Figure 1B and Figure 1C The illustration shows a first example of a memory cell (CEL) that is manufactured in and on a semiconductor substrate (SUB) of an integrated circuit.

[0035] Figure 1A The illustration shows a top view of a cell (CEL), with the components of the cell (CEL) shown in a transparent manner.

[0036] Figure 1B The diagram illustrates the cell CEL in Figure 1A A cross-sectional view in plane AA'.

[0037] Figure 1C The diagram illustrates the cell CEL in Figure 1A A cross-sectional view in plane BB'.

[0038] The cell CEL is provided with a vertical gate TG selection transistor TA buried in the substrate and a state transistor TE. The state transistor TE includes a floating gate PO1 capable of storing charge in a non-volatile manner and a control gate PO2 capable of receiving a control potential.

[0039] The vertical gate TG structure buried in the substrate includes a dielectric shell GO on the sidewalls and bottom of a trench in the substrate SUB, the remaining volume of which is filled by a gate conductive region P0, which is made of, for example, polysilicon.

[0040] The stacked structure of the floating gate PO1 and control gate PO2 of the state transistor TE covers the first active region ACT1 and the second active region ACT2 of the substrate. The first active region ACT1 and the second active region ACT2 are defined by the lateral isolation region STI, which is typically a shallow isolation trench.

[0041] In the first active region ACT1, the state transistor TE and the select transistor TA are coupled in series with the drain region D of the state transistor. The drain region D of the state transistor is typically accessible via bit lines and contacts CNT1, the conductive region S / D (which is used as the source of the state transistor TE and the drain of the select transistor TA), and up to the source region of the select transistor TA located in the NISO well deeply implanted in the substrate SUB.

[0042] The second active region ACT2 includes the implantation of a dopant of the opposite type to that of the substrate, which occupies a volume located below the floating gate of the state transistor TE.

[0043] The implantation region CAPIMP is located on the surface of the substrate SUB and extends deeper than the drain D and conductive S / D implantation regions, but shallower than the lateral isolation region STI.

[0044] Contact CNT2 can be electrically connected to the injection region CAPIMP of the second active region ACT2.

[0045] The cross-sectional plane AA' longitudinally passes through the first active region ACT1, while the cross-sectional plane BB' longitudinally passes through the second active region ACT2.

[0046] In a first example of a memory cell CEL, a first active region ACT1 and a second active region ACT2 extend parallel to each other in a first direction and are traversed by a stack of gates of a state transistor TE and by a buried vertical gate TG extending parallel to each other in a second direction, which is perpendicular to the first direction.

[0047] The first active region ACT1 is provided to implement programming-type write operations and to read data contained in the memory cell CEL, while the second active region ACT2 is provided to implement data erasure-type write operations.

[0048] refer to Figure 9 The write operation ECR in the middle.

[0049] Figure 9 The table of values ​​illustrates examples of voltage conditions on the control gate CG (PO2), drain D / CAPIMP (which also biases the injection region CAPIMP in the second active region ACT2), vertical gate, and NISO source plane of the selection transistor TG, enabling programming PROG and erasing EFF operations to be implemented in the memory cell CEL.

[0050] Various write voltages can be generated and distributed using conventional write circuitry, which will not be described in detail here.

[0051] The programming conditions PROG include biasing the control gate at +10V, biasing the drain D at +4.5V, biasing the injection region CAPIMP in the second active region ACT2 at 0V, biasing the vertical gate at a voltage Vt (e.g., 1V) sufficient to generate a conductive channel, and biasing the source plane S at 0V.

[0052] These programming conditions PROG enable the formation of a conductive channel region from the drain D to the NISO source plane, and generate ionization by impacting the source S / D side of the state transistor TE, thereby causing the channel from the source S / D side to inject (negatively signed) hot carriers into the floating gate.

[0053] The erase conditions EFF of the separation voltage type include the bias of the control gate at -8V, the bias of the drain D at 0V, the bias of the injection region CAPIMP in the second active region ACT2 at +8V, the bias of the vertical gate at the blocking voltage of 0V, and the bias of the source plane S at 0V.

[0054] These erase conditions (EFF) enable the generation of (negative-signed) charge transfer from the floating gate PO1 to the second active region ACT2 via the Furi-Noltheim effect through the injection region CAPIMP.

[0055] The erase condition EFF also enables positive sign charge transfer in the floating gate PO1 via the injection region CAPIMP (e.g., also via the Fure-Noltheim effect).

[0056] These write conditions, and especially the erase EFF, offer good performance, one-bit granularity, and small perturbation to adjacent cells.

[0057] In addition, and again refer to Figure 1A , Figure 1B and Figure 1C Advantageously, relative to the above-described writing conditions, after etching the trench TG in the memory cell CEL, the thickness (in width) E of the lateral isolation region STI between the sidewall of the vertical gate TG of the buried transistor and the second active region ACT2 is maintained.

[0058] In fact, in one respect, this prevents the gate dielectric case GO of the select transistor TA from being subjected to the stress of an 8V voltage during an erase operation.

[0059] On the other hand, this allows for further avoidance of forming a reversal region (also known as a space charge region) along the vertical gate buried at the interface with the second active region ACT2 for erasure operations, which would result in a loss of erasure efficiency.

[0060] Depending on the magnitude, the thickness (in width) E of the lateral isolation region STI between the sidewall of the vertical gate and the second active region ACT2 is at least 5 times the thickness of the dielectric shell GO. In fact, depending on the manufacturing limits (or node), the thickness (in width) E can be 5 to 25 times the thickness of the dielectric shell GO.

[0061] For example, the thickness (in width) E dimension of the maintained STI can have a size between 0.03 μm and 0.25 μm, such as 0.08 μm, while the gate dielectric layer can have a thickness of several nanometers, such as from 3 nm to 10 nm.

[0062] Figure 2A and Figure 2B The illustration shows a second example of a memory cell (CEL). The second example differs from the first example in that it is from an architectural perspective (i.e., the arrangement of the resulting components) rather than a functional perspective.

[0063] Figure 2A The diagram shows a top view of a cell (CEL), with the components of the cell shown in a transparent manner.

[0064] Figure 2B The diagram illustrates the cell CEL in Figure 2A A cross-sectional view in plane CC'.

[0065] The second example of the memory cell CEL is an alternative architectural scheme to the first example of the memory cell CEL, wherein only the layout of the elements of the memory cell is changed.

[0066] In a second example of the memory cell CEL, the first active region ACT1 and the second active region ACT2 are aligned in length in the first direction on either side of the vertical gate TG extending in the second direction, and the second direction is perpendicular to the first direction.

[0067] The stacked gates of the state transistor TE cover the vertical gate and the first active region ACT1 and the second active region ACT2 on each side of the selection transistor TA in the first direction.

[0068] The cross-sectional plane CC' passes longitudinally through the first active region ACT1, laterally through the vertical gate TG, and longitudinally through the second active region ACT2.

[0069] The memory cell CEL in both examples has the same components and the same reference numerals. (The preceding text refers to...) Figure 1A , Figure 1B and Figure 1C The description applies to Figure 2A and Figure 2B The memory cell CEL differs from the layout described above.

[0070] Figures 3 to 8 The illustration shows the steps of a method for manufacturing a memory cell CEL, which is advantageously integrated with a capacitor element TCAP during manufacturing.

[0071] and Figure 1B and Figure 1C The cross-sectional views in planes AA' and BB' corresponding to the planes in the first example show the memory cell CEL in the layout for manufacturing the first example, and the corresponding cross-sectional view for the capacitor element TCAP.

[0072] Figure 3 The illustration shows step 300, in which the NISO region is deeply injected into the substrate SUB of the region of the substrate of the receiving memory cell CEL.

[0073] The substrate SUB is, for example, conventional P-type doped silicon, and the deeply implanted NISO layer is N-type doped.

[0074] Figure 4 The illustration shows step 400, in which a lateral isolation region STI is formed, for example, according to a shallow trench isolation technique, wherein a shallow trench is opened in the substrate and filled with a dielectric volume, such as silicon oxide.

[0075] The lateral isolation region STI allows active regions ACT1, ACT2, and ACT3 to be defined between the lateral isolation regions STI on the surface of the substrate SUB.

[0076] Specifically, it should be noted that at step 400, a lateral isolation region STI is provided through the cross-sectional plane BB' of the memory cell.

[0077] Figure 5 The illustration shows step 500: implanting a dopant of the opposite type to the substrate SUB (i.e., implantation of an N-type dopant) into the second active region ACT2, the implantation covering the entire extent of the second active region ACT2 at the surface, down to a depth lower than the depth of the lateral isolation region STI, but with a considerable amplitude.

[0078] The presence of the lateral isolation region STI in the plane BB' of the second active region ACT2 provides additional robustness for the alignment of the injected CAPIMP.

[0079] Figure 6 The illustration shows step 600: etching trench TR, which will receive the vertical gate structure of the selection transistor TA of the memory cell CEL and the vertical electrode structure of the capacitor element TCAP.

[0080] In plane BB', the etch 600 of trench TR is positioned opposite the lateral isolation region STI to maintain the thickness (in width) E dimension of the lateral isolation region STI between the sidewall of the future vertical gate and the second active region ACT2 after etch 600.

[0081] The thickness (in width) E dimension can be configured to be at least 5 times the thickness of the gate dielectric layer GO formed in step 700.

[0082] The thickness (in width) E of the remaining lateral isolation region can be substantially 0.08 μm, for example, between 0.03 μm and 0.25 μm.

[0083] Figure 7 The illustration shows step 700, in which a dielectric shell GO is formed on the sidewalls and bottom of the trench TR, and a conductive region PO0 is formed, which fills the remainder of the trench TR.

[0084] For example, a dielectric shell GO made of silicon oxide has a thickness of the logic transistor gate dielectric type, typically less than 10 nm, for example from 3 nm to 10 nm.

[0085] The magnitude of the thickness of the dielectric shell GO advantageously allows for the production of high capacitance values ​​in capacitor TCAP.

[0086] In fact, the capacitance interface of the capacitor TCAP is located between the conductive region PO0 of the filled trench and the active region ACT3 of the substrate (i.e., the dielectric layer GO).

[0087] The conductive region PO0 is formed, for example, by overfilling polycrystalline silicon and then chemically and mechanically planarizing it until the front side of the substrate SUB is exposed.

[0088] Therefore, in the first active region ACT1 of the memory cell and the third active region ACT3 of the receiving capacitor TCAP, the thickness of the dielectric interface between the gate conductive region PO0 and the substrate SUB is the thickness of the gate dielectric layer GO.

[0089] This is particularly advantageous for controlling the capacitance values ​​of the selection transistor TA and the capacitor element TCAP in the first active region ACT1.

[0090] In the second active region ACT2 of the memory cell CEL, the thickness of the dielectric interface between the gate conductive region PO0 and the substrate SUB includes the remaining thickness (in width) E of the gate dielectric layer GO and the lateral isolation region STI, the accumulation of the front side of the substrate, until the depth exceeds the depth of the implantation region CAPIMP (note that the implantation region CAPIMP will support an 8V erase voltage).

[0091] The remaining portion of the dielectric interface between the gate conductive region PO0 and the substrate SUB, i.e., the remaining portion of the dielectric interface between the bottom of the lateral isolation region STI and the deep-injected NISO well, has the thickness of the gate dielectric layer GO (under erase conditions, the substrate SUB facing this thickness GO is at a substantially zero potential).

[0092] Figure 8 The diagram illustrates the conventional formation 800 of the floating gate PO1 and the control gate PO2 stack in a portion of the receive memory cell CEL.

[0093] In summary, a memory cell is formed in which the thickness of the dielectric interface between the vertical gate and the second active region is increased without increasing the thickness of the gate dielectric of the dielectric interface of the co-integrated capacitor elements and without causing dedicated steps or additional costs.

[0094] The thicker dielectric interface enables better isolation between the injection region CAPIMP in the second active region ACT2 and the vertical gate of the selection transistor TA.

[0095] Since there is no space charge region between the injection region CAPIMP and the dielectric interface, the better isolation between the second active region ACT2 (CAPIMP) and the vertical gate of the select transistor TA enables better erasure efficiency; and because the dielectric thickness at the erasure region is more reliable, the lifetime may be longer.

[0096] Furthermore, the possibility of co-integrating two different dielectric interface thicknesses allows for manufacturing costs without increasing the amount of additional masks and steps; and at the same time, it allows for the capacitance value of the capacitor to be maintained without reducing the cost due to the surface space occupied by the capacitor.

Claims

1. An integrated circuit, characterized in that, include: Semiconductor substrate; as well as A memory cell, the memory cell being provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor, the floating gate state transistor covering a first active region and a second active region of the substrate defined by a lateral isolation region; The memory cell includes a lateral isolation region thickness between the sidewall of the vertical gate of the buried transistor and the second active region.

2. The integrated circuit according to claim 1, characterized in that, The vertical gate of the select transistor includes a dielectric shell on the sidewalls and bottom of a trench filled with conductive regions in the substrate, wherein the thickness of the lateral isolation region between the sidewalls of the vertical gate and the second active region is at least 5 times the thickness of the dielectric shell.

3. The integrated circuit according to claim 1, characterized in that, It also includes a capacitor element having a vertically conductive electrode embedded in the substrate, the vertically conductive electrode having the same structure and composition as the vertical gate of the selection transistor.

4. The integrated circuit according to claim 1, characterized in that, The second active region includes the implantation of a dopant of the opposite type to that of the substrate, the implantation occupying a volume located below the floating gate of the state transistor.

5. The integrated circuit according to claim 1, characterized in that, It also includes a write circuit device configured to generate programming conditions and erase conditions, the programming conditions and the erase conditions being adjusted to cause charge transfer of a first symbol between the floating gate and the first active region and charge transfer of a second symbol between the floating gate and the second active region, respectively.

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