Device

Abstract

The utility model relates to a device. A device includes: a semiconductor heterostructure including an active region and a non-active region, and having a channel layer of a high electron mobility transistor (HEMT); the GaN gate layer is located on the channel layer and comprises a first gate finger, a second gate finger and a gate arc connected with the first gate finger and the second gate finger; and a source region between the first and second gate fingers and in contact with the channel layer therebetween, where the channel layer has a higher concentration of isolation dopant species in the non-active region than in the active region, where the entire gate arc is located directly above the active region.

Description

Technical Field

[0001] This disclosure relates to field-effect high electron mobility transistors (HEMTs) and their manufacturing processes. Background Technology

[0002] HEMT devices are known in which the conductive channel is based on the formation of a layer of two-dimensional electron gas (2DEG) with high mobility at a heterojunction (i.e., an interface between semiconductor materials with different band gaps). For example, HEMT devices are known to be based on a heterojunction between aluminum and GaN (AlGaN) layers and GaN (GaN) layers.

[0003] HEMT devices based on AlGaN / GaN heterojunctions or heterostructures offer several advantages, making them particularly suitable for and widely used in various applications. For example, the high breakdown threshold of HEMT devices is used in high-performance power switches; the high electron mobility in the conductive channel allows for high-frequency amplifiers; and the high electron concentration in 2DEG allows for low on-state resistance (R0). ON ).

[0004] AlGaN / GaN HEMTs can typically operate in depletion mode (normally on). However, for practical applications, enhancement-mode (normally off) devices are used to facilitate safe operation and simplify drive circuitry. Several methods have been proposed for realizing normally off HEMTs: recessed gate, under-gate fluorine plasma doping, or p-GaN gate. In the case of p-GaN gate devices, isolation implantation can be used to form the non-active region of the HEMT heterostructure. However, the ion-implanted isolation region may not form a distinct interface with the active region of the GaN HEMT. Lateral ion penetration can introduce defects and lead to the formation of parasitic channels on the sides of the HEMT.

[0005] All topics discussed in the Background section are not necessarily prior art, and should not be assumed to be prior art simply because a topic is discussed in the Background section. Accordingly, unless explicitly stated as prior art, any awareness of problems existing in prior art discussed in the Background section or related to such topics should not be considered prior art. Rather, the discussion of any topic in the Background section should be considered as part of the inventor's solution to a particular problem, which may itself be inventive. Utility Model Content

[0006] Embodiments of this disclosure provide a HEMT and a corresponding manufacturing method that overcomes the drawbacks of other HEMTs and their formation processes. During the HEMT process, a pGaN gate is formed and patterned on a semiconductor heterostructure including a channel layer. The pGaN gate includes a straight first gate finger, a straight second gate finger, and a semi-circular gate arc connecting the first and second gate fingers.

[0007] An isolation mask is formed on the heterostructure, completely covering the pGaN gate, with the edges of the isolation mask very close to the edge of the gate arc. Then, an isolation implantation process is performed in the presence of the mask to implant ions into the masked portions of the heterostructure. This implantation process deactivates the exposed portions of the heterostructure in the HEMT device.

[0008] Due to the placement of the isolation mask and the shape of the pGaN gate, the heterostructure beneath the gate finger is subject to slight or no lateral penetration by the isolation implantation material. This results in improved HEMT performance and reduced formation of parasitic channels on the HEMT sides.

[0009] In one embodiment, a method includes forming a semiconductor heterostructure including a channel layer of a HEMT. The method includes forming a GaN gate layer on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first and second gate fingers. The method includes forming an isolation mask covering the active regions of the semiconductor heterostructure and the gate arc, and performing ion bombardment on the non-active regions of the semiconductor heterostructure exposed by the isolation mask.

[0010] In one embodiment, a device includes a semiconductor heterostructure comprising an active region and an active region, and having a channel layer for a HEMT. The device includes a gate layer situated on the channel layer and including a first gate finger, a second gate finger, and a gate arc connecting the first and second gate fingers. The device includes a source region located between and in contact with the channel layer between the first and second gate fingers. The channel layer has a higher concentration of isolation dopant material in the active region than in the active region. The entire gate arc is located directly above the active region.

[0011] In one embodiment, a method includes forming a semiconductor heterostructure and forming a GaN gate layer on a channel layer, the semiconductor heterostructure comprising an AlGaN channel layer of a high electron mobility transistor (HEMT). The method includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first and second gate fingers. The method includes forming an isolation mask covering the active region of the semiconductor heterostructure and the gate arc, and having a substantially straight edge adjacent to the gate arc and at least 500 nm away from the first and second gate fingers. The method includes defining the non-active region of the semiconductor heterostructure laterally outside the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0012] According to one aspect of this disclosure, a method is provided, comprising: forming a semiconductor heterostructure including a channel layer of a high electron mobility transistor (HEMT); forming a GaN gate layer on the channel layer; patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger; forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc; and performing ion bombardment on a non-active region of the semiconductor heterostructure exposed by the isolation mask.

[0013] According to embodiments of this disclosure, the method includes forming a source region located between a first gate finger and a second gate finger and in contact with a channel layer in an active region.

[0014] According to embodiments of this disclosure, the source region is in contact with a portion of the channel layer outside the active region.

[0015] According to embodiments of the present disclosure, a first gate finger and a second gate finger extend in a first direction, wherein the isolation mask has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

[0016] According to an embodiment of the present disclosure, a first gate finger and a second gate finger extend in a first direction, wherein the edge of the isolation mask has a first portion adjacent to the gate arc, the first portion being an arc shape of the outer edge of the gate arc.

[0017] According to an embodiment of the present disclosure, the edge of the isolation mask has a second portion that is straight, extends in a second direction transverse to the first direction, and connects to the first portion.

[0018] According to embodiments of this disclosure, the method includes: removing an isolation mask after performing an ion bombardment process; and forming a source region after removing the isolation mask.

[0019] According to embodiments of this disclosure, the method includes forming a drain region in contact with the channel region in the same process as forming the source region.

[0020] According to embodiments of this disclosure, the ion bombardment process includes implanting nitrogen ions into a non-active region.

[0021] According to embodiments of this disclosure, the method includes doping a gate layer with a p-type dopant.

[0022] According to embodiments of this disclosure, the channel region comprises AlGaN.

[0023] According to another aspect of this disclosure, a device is provided, comprising: a semiconductor heterostructure including an active region and an active region, and a channel layer having a high electron mobility transistor (HEMT); a GaN gate layer located on the channel layer and including a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger; a source region located between the first gate finger and the second gate finger and in contact with the channel layer therebetween, wherein the channel layer has a higher concentration of isolation dopant material in the active region than in the active region, and wherein the entire gate arc is located directly above the active region.

[0024] According to embodiments of the present disclosure, a first gate finger and a second gate finger extend in a first direction, wherein the boundary between the active region and the non-active region has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

[0025] According to an embodiment of the present disclosure, a first gate finger and a second gate finger extend in a first direction, wherein the boundary between the active region and the non-active region has a first portion adjacent to the gate arc, the first portion being an arc shape of the outer edge of the gate arc.

[0026] According to an embodiment of the present disclosure, the boundary between the active region and the non-active region has a second portion, which is straight, extends in a second direction transverse to the first direction, and connects to the first portion.

[0027] According to embodiments of this disclosure, the device includes the drain region of a HEMT that contacts the channel region in both the non-active and active regions.

[0028] According to embodiments of this disclosure, the drain region has a substantially straight edge, and the source region has a semi-circular edge.

[0029] According to another aspect of this disclosure, a method is provided, comprising: forming a semiconductor heterostructure including an AlGaN channel layer of a high electron mobility transistor (HEMT); forming a GaN gate layer on the channel layer; patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger; forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc, and having a substantially straight edge adjacent to the gate arc and at least 500 nm away from the first gate finger and the second gate finger; and defining a non-active region of the semiconductor heterostructure laterally outside the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0030] According to embodiments of this disclosure, ion bombardment treatment implants nitrogen atoms into the non-active region of a semiconductor heterostructure.

[0031] According to embodiments of the present disclosure, the method includes: removing an isolation mask; forming a source region of a HEMT located between a first gate finger and a second gate finger and contacting the channel layer only at the active region; and forming a drain region of a HEMT contacting the channel layer at both the active and non-active regions. Attached Figure Description

[0032] Figures 1A-1J The images include cross-sectional and top views of an integrated circuit, including various stages of forming a HEMT in an integrated circuit according to one embodiment.

[0033] Figure 2 This is a top view of an integrated circuit including a HEMT according to one embodiment.

[0034] Figure 3 This is a top view of an integrated circuit including a HEMT according to one embodiment.

[0035] Figure 4 This is a flowchart of a method for forming a HEMT according to one embodiment.

[0036] Figure 5 This is a flowchart of a method for forming a HEMT according to one embodiment. Detailed Implementation

[0037] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details, or can be practiced using other methods, components, materials, etc. In other instances, well-known systems, components, and circuit systems associated with integrated circuits have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0038] Unless the context otherwise requires, throughout the specification and the following claims, the word “comprising” and its variations, such as “including” and “comprising of,” shall be interpreted in an open, inclusive sense, i.e., “including but not limited to.” Furthermore, unless the context expressly provides otherwise, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable.

[0039] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in multiple places throughout this specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

[0040] As used in this specification and the appended claims, the singular forms “a” and “the” include plural references, unless otherwise expressly specified. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or” unless otherwise expressly specified.

[0041] Figure 1A This is a cross-sectional view of an integrated circuit 100 in an intermediate stage of forming a HEMT device according to one embodiment. Figure 1A In one embodiment, integrated circuit 100 includes a substrate 102. The substrate 102 may include a semiconductor material. In one embodiment, the substrate 102 includes silicon. However, the substrate 102 may include other types of semiconductor materials. In some embodiments, the substrate 102 may include one or more layers of dielectric material. The substrate 102 may include other materials suitable for forming HEMTs.

[0042] Although Figure 1A The substrate 102 is shown as a single layer, but in practice, the substrate 102 may include multiple layers. For example, the substrate 102 may include a silicon base layer, an aluminum nitride and a silicon layer, and a buffer layer on the aluminum nitride layer, as will be described in more detail below. The substrate 102 may also include silicon carbide, sapphire, aluminum nitride, or other suitable materials.

[0043] In one embodiment, the integrated circuit 100 includes a semiconductor heterostructure 103 formed on a substrate 102. Although the heterostructure 103 is shown as being formed on the substrate 102, in practice, the heterostructure 103 may include a portion of the substrate 102 comprising aluminum nitride and a buffer layer.

[0044] The heterostructure 103 can be formed via an epitaxial growth process. The epitaxial growth process grows the semiconductor heterostructure 103 from a substrate 102. Multiple individual layers of the heterostructure 103 can be formed by adjusting the parameters of the epitaxial growth process in situ. For example, the epitaxial growth process may include flowing one or more gases or other materials into the deposition chamber where the integrated circuit 100 (which is part of a semiconductor wafer at this stage) is located. Temperature, pressure, and materials can be adjusted throughout the epitaxial growth process to form multiple layers of the heterostructure 103. In some cases, when one layer of the heterostructure 103 is completed, a scavenging process can be performed before starting the growth of the next layer to remove any excess gas or byproducts from the deposition chamber.

[0045] In one embodiment, an aluminum nitride semiconductor layer is formed as part of substrate 102 through epitaxial growth. The aluminum nitride layer can be formed as a precursor for forming multiple GaN layers. Aluminum nitride can be chosen as the first layer because gallium can damage the base layer of substrate 102, especially when the base layer includes silicon. Therefore, the epitaxial growth process first forms the aluminum nitride layer so that the GaN layer can be formed subsequently.

[0046] The buffer layer may comprise a superlattice of multiple layers formed on the aluminum nitride layer during the first epitaxial growth process. In an example where the substrate 102 includes an aluminum nitride layer and a subsequent GaN layer is to be formed, the first layer of the superlattice may comprise an AlGaN layer with a high percentage of aluminum and a low percentage of gallium to enable epitaxial growth from the aluminum nitride layer. Subsequent layers of the superlattice comprise AlGaN, wherein the gallium concentration increases and the aluminum concentration decreases. Finally, the top layer of the superlattice may comprise GaN without any aluminum. The superlattice may comprise up to 200 layers. The superlattice may comprise other materials and structures without departing from the scope of this disclosure. The superlattice may also comprise AlGaN and AlN.

[0047] After forming the superlattice, layer 104 is formed on substrate 102. Specifically, layer 104 may be formed on the superlattice of substrate 102. In an example where the superlattice is a transitional structure comprising multiple layers that gradually transition from aluminum nitride to GaN, layer 104 may comprise GaN. In one embodiment, layer 104 of GaN comprises p-type or n-type dopants. In one embodiment, layer 104 of GaN is doped with carbon atoms, which can produce n-type or p-type doping (depending on the carbon concentration). In another embodiment, layer 104 of GaN is doped with magnesium atoms. The total thickness of layer 104 may be approximately 1 μm. The total thickness of the superlattice may also be approximately 2 μm. The composition of the superlattice and GaN layer 104 can facilitate the formation of HEMT devices that can operate at very high voltages. For example, the composition of the superlattice and GaN layer 104 can facilitate the operation of HEMT devices at voltages exceeding 600 V between the terminals of an HEMY device. Other materials, thicknesses, and operating voltages may be used without departing from the scope of this disclosure.

[0048] In one embodiment, layer 104 may include multiple layers. In one embodiment, layer 104 may include an intrinsically doped channel layer GaN that does not contain any doping.

[0049] In one embodiment, layer 104 may include multiple layers. For example, layer 104 may include a GaN layer doped with a p-type dopant as described above. Layer 104 may also include a GaN back barrier layer and a p-doped region of GaN.

[0050] In one example, the back barrier layer may be doped with magnesium atoms. The thickness of the back barrier layer may be between 50 nm and 300 nm. Other materials and thicknesses may be used for the back barrier layer without departing from the scope of this disclosure. Furthermore, in some embodiments, the back barrier layer may be absent.

[0051] In one embodiment, the heterostructure 103 includes a barrier layer 106 and a channel layer 104. The interface between the barrier layer 106 and the layer 104 corresponds to a layer in which a two-dimensional electron gas (2DEG) is formed during transistor operation. Free electrons flow through the channel region based on a bias between the source and drain regions and a control voltage applied to the gate electrode, as will be described in more detail below.

[0052] In one embodiment, the barrier layer 106 comprises AlGaN. The percentage of aluminum can be between 1% and 50%, but other compositions may also be used without departing from the scope of this disclosure. The thickness of the AlGaN layer can be between 1 nm and 30 nm. Other compositions and thicknesses may be used for the AlGaN layer without departing from the scope of this disclosure.

[0053] In one embodiment, the barrier layer 106 may include a thin aluminum nitride layer located between the GaN layer and the AlGaN layer. The barrier layer 106 may have various compositions without departing from the scope of this disclosure.

[0054] The semiconductor heterostructure 103 includes a gate layer 108, a channel layer 104, and a barrier layer 106. The gate layer 108 may comprise heavily p-doped GaN. Therefore, the gate layer 108 may be referred to as a p-GaN layer. The heavy doping of the gate layer 108 results in high conductivity. This, to some extent, enables the semiconductor material of the gate layer 108 to act as a conductive gate layer. The thickness of the gate layer 108 can be between 50 nm and 150 nm. Other thicknesses and materials may be used without departing from the scope of this disclosure.

[0055] exist Figure 1B In this process, the gate layer 108 has been patterned to expose a portion of the barrier layer 106. The gate layer 108 can be patterned according to a photolithography process, wherein a mask is formed on the gate layer 108 with a desired pattern. An etching process can then be performed to remove the gate layer 108 at the locations exposed by the mask, thereby producing a patterned gate layer 108.

[0056] Figure 1C According to one embodiment Figure 1B A top view of the integrated circuit 100 in the processing stage shown. Figure 1C The top view illustration shows the patterned gate layer 108, a straight first gate finger 110 extending in the X direction, and a straight second gate finger 112 extending parallel to the straight first gate finger 110 in the X direction. Gate layer 108 includes... Figure 1C The top of the gate layer 108 is connected to the gate arc 114 of the first gate finger 110 and the second gate finger 112. The gate layer 108 includes... Figure 1C The bottom of the gate layer 108 is connected to the gate arc 116 of the first gate finger 110 and the second gate finger 112. The gate layer 108 also includes an outer edge 118. Figure 1C The diagram also shows the cut-off point above. Figure 1B The cutting line corresponding to the cutting line of the cross section is cutting line 1B. Figure 1C The view illustrates the exposed portion of the barrier layer 106 not covered by the gate layer 108. The patterned gate layer 108 may also be referred to as a gate ring.

[0057] Figure 1D This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 1D In this process, a dielectric layer 124 has been formed on the gate layer 108 and on the exposed portion of the barrier layer 106. The dielectric layer may include aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, silicon nitride, silicon oxide, or other suitable dielectric materials.

[0058] exist Figure 1D In this process, a mask 126 has been formed on the dielectric layer 124. Mask 126 corresponds to an isolation mask, which is used to separate the active regions of the heterostructure 103 from the non-active regions of the heterostructure 103. More specifically, the isolation mask is used to perform an isolation implantation process, during which ions are implanted into the portions of the heterostructure 103 not covered by the isolation mask 126. This implantation process causes the exposed portions of the heterostructure 103 to become the non-active regions of the heterostructure 103, while the unexposed portions of the heterostructure 103 correspond to the active regions of the heterostructure 103.

[0059] Mask 126 may correspond to a hard mask, which includes a dielectric material, a conductive material, a ceramic material, or other materials through which ions will not pass during subsequent ion implantation processes. Mask 126 may be patterned using photolithography.

[0060] like Figure 1D As can be seen, mask 126 includes an edge 128. Edge 128 is positioned in the X direction beyond edge 118 of gate layer 108. The lateral distance between edge 128 and edge 118 helps ensure that any lateral implantation of ions during ion implantation will not extend below the first and second fingers 110 / 112. In one embodiment, the lateral distance between edge 128 of mask 126 and edge 118 of gate layer 108 is less than 5 μm. Other sizes, materials, and shapes may be used for mask 126 without departing from the scope of this disclosure.

[0061] Figure 1E According to one embodiment Figure 1D A top view of the integrated circuit 100 in the processing stage shown. Figure 1E The top view shows the position of edge 128 of mask 126. Figure 1D The location of the gate layer 108 beneath the mask 126 is also illustrated by dashed lines. The edge 128 of the mask 126 is straight and extends laterally and substantially perpendicularly to the directions of the first gate fingers and the second gate fingers 110 and 112. Furthermore, the edge 128 extends beyond the edge 118 of the gate layer 108, such that the entire gate arcs 114 and 116 are covered by the mask 126.

[0062] Figure 1FThis is a cross-sectional view of integrated circuit 100 during an ion implantation process according to one embodiment. The ion implantation process can correspond to an isolation implantation process. During the implantation process, ions (atoms or compounds with a net charge) bombard integrated circuit 100. The ions do not penetrate mask 126. The ions penetrate into layers 104 and 106 at the region exposed by mask 126. The ions penetrate into layers 104 and 106, severely disrupting the semiconductor lattice of the semiconductor material in the heterostructure. This makes the exposed portion of the heterostructure a non-active region. The portion of heterostructure 103 covered by mask 126 remains an active region of heterostructure 103. The active region of heterostructure 103 is part of the HEMT to be formed.

[0063] In one embodiment, the ions disrupt the lattice of layers 104 and 106 at the exposed region. In one embodiment, the ions may include nitrogen, argon, and boron ions. In one embodiment, the ions include nitrogen molecules carrying a net charge. Other types of particles may be used for isolation implantation processes without departing from the scope of this disclosure.

[0064] Figure 1G According to one embodiment Figure 1F A cross-sectional view of the integrated circuit 100 after ion implantation. Mask 126 has been removed. Figure 1G The diagram illustrates the active region 140 and the non-active region 142 of the heterostructure 103. Figure 1G The boundary 144 between the non-active region 142 and the active region 140 is also illustrated.

[0065] In practice, it is possible for ions to be laterally implanted into some areas not covered by mask 106. However, the position of the mask relative to the shape and location of the gate layer 108 helps ensure that no significant lateral implantation occurs into the region of heterostructure 103 directly below gate fingers 110 and 112. Active region 142 differs from active region 140 because the nitrogen concentration in the non-active region 142 is higher than that in active region 140. Active region 142 also differs from active region 140 because the semiconductor layer of heterostructure 103 is damaged or the lattice is disrupted in non-active region 142.

[0066] Figure 1G The illustration shows boundary 144 located at a position corresponding to edge 128 of mask 126. However, in practice, there will be some lateral implantation of ions below mask 126. Boundary 144 may correspond to a position where the concentration of ions implanted therein has a specific value.

[0067] Figure 1H According to one embodiment Figure 1G A top view of the integrated circuit 100. Figure 1HThe diagram illustrates the boundary 144 between the active region 140 and the non-active region 142.

[0068] Figure 1I This is a top view of the integrated circuit 100 after the elements of the HEMT 101 have been further formed, according to one embodiment. Figure 1G In one embodiment, source region 154 and drain region 160 have been formed. A photolithography process can be performed to form trenches that partially extend into the barrier layer 106. Source / drain metal can then be deposited and patterned to form source region 154 and drain region 160. The source / drain metal may include titanium, tantalum, aluminum, titanium nitride, or other suitable conductive materials. The source / drain metal can be deposited using PVD, ALD, CVD, or other suitable deposition processes.

[0069] exist Figure 1I In this embodiment, a gate electrode 150 has been formed on the gate layer 108. The gate electrode 150 is made of gate metal. The gate metal may include titanium nitride, titanium, aluminum, tungsten, and may be deposited by PVD, ALD, CVD, or other suitable deposition processes. The gate metal may include other materials and configurations without departing from the scope of this disclosure. For example, although the gate metal is shown as a single gate metal, in practice, multiple gate metals may be present.

[0070] For the sake of simplicity, Figure 1I The top view does not show other components that may exist in HEMT 101. For example, field plates, metal wires, and other components may be present, such as... Figure 1J As shown in the image.

[0071] HEMT 101 may include various other layers, including passivation layers and other dielectric layers, to isolate and protect the source / drain metals and gate electrode 150. The HEMT can be operated by applying a control voltage to the gate electrode 150 and applying a bias to the source region 154 and drain region 160. Depending on the control and bias voltages, the HEMT can be turned on or off. When the HEMT is turned on, current from the electron gas can flow through the channel layer 106 and under the gate layer 108 between the drain region 160 and the source region 154.

[0072] exist Figure 1I In this configuration, the source region 154 has an arc-shaped end and is laterally formed between the first gate finger 110, the second gate finger 112, and the gate arcs 114 / 116. The drain region 160 extends further in the X direction than the source region 154. Specifically, the drain region 160 extends into the non-active region 142, while the source region 154 is entirely within the active region 140. Furthermore, the drain region 160 has a straight end that initially extends in the Y direction, while the source region 154 has an arc-shaped end.

[0073] Compared to other possible solutions, Figure 1I The HEMT 101 structure offers several advantages. For example, the threshold voltage of the HEMT 101 can be increased. For instance, the threshold voltage can be approximately 1V. Furthermore, the drain current can have a much more dramatic rise after reaching the threshold voltage. Additionally, Figure 1I The HEMT 101 offers lower drain leakage in the off state. Compared to other solutions, the HEMT 101's on-resistance (the effective resistance between the source and drain in the saturation region) is not increased.

[0074] Figure 1J It was cut along the cutting line 1J according to one embodiment. Figure 1I A cross-sectional view of integrated circuit 100. Figure 1J The cross-sectional diagram illustrates Figure 1I Additional components not shown. For example, Figure 1J The diagram illustrates dielectric layer 170 and dielectric layer 124. Figure 1J The diagram illustrates dielectric layer 172 and dielectric layer 170. Figure 1J The illustration shows a field plate 174, which can be used to apply a selected electric field to the channel region in addition to the gate voltage. Figure 1J The diagram also shows the metal line 176 on the dielectric layer 172.

[0075] Figure 1J The illustration shows source region 154 and drain region 160 formed in a trench passing through dielectric layers 170 and 124 and barrier layer 106. Therefore, source region 154 and drain region 160 are in contact with channel layer 106. Figure 1J In this configuration, source region 154 and drain region 160 terminate at the top surface of layer 104. However, source region 154 and drain region 160 may terminate within channel layer 106 or within layer 104. Various other configurations of HEMT 101 may be used without departing from the scope of this disclosure. Although Figure 1I and 1J Although not shown, gate contacts, source contacts, and drain contacts may be present to electrically connect source region 154, drain region 160, and gate 150, as well as other conductive structures formed thereon.

[0076] Figure 2 This is a top view of an integrated circuit 100 including HEMT 101 according to one embodiment. Figure 2 The diagram illustrates that HEMT 101 may include multiple gate layers 108, multiple source regions 154, and multiple drain regions 160. The HEMT may include a plurality of source regions 154, drain regions 160, and gate rings 108. Field plate 174 is also shown adjacent to gate ring 108.

[0077] Figure 3This is a top view of an integrated circuit 100 including HEMT 101 according to one embodiment. Figure 3 HEMT 101 and Figure 1I The HEMT is basically similar, except that the active region 140 has a boundary 144 that is not a straight line. Instead, the boundary has a linear portion extending laterally from the gate fingers 110 and 112 in the Y direction, and a semi-circular arc portion that is substantially the same shape as the edges 118 of the gate arcs 114 and 116.

[0078] Figure 3 The boundary 144 between the active region 140 and the non-active region 142 can be formed by creating semi-circular protrusions with a pattern similar to the desired pattern of the boundary 144. Figure 1D This is achieved using a mask layer 126. Subsequent isolation bombardment processing will produce an active region 140 and a non-active region 142 sharing a boundary 144, as... Figure 3 As shown in the image.

[0079] In one embodiment, HEMT 101 can employ... Figure 1I The retracted gate ring 108 shown is formed, but no isolation implantation process is required. In other words, in one embodiment, the mask 126 is not formed during the performed isolation bombardment process. As a result, there are no non-active regions in which the crystal structure is destroyed by the isolation bombardment process.

[0080] Figure 4 This is a flowchart of a method 400 for forming a HEMT according to one embodiment. Method 400 can use... Figures 1A-3 The described process, structure, and system. At 402, method 400 includes forming a semiconductor heterostructure including a channel layer of HEMT. At 404, method 400 includes forming a GaN gate layer on the channel layer. At 406, method 400 includes patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. At 408, method 400 includes forming an isolation mask covering the active region of the semiconductor heterostructure and the gate arc. At 410, method 400 includes performing an ion bombardment process on the non-active region of the semiconductor heterostructure exposed by the isolation mask.

[0081] Figure 5 This is a flowchart of a method 500 for forming a HEMT according to one embodiment. Method 500 can use... Figures 1A-3The described process, structure, and system. At 502, method 500 includes forming a semiconductor heterostructure comprising an AlGaN channel layer of a HEMT. At 504, method 500 includes forming a GaN gate layer on the channel layer. At 506, method 500 includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger. At 508, method 500 includes forming an isolation mask covering the active region of the semiconductor heterostructure and the gate arc, and having a substantially straight edge adjacent to the gate arc and at least 500 nm away from the first and second gate fingers. At 510, method 500 includes defining a non-active region of the semiconductor heterostructure laterally outside the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0082] In one embodiment, a method includes forming a semiconductor heterostructure including a channel layer of a HEMT. The method includes forming a GaN gate layer on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first and second gate fingers. The method includes forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc, and performing ion bombardment on the non-active regions of the semiconductor heterostructure exposed by the isolation mask.

[0083] In one embodiment, the method includes forming a source region located between a first gate finger and a second gate finger and in contact with a channel layer in the active region.

[0084] In one embodiment, the source region does not contact the channel layer outside the active region.

[0085] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the isolation mask has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

[0086] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the edge of the isolation mask has a first portion that is arc-shaped, resembling the outer edge of the gate arc adjacent to the gate arc.

[0087] In one embodiment, the edge of the isolation mask has a second portion that is straight and extends in a second direction transverse to the first direction and is connected to the first portion.

[0088] In one embodiment, the method includes removing the isolation mask after performing ion bombardment and forming a source region after removing the isolation mask.

[0089] In one embodiment, the method includes forming a drain region in contact with the channel region in the same process as forming the source region.

[0090] In one embodiment, the ion bombardment process includes injecting nitrogen ions into the non-active region.

[0091] In one embodiment, the method includes doping the gate layer with a p-type dopant.

[0092] In one embodiment, the channel region comprises AlGaN.

[0093] In one embodiment, the source region is in contact with the portion of the channel layer outside the active region.

[0094] In one embodiment, a device includes a semiconductor heterostructure comprising an active region and an active region, and having a HEMT channel layer. The device includes a GaN gate layer on the channel layer and includes a first gate finger, a second gate finger, and a gate arc connecting the first and second gate fingers. The device includes a source region channel layer located between and in contact with the first and second gate fingers. The channel layer has a higher concentration of isolation dopant material in the active region than in the active region. The entire gate arc is located directly above the active region.

[0095] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the boundary between the active region and the non-active region has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

[0096] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the boundary between the active region and the non-active region has a first portion adjacent to the gate arc, the first portion being an arc shape of the outer edge of the gate arc.

[0097] In one embodiment, the boundary between the active region and the non-active region has a second portion that is straight, extends in a second direction transverse to the first direction, and connects to the first portion.

[0098] In one embodiment, the device includes a drain region of a HEMT that contacts the channel region in both the non-active region and the active region.

[0099] In one embodiment, the drain region has a substantially straight edge, while the source region has a semi-circular edge.

[0100] In one embodiment, a method includes forming a semiconductor heterostructure and forming a GaN gate layer on a channel layer, the semiconductor heterostructure comprising an AlGaN channel layer of a high electron mobility transistor (HEMT). The method includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first and second gate fingers. The method includes forming an isolation mask covering the active region of the semiconductor heterostructure and the gate arc, and having a substantially straight edge adjacent to the gate arc and at least 500 nm away from the first and second gate fingers. The method includes defining the non-active region of the semiconductor heterostructure laterally outside the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0101] In one embodiment, ion bombardment treatment implants nitrogen atoms into the non-active region of a semiconductor heterostructure.

[0102] In one embodiment, the method includes: removing an isolation mask; forming a source region of a HEMT located between a first gate finger and a second gate finger and in contact with the channel layer only at the active region; and forming a drain region of a HEMT in contact with the channel layer at both the active and non-active regions.

[0103] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents conferred by those claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A device, characterized in that, include: A semiconductor heterostructure, comprising active and non-active regions, and having a channel layer for a high electron mobility transistor (HEMT); The gate layer of GaN is located on the channel layer and includes a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger; The source region is located between the first gate finger and the second gate finger and in contact with the channel layer between them, wherein the channel layer has a higher concentration of isolation dopant material in the non-active region than in the active region, and wherein the entire gate arc is located directly above the active region.

2. The device as described in claim 1, characterized in that, The first gate finger and the second gate finger extend in a first direction, and the boundary between the active region and the non-active region has a substantially straight edge that extends beyond the first gate finger, the second gate finger and the gate arc in a second direction transverse to the first direction.

3. The device as described in claim 1, characterized in that, The first gate finger and the second gate finger extend in a first direction, and the boundary between the active region and the non-active region has a first portion adjacent to the gate arc, the first portion being an arc shape in the shape of the outer edge of the gate arc.

4. The device as described in claim 3, characterized in that, The boundary between the active region and the non-active region has a second part, which is straight, extends in a second direction transverse to the first direction, and connects to the first part.

5. The device as claimed in claim 1, characterized in that, This includes the drain region of the HEMT that contacts the channel region in both the non-active and active regions.

6. The device as described in claim 5, characterized in that, The drain region has a basically straight edge, while the source region has a semi-circular edge.

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