HJT cell and photovoltaic module

Abstract

The utility model relates to the technical field of solar cells, in particular to an HJT cell and a photovoltaic module. The HJT battery comprises a first conductive layer and a second conductive layer which are oppositely arranged; wherein the first conductive layer comprises a composite layer formed by laminating a first transparent conductive layer, an Ag layer and a second transparent conductive layer, and the second conductive layer comprises a third transparent conductive layer. Therefore, the P-side conductive layer of the HJT battery provided by the embodiment of the utility model is provided with the Ag layer, so that the conductivity of the conductive layer can be improved, and the short-circuit current and the conversion efficiency of the battery are further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to an HJT cell and a photovoltaic module. BACKGROUND

[0002] Heterojunction solar cells (HJT cells) have attracted extensive attention in the photovoltaic field due to their high conversion efficiency and good temperature characteristics. However, the performance of HJT cells is not good, and the reason is that the short-circuit current of the HJT cell is low. The short-circuit current is one of the important parameters for measuring the performance of a solar cell.

[0003] For HJT cells, the conductive layer of the HJT cell needs to have good transmittance to sunlight while conducting electricity. Therefore, a transparent conductive film (TCO) is usually used as the conductive layer, and the conductivity of the TCO needs to be improved to further improve the short-circuit current of the HJT cell.

[0004] It should be noted that the above content is not necessarily prior art, and is not used to limit the patent protection scope of the present application. UTILITY MODEL CONTENT

[0005] The embodiments of the present application provide an HJT cell and a photovoltaic module to solve or alleviate one or more technical problems proposed above.

[0006] The first aspect of the embodiments of the present application provides an HJT cell, comprising:

[0007] a first conductive layer and a second conductive layer arranged oppositely;

[0008] The first conductive layer comprises a composite layer composed of a first transparent conductive layer, an Ag layer and a second transparent conductive layer, and the second conductive layer comprises a third transparent conductive layer.

[0009] The second aspect of the embodiments of the present application provides a photovoltaic module, which comprises the HJT cell as described above.

[0010] The technical solutions of the embodiments of the present application can include the following advantages:

[0011] In the embodiments of the present application, the first conductive layer can comprise a composite layer of a first transparent conductive layer / Ag (silver) layer / second transparent conductive layer. The TCO with a silver layer in the middle can improve the conductivity of the first conductive layer, while suppressing the formation of defects in the TCO layer and reducing the non-radiative recombination centers in the first conductive layer, thereby improving the carrier lifetime, short-circuit current and conversion efficiency. In addition, in the embodiments of the present application, the composite layer is only arranged on the P side, so as to avoid the phenomenon of electric leakage when the conductive layers on both sides simultaneously adopt the composite layer containing the silver layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] In the drawings, like reference numerals refer to like elements throughout the several views. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the application. It should be understood that the drawings are merely schematic and that the application can be embodied in many different forms.

[0013] Figure 1 is a structural schematic diagram of the HJT cell provided by the embodiments of the present application.

[0014] Legend of reference numerals:

[0015] 1-silicon substrate; 201-first hydrogenated amorphous silicon layer; 202-first microcrystalline silicon layer; 3-first doped layer; 401-first transparent conductive layer; 402-silver layer; 403-second transparent conductive layer; 5-first electrode; 601-second hydrogenated amorphous silicon layer; 602-second microcrystalline silicon layer; 7-second doped layer; 8-second conductive layer; 9-second electrode. DETAILED DESCRIPTION

[0016] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings. In the drawings, the size and relative sizes of layers, regions, elements, and the like can be exaggerated for clarity. Identical or similar component elements throughout the several views are denoted by the same or similar reference numerals. The embodiments described below by reference to the drawings are exemplary only, and are not to be construed as limiting the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0017] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0018] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0019] It should be noted that the terms "first", "second", and so on in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0020] In this application, when referring to a numerical interval (i.e., a numerical range), the distribution of the selectable values within the numerical interval is considered continuous and includes both numerical endpoints (i.e., the minimum and maximum values) of the numerical interval and every value between the two numerical endpoints, unless otherwise specified. When a numerical interval refers only to integers within the numerical interval, including both endpoints and every integer between the endpoints, it is equivalent to listing each integer directly, unless otherwise specified. When multiple numerical ranges are provided to describe a feature or characteristic, the numerical ranges can be combined. In other words, unless otherwise indicated, numerical ranges disclosed in this application are to be understood to include any and all sub-ranges subsumed therein. A "value" in a numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. A "numerical interval" is intended to broadly include quantitative intervals such as percentage intervals, ratio intervals, value intervals, etc.

[0021] In a solar cell, the short-circuit current has a huge impact on the solar cell, which is specifically embodied as follows: 1. The short-circuit current is related to the improvement of conversion efficiency, and the conversion efficiency is one of the key indicators for measuring the performance of a solar cell, and the conversion efficiency depends on the fill factor (FF), the open-circuit voltage (V oc ) and the short-circuit current (J sc ). Therefore, improving the short-circuit current can directly improve the conversion efficiency of the cell. 2. The short-circuit current is also closely related to the power generation capacity. Higher short-circuit current means that the battery can generate more power under the same light conditions, which is very beneficial to improving the total power generation of the solar system. 3. When the short-circuit current increases, it means that more current is generated per unit area, and fewer batteries are needed to achieve the same power output, which can simplify system design, reduce connection loss and potential failure types, and improve system reliability. 4. Higher current density means that more power can be generated per square meter of solar panel, so the number of solar panels required for installation can be reduced. This not only saves material costs, but also reduces installation costs and maintenance costs, ultimately helping to reduce the cost of each kilowatt-hour of electricity.

[0022] Embodiments of the present application provide a HJT cell and a photovoltaic module. Based on this, the short-circuit current of the HJT cell is improved. See the following for details.

[0023] In the following, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0024] As shown in Figure 1 , the embodiments of the present application provide a HJT cell.

[0025] The HJT cell can include a first conductive layer and a second conductive layer 8 arranged oppositely;

[0026] The first conductive layer includes a composite layer of a first transparent conductive layer 401, a silver layer 402, and a second transparent conductive layer 403, and the second conductive layer 8 includes a third transparent conductive layer.

[0027] Further, the HJT cell can further include a silicon substrate 1, a first passivation layer, a second passivation layer, a first doped layer 3, a second doped layer 7, a first conductive layer, a second conductive layer 8, a first electrode 5, and a second electrode 9.

[0028] In some embodiments, the silicon substrate 1 includes a first surface and a second surface arranged oppositely; thereby serving as a substrate of the HJT cell to prepare various functional layers thereon. Optionally, the thickness of the silicon substrate 1 can be 100-120 nm. Optionally, the silicon substrate 1 can be selected from N-type monocrystalline silicon. The N-type monocrystalline silicon is phosphorus-doped, and does not have defects such as boron-oxygen complex and boron-iron complex in P-type crystalline silicon, so the HJT cell is immune to LID (light-induced degradation) effect.

[0029] In some embodiments, the first passivation layer is arranged on the first surface; optionally, the first passivation layer can be a hydrogenated amorphous silicon layer, thereby the combination of the silicon substrate 1 and the hydrogenated amorphous silicon layer can effectively passivate defects on the substrate surface, reduce recombination loss, and thus improve the conversion efficiency of the cell. Preferably, the first passivation layer includes a first hydrogenated amorphous silicon layer 201 and a first microcrystalline silicon layer 202 stacked on the silicon substrate 1, thereby the presence of the first microcrystalline silicon layer 202 facilitates subsequent microcrystalline growth and improves electrical conductivity. Further, the thickness of the first hydrogenated amorphous silicon layer 201 is 7-10 nm, and the thickness of the first microcrystalline silicon layer 202 is 2-3 nm. Preferably, the first hydrogenated amorphous silicon layer 201 can include an anti-epitaxy layer and a passivation main body layer; the anti-epitaxy layer can be obtained by pure silane deposition, and has a loose structure and a thickness of 2-3 nm, which can prevent epitaxy; the passivation main body layer has a passivation effect and can be obtained by hydrogen and silane deposition, and has a thickness of 5-8 nm.

[0030] Optionally, the first microcrystalline silicon layer 202 can be formed by laser induction of a hydrogenated amorphous silicon layer. For example, a 2-nm-thick hydrogenated amorphous silicon layer is subjected to laser induction to form a 2-nm-thick first microcrystalline silicon layer 202. Further, the first microcrystalline silicon layer 202 formed by laser induction includes microcrystals and amorphous, the size of the microcrystals is 5-30 nm, and the content of the microcrystals is above 40 wt%. In the embodiments of the present application, the size and content of the microcrystals can be determined by X-ray diffraction method.

[0031] In some embodiments, a second passivation layer is provided on the second surface; optionally, the second passivation layer can be a hydrogenated amorphous silicon layer, whereby the combination of the silicon substrate 1 and the hydrogenated amorphous silicon layer can effectively passivate the defects on the surface of the substrate, reduce the recombination loss, and thus improve the conversion efficiency of the cell. Preferably, the second passivation layer includes a second hydrogenated amorphous silicon layer 601 and a second microcrystalline silicon layer 602 stacked on the silicon substrate 1, whereby the presence of the second microcrystalline silicon layer 602 facilitates the subsequent growth of microcrystals and improves the conductivity. Further, the thickness of the second hydrogenated amorphous silicon layer 601 is 7-10 nm, and the thickness of the second microcrystalline silicon layer 602 is 2-3 nm. Preferably, the second hydrogenated amorphous silicon layer 601 can include an anti-epitaxy layer and a passivation main layer; the anti-epitaxy layer can be obtained by pure silane deposition, the structure and film layer of the anti-epitaxy layer are relatively loose, can prevent epitaxy, and the thickness is 2-3 nm; the passivation main layer plays a passivation role and can be obtained by hydrogen and silane deposition, and the film thickness of the passivation main layer can be 5-8 nm.

[0032] Optionally, the second microcrystalline silicon layer 602 can be formed by laser induction of a hydrogenated amorphous silicon layer. For example, a 2-nm-thick hydrogenated amorphous silicon layer is subjected to laser induction to form a 2-nm-thick second microcrystalline silicon layer 602. Further, the second microcrystalline silicon layer 602 formed by laser induction includes microcrystals and amorphous, the average grain size of the microcrystals is 5-30 nm, and the content of the microcrystals is above 40 wt%. In the embodiments of the present application, the size and content of the microcrystals can be determined by X-ray diffraction.

[0033] In some embodiments, a first doping layer 3 is provided on the side of the first passivation layer away from the first surface; the first doping layer 3 is used to form a heterojunction with the silicon substrate 1, and when the silicon substrate 1 is an N-type single crystal silicon, the first doping layer 3 can be a p-type microcrystalline silicon thin film, whereby a heterojunction is formed to generate carriers when illuminated. Optionally, the thickness of the first doping layer 3 is 25-40 nm.

[0034] In some embodiments, a second doping layer 7 is provided on the side of the second passivation layer away from the second surface; when the silicon substrate 1 is an N-type single crystal silicon, the second doping layer 7 can be an n-type microcrystalline silicon thin film to form a back surface field.

[0035] In some embodiments, the first passivation layer and the second passivation layer can be deposited by chemical vapor deposition (CVD) or the like to deposit a hydrogenated amorphous silicon layer on the front and back surfaces of the silicon substrate, and then the hydrogenated amorphous silicon layer with a predetermined thickness is subjected to laser induction to form a passivation layer including a hydrogenated amorphous silicon layer and a microcrystalline silicon layer.

[0036] In some embodiments, the first doped layer 3 and the second doped layer 7 can be prepared by the following method: a p-type microcrystalline silicon film can be deposited on the first passivation layer as the first doped layer 3 by chemical vapor deposition (CVD) or the like, and an n-type microcrystalline silicon film can be deposited on the second passivation layer as the second doped layer 7.

[0037] In some embodiments, the first conductive layer is arranged on the side of the first doped layer 3 away from the first passivation layer; thus, the first conductive layer is used for transmitting the generated holes. Preferably, the first conductive layer can include a composite layer of a first transparent conductive layer 401 / silver layer 402 / second transparent conductive layer 403; thus, by using a transparent conductive layer (TCO layer) with a silver layer arranged in the middle, the conductivity of the first conductive layer can be improved, the series resistance of the battery can be reduced, and the formation of defects in the TCO layer can be inhibited, thereby reducing the non-radiative recombination centers in the first conductive layer, and further improving the carrier lifetime, short-circuit current, and battery efficiency. The embodiments of the present application only introduce the composite layer on the P side, because the TCO on the N side of the HJT battery is mainly responsible for transmitting light into the battery, while the TCO on the P side mainly assumes the role of reflecting the unabsorbed light back into the battery. If silver is doped in the TCO layer on the N side, the scattering effect of silver particles will change the path of incident light, which not only may affect the direct transmission of light, but also may cause unnecessary light absorption or reflection, affecting the photoelectric conversion efficiency of the battery.

[0038] It is worth noting that the composite layer of the first transparent conductive layer 401 / silver layer 402 / second transparent conductive layer 403 is a composite layer composed of the first transparent conductive layer 401, silver layer 402, and second transparent conductive layer 403 stacked in sequence.

[0039] Further, in the composite layer, the thickness of the Ag layer 402 is 1 nm to 2 nm; and the thickness of the composite layer is 70 nm to 120 nm. Thus, the presence of the Ag layer can not only improve the conductivity of the composite layer, but also does not affect the transmittance of sunlight.

[0040] In some embodiments, the second conductive layer 8 is arranged on the side of the second doped layer away from the second passivation layer; and the second conductive layer 8 can be a third transparent conductive layer. Thus, the phenomenon of electric leakage caused by using the composite layer containing the silver layer on both sides of the conductive layer can be avoided.

[0041] In some embodiments, the first transparent conductive layer 401, the second transparent conductive layer 403 and the third transparent conductive layer can be deposited by at least one of ITO target (indium tin oxide), SCOT target (In2O3:ZrO2:TiO2:Ga2O3 mass ratio of 98.5:0.5:0.5:0.5), IWO target (a target composed of indium oxide and tungsten oxide), and ICO target (indium cerium oxide target), respectively. The silver layer can be obtained by magnetron sputtering using a silver target.

[0042] In some embodiments, the first electrode 5 is arranged on the side of the first conductive layer away from the first doped layer 3; and the second electrode 9 is arranged on the side of the second conductive layer 8 away from the second doped layer 7. The first electrode 5 and the second electrode 9 can be obtained by screen printing, and the paste used can be silver paste, copper paste, etc. Thus, good conductivity is achieved.

[0043] The embodiments of the present application can also provide a preparation method of the HJT cell.

[0044] The preparation method comprises:

[0045] (1) providing an N-type single crystal silicon as a silicon substrate 1, and depositing a hydrogenated amorphous silicon layer on both surfaces of the silicon substrate 1;

[0046] Preferably, the hydrogenated amorphous silicon layer comprises a first hydrogenated amorphous silicon sub-layer, a second hydrogenated amorphous silicon sub-layer and a third hydrogenated amorphous silicon sub-layer. The first hydrogenated amorphous silicon sub-layer is formed by pure silane at a rate of 0.5 nm / min and a film thickness of 2 nm; the second hydrogenated amorphous silicon sub-layer is deposited by hydrogen and silane at a flow ratio of 5:1 at a deposition rate of 0.01 nm / min and a film thickness of 5 nm; and the third hydrogenated amorphous silicon sub-layer is deposited by hydrogen and silane at a flow ratio of 20:1 at a deposition rate of 0.008 nm / min and a film thickness of 3 nm.

[0047] (2) preparing a P-side

[0048] (201) promoting microcrystallization of the third hydrogenated amorphous silicon sub-layer on the front surface by laser ablation to form a first microcrystalline silicon layer 202;

[0049] (202) doping boron on the first microcrystalline silicon layer 202 by vapor deposition to form a first doped layer 3;

[0050] (203) depositing a first transparent conductive layer 401 by magnetron sputtering;

[0051] Preferably, a magnetron sputtering method can be used to deposit a 2nm-thick TCO seed layer at a power of 5MW and a 30nm-thick TCO layer at a power of 12MW, which together serve as the first transparent conductive layer 401;

[0052] (204) Depositing a silver layer, using a silver target to deposit a 1nm-thick silver layer 402;

[0053] (205) Depositing a 40nm-thick second transparent conductive layer 403 using a PVD machine at a power of 10MW;

[0054] (206) Screen printing a silver electrode

[0055] (3) Preparing the N side

[0056] (301) Using a laser ablation method to microcrystallize the other side of the third hydrogenated amorphous silicon sub-layer to form a second microcrystalline silicon layer 602;

[0057] (302) Doping phosphorus in the second microcrystalline silicon layer 602 using a vapor deposition method to form a second doped layer 7;

[0058] (303) Depositing a third transparent conductive layer using a magnetron sputtering method to form a second conductive layer 8;

[0059] (304) Screen printing a silver electrode on the second conductive layer 8.

[0060] The performance of the HJT cell prepared according to the method of the present application will be tested below.

[0061]

Example 1

[0062] The specific preparation process is as follows:

[0063] (1) Providing an N-type monocrystalline silicon as a silicon substrate 1, and depositing a hydrogenated amorphous silicon layer on both surfaces of the silicon substrate 1, specifically, depositing a 2nm-thick first hydrogenated amorphous silicon sub-layer using pure silane, then depositing a 5nm-thick second hydrogenated amorphous silicon sub-layer using hydrogen and silane at a flow ratio of 5:1, and then depositing a 2nm-thick third hydrogenated amorphous silicon sub-layer using hydrogen at a flow ratio of 20:1;

[0064] (2) Preparing the P side

[0065] (201) Using a laser ablation method to promote microcrystallization of the third hydrogenated amorphous silicon sub-layer on the front side to form a first microcrystalline silicon layer 202;

[0066] (202) Doping boron on the first microcrystalline silicon layer 202 using a vapor deposition method to form a first doped layer 3;

[0067] (203) A 2 nm thick ITO seed layer is deposited using a 5 MW power, and a 30 nm thick ITO layer is deposited using a 12 MW power, both as the first transparent conductive layer 401;

[0068] (204) A 1 nm silver layer 402 is deposited using a silver target;

[0069] (205) A 40 nm ITO layer is deposited using a magnetron sputtering at a 10 MW power, as the second transparent conductive layer 403;

[0070] (206) A silver electrode, i.e. the first electrode 5, is screen printed;

[0071] (3) Preparation of the N side

[0072] (301) The third hydrogenated amorphous silicon sub-layer on the other side is microcrystallized by laser ablation to form a second microcrystalline silicon layer 602;

[0073] (302) A second doped layer 7 is formed by doping the second microcrystalline silicon layer 602 with phosphorus using a vapor deposition method;

[0074] (303) A third ITO layer is deposited to form a second conductive layer 8;

[0075] (304) A silver electrode, i.e. the second electrode 9, is screen printed on the second conductive layer 8.

[0076]

Example 2

[0077] The other operations are the same as in Example 1, except that step (204) is replaced by depositing a 2 nm silver layer 402 using a silver target.

[0078]

Example 3

[0079] The other operations are the same as in Example 1, except that step (204) is replaced by depositing a 3 nm silver layer 402 using a silver target.

[0080]

Comparative Example 1

[0081] The other operations are the same as in Example 1, except that step (204) is omitted.

[0082]

Comparative Example 2

[0083] The other operations are the same as in Example 1, except that step (303) is replaced by steps (203)-(205).

[0084]

Test Example

[0085] The HJT cells of Examples 1-3 and the HJT cells of Comparative Examples 1-2 were subjected to IV testing, and the testing conditions were: AM1.5G spectrum, standard testing conditions (STC), testing at 25°C, and the testing data is shown in Table 1.

[0086] Table 1

[0087]

[0088] As can be seen from Table 1 above, the short-circuit current and the conversion efficiency of Examples 1 and 2 are greatly improved compared with Comparative Examples 1 and 2. Comparative Example 2 uses silver-doped TCO on both sides, which has a great negative impact on the short-circuit current.

[0089] The embodiments of the present application can also provide a photovoltaic module (not shown), which comprises the HJT cell as described above. The HJT cell can be connected in series and / or parallel with one or more other solar cells in a preset manner. Wherein, a plurality of cells can form a cell string, and adjacent cells can be connected together by series welding.

[0090] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. The orientation terms "inner" and "outer" refer to the inner and outer of the profile of each component itself. For example, if the device in the drawing is inverted, the device described as "above" or "on" other devices or structures will be positioned "below" or "under" the other devices or structures. Thus, the exemplary term "above" can include both "above" and "below" orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0091] It should also be noted that "one embodiment", "another embodiment", "embodiment", and the like in the present application refer to specific features, structures or characteristics described in conjunction with the embodiment, which are included in at least one embodiment described generally in the present application. The same description appearing in several places in the specification does not necessarily refer to the same embodiment. Further, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the implementation of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of the present application.

[0092] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0093] It should be further noted that the above is only the preferred embodiment of the application, and does not limit the patent protection scope of the application, and any equivalent structure or equivalent process transformation using the content of the application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. An HJT battery, characterized in that, include: The first conductive layer and the second conductive layer are positioned opposite to each other; The first conductive layer comprises a composite layer formed by stacking a first transparent conductive layer, an Ag layer, and a second transparent conductive layer, and the second conductive layer comprises a third transparent conductive layer.

2. The HJT battery according to claim 1, characterized in that, The HJT battery also includes: A silicon substrate, the silicon substrate including a first surface and a second surface disposed opposite to each other; A first passivation layer is disposed on the first surface; A second passivation layer is disposed on the second surface; A first doped layer is disposed on the side of the first passivation layer away from the first surface; The second doped layer is disposed on the side of the second passivation layer away from the second surface; The first conductive layer is disposed on the side of the first doped layer away from the first passivation layer; the second conductive layer is disposed on the side of the second doped layer away from the second passivation layer; and the first doped layer forms a heterojunction with the silicon substrate.

3. The HJT battery according to claim 1 or 2, characterized in that, In the composite layer, the thickness of the Ag layer is 1 nm to 2 nm; and / or The thickness of the composite layer is 70nm to 120nm.

4. The HJT battery according to claim 2, characterized in that, The first passivation layer and the second passivation layer each independently comprise hydrogenated amorphous silicon.

5. The HJT battery according to claim 2, characterized in that, The first passivation layer and the second passivation layer each independently comprise a hydrogenated amorphous silicon layer and a microcrystalline silicon layer stacked on the silicon substrate.

6. The HJT battery according to claim 5, characterized in that, The thickness of the hydrogenated amorphous silicon layer is 7nm~10nm; and / or The thickness of the microcrystalline silicon layer is 2nm~3nm.

7. The HJT battery according to claim 2, characterized in that, The materials of the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer each independently include at least one of indium tin oxide, SCOT, IWO, and indium cerium oxide.

8. The HJT battery according to claim 2, characterized in that, The silicon substrate includes N-type monocrystalline silicon.

9. The HJT battery according to claim 2, characterized in that, The HJT battery also includes: The first electrode is disposed on the side of the first conductive layer away from the first doped layer; The second electrode is disposed on the side of the second conductive layer away from the second doped layer.

10. A photovoltaic module, characterized in that, The photovoltaic module includes the HJT battery as described in any one of claims 1 to 9.

Images