General computing circuit and computing equipment for liquid state machine and Isin annealing

Abstract

The utility model relates to the technical field of circuits, in particular to a general computing circuit and computing equipment for a liquid state machine and Isin annealing. Wherein the general calculation circuit comprises a processor, a selector, a linear feedback shift register, a weight memory, a membrane potential-local field calculation array, a membrane potential-local field memory, a comparator array, a neuron-spin state memory, a pulse counter, a dynamic multiply-accumulate array, an index calculation array and an output module; according to the general calculation circuit provided by the utility model, the same hardware circuit is shared to accelerate the processing of the liquid state machine and the Isin annealing task, so that not only can the identification, classification and prediction problems be quickly processed, but also the combinatorial optimization problem can be quickly solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of circuit, especially relates to a liquid state machine and ising annealing general computing circuit and computing device. BACKGROUND

[0002] With the development of artificial intelligence and optimization computing, liquid state machine (LSM) and ising annealing have been widely applied in many fields. Liquid state machine is a computing model based on spiking neural network, commonly used for processing time series data and pattern recognition tasks, while ising annealing is a computing method for solving combinatorial optimization problems, which finds the optimal solution by simulating the annealing process of physical systems. Although these two computing models perform well in their respective fields, the existing computing circuit design has obvious limitations. The current liquid state machine computing circuit and ising annealing computing circuit are usually designed independently, and each circuit can only work in a specific mode. This specialization leads to waste of resources and increase in cost. In addition, due to strong specialization, the existing computing circuit cannot be flexibly switched between different modes, and users need to purchase and maintain different hardware devices for each mode, increasing the complexity and maintenance difficulty of the system. At the same time, the existing computing circuit is usually composed of multiple independent modules, each module is responsible for a specific function. This low integration design not only increases the size and power consumption of the circuit, but also reduces the overall performance and reliability of the system. SUMMARY

[0003] To solve the technical problem that the existing liquid state machine and ising annealing computing circuit are not universal, the utility model provides a liquid state machine and ising annealing general computing circuit and computing device.

[0004] The utility model discloses a technical problem's scheme is to provide a liquid state machine and isssing annealing general computing circuit, including treater, selector, linear feedback shift register, weight storage, membrane potential - local field computing array, membrane potential - local field memory, comparator array, neuron - spin state memory, pulse counter, dynamic multiply - accumulate array, exponential computing array and output module, when computing circuit is in liquid state machine mode, the output of treater is connected with the input of selector and linear feedback shift register, the output of selector is connected with the input of weight storage and membrane potential - local field computing array, the output of linear feedback shift register is connected with the input of weight storage, the output of weight storage is connected with the input of membrane potential - local field computing array and dynamic multiply - accumulate array respectively, the input and output of membrane potential - local field computing array are connected with the output and input of membrane potential - local field memory respectively, the output of membrane potential - local field memory is connected with the input of comparator array, the output of comparator array is connected with the input of neuron - spin state memory, the output of neuron - spin state memory is connected with the input of pulse counter, the output of pulse counter is connected with the input of dynamic multiply - accumulate array, the output of dynamic multiply - accumulate array is connected with the input of exponential computing array, the output of exponential computing array is connected with the input of output module, when computing circuit is in isssing annealing mode, the output of treater is connected with the input of selector and linear feedback shift register, the output of selector is connected with the input of weight storage, the output of linear feedback shift register is connected with the input of comparator array, the output of weight storage is connected with the input of membrane potential - local field computing array, the output of membrane potential - local field computing array is connected with the input of membrane potential - local field memory, the output of membrane potential - local field memory is connected with the input of dynamic multiply - accumulate array, the output of comparator array is connected with the input of neuron - spin state memory, the output of neuron - spin state memory is connected with the input of membrane potential - local field computing array, the output of dynamic multiply - accumulate array is connected with the input of exponential computing array, the output of exponential computing array is connected with the input of comparator array and output module respectively.

[0005] Preferably, the weight storage includes a first block of storage, a second block of storage, and a third block of storage; when the computing circuit is in different modes, the first block of storage, the second block of storage, and the third block of storage store different information.

[0006] Preferably, the membrane potential-local field computing array comprises a plurality of computing units, each computing unit comprising an adder, a selector and a NOT gate.

[0007] Preferably, the membrane potential-local field computing array comprises an input pulse port, a weight value port, a state information port, an old result port and a new membrane potential / local field value port; when the computing circuit is in the liquid state machine mode, the input pulse port is used for receiving an input pulse signal from a processor; the weight value port is used for receiving a weight value from a weight storage; the state information port is used for receiving neuron-spin state information from a neuron-spin state storage; the old result port is used for receiving an old membrane potential from a membrane potential-local field storage; and the new membrane potential / local field value port is used for outputting a newly calculated membrane potential value; when the computing circuit is in the Ising annealing mode, the input pulse port is used for receiving a 0 value signal; the weight value port is used for receiving an inter-spin coupling weight value from the weight storage; the state information port is used for receiving spin state information from the neuron-spin state storage; the old result port is used for receiving an old local field value from the membrane potential-local field storage; and the new membrane potential / local field value port is used for outputting a newly calculated local field value.

[0008] Preferably, the input ends of the membrane potential-local field computing array, the comparator array and the dynamic multiply-accumulate array are respectively provided with the selectors.

[0009] Preferably, when the computing circuit is in the liquid state machine mode, the neuron-spin state storage is used for storing a pulse generation state of each neuron; and when the computing circuit is in the Ising annealing mode, the neuron-spin state storage is used for storing a current state of each spin.

[0010] Preferably, the dynamic multiply-accumulate array comprises a plurality of multiply-accumulate units, and each multiply-accumulate unit comprises a multiplier, an adder, a register, a selector, a shifter and a NOT gate.

[0011] Preferably, the output module comprises a first-in-first-out buffer.

[0012] Preferably, the output module further comprises a data sending unit, an input end of the data sending unit being connected with the first-in-first-out buffer, and an output end of the data sending unit being connected with the processor.

[0013] Another scheme for solving the technical problem of the utility model is to provide a computing device comprising the universal computing circuit as described above.

[0014] Compared with the prior art, the liquid state machine and Ising annealing universal computing circuit and computing device provided by the utility model have the following advantages:

[0015] 1. The utility model embodiment provides a kind of liquid state machine and ising annealing general computing circuit, and the same hardware circuit is used to accelerate processing liquid state machine and ising annealing task, not only can the identification, classification and prediction problem be quickly handled, but also can quickly solve combination optimization problem.Specifically, the embodiment is by pulse neuron weight and spin connection coefficient share the same weight storage, pulse neuron membrane potential and spin local field share the same membrane potential-local field memory, pulse neuron pulse generation and spin state share the same neuron-spin state memory, reduce memory resource consumption;Random weight generation between liquid layer pulse neuron and spin state random flip share the same linear feedback shift register, neuron membrane potential calculation and spin local field calculation share the same membrane potential-local field calculation array, liquid layer pulse neuron pulse generation and spin state calculation share the same comparator array, output layer neuron multiplication-accumulation calculation and spin energy difference and its temperature multiplication calculation share the same dynamic multiplication-accumulation array, output layer neuron nonlinear activation calculation and spin flip probability calculation share the same exponential calculation array, reduce the consumption of computing resources.

[0016] 2. In the general computing circuit of the utility model embodiment, the weight storage includes first block storage, second block storage and third block storage, different information is stored according to different modes, to ensure the efficient operation of the circuit in different modes;By block storage, storage resources are reasonably utilized, and storage efficiency is improved.

[0017] 3. In the general computing circuit of the utility model embodiment, multiple computing units can process multiple computing tasks in parallel, improve the efficiency and speed of calculation, shorten the calculation time;Through adder, the accuracy of membrane potential and local field calculation is ensured, calculation error is reduced, and the reliability of calculation result is improved;Selector makes the computing unit can select appropriate calculation data according to different modes and input data, improves the flexibility and adaptability of the circuit, so that the circuit can quickly adapt to different computing tasks.

[0018] 4. In the general computing circuit of the utility model embodiment, the membrane potential-local field calculation array is designed to include multiple ports, each port has different functions in different modes, so that the membrane potential-local field calculation array can flexibly handle data input and output in different modes;Through the accurate control of multiple ports, the accuracy and consistency of input data, weight data, state data and old result data are ensured, so as to improve the precision and reliability of calculation result.

[0019] 5. In the general computing circuit of the embodiment of the present application, the selector enables the membrane potential-local field computing array, the comparator array and the dynamic multiply-accumulate array to select appropriate input data according to different modes and task requirements, thereby improving the flexibility and adaptability of the circuit. Specifically, for the membrane potential-local field computing array, the selector can select appropriate input data such as input pulses and weight values according to different modes, thereby ensuring that the computing array can receive correct input data according to different computing requirements; for the comparator array, the selector can select different input data for comparison, such as the membrane potential data of the membrane potential-local field memory and the membrane potential threshold, thereby ensuring that the comparator can accurately compare according to different modes; for the dynamic multiply-accumulate array, the selector can select different input data for multiply-accumulate operation, such as the output value of the weight value and the pulse counter, thereby ensuring that the dynamic multiply-accumulate array can efficiently operate according to different computing requirements.

[0020] 6. In the general computing circuit of the embodiment of the present application, the same neuron-spin state memory is used to store different types of state information in different modes, thereby reducing the redundancy of the memory and optimizing the use of storage resources; when switching between different modes, no additional memory switching and initialization operation is required, thereby reducing the switching time and overhead.

[0021] 7. In the general computing circuit of the embodiment of the present application, the combination of the multiplier and the adder ensures the accuracy of the multiplication and accumulation operation, reduces the calculation error, and improves the reliability of the calculation result; the register is used to store the intermediate result, thereby reducing the dependence on external memory and improving the efficiency of the calculation.

[0022] 8. In the general computing circuit of the embodiment of the present application, the buffer is arranged in the output module, thereby smoothing the data flow, reducing the burstiness and discontinuity of data transmission, and improving the stability of data transmission; the first-in first-out principle is followed, thereby ensuring that the data is output in order and avoiding data out-of-order and loss.

[0023] 9. The embodiment of the present application further provides a computing device comprising the general computing circuit as described above, and therefore has the beneficial effects consistent with the general computing circuit as described above, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a connection diagram of a general computing circuit provided by the embodiment of the present application Figure 1 .

[0025] Figure 2 is a connection diagram of part of modules of a general computing circuit provided by the embodiment of the present application Figure 1 .

[0026] Figure 3 is a connection diagram of a general computing circuit part module provided by the embodiment of the utility model Figure 2 .

[0027] Figure 4 is a schematic diagram of a membrane potential-local field computing array of a general computing circuit provided by the embodiment of the utility model

[0028] Figure 5 is a connection diagram of a general computing circuit part module provided by the embodiment of the utility model Figure 3 .

[0029] Figure 6 is a schematic diagram of a dynamic multiply-accumulate array of a general computing circuit provided by the embodiment of the utility model

[0030] Figure 7 is a connection diagram of a general computing circuit provided by the embodiment of the utility model Figure 2 .

[0031] Figure 8 is a block diagram of a computing device provided by the embodiment of the utility model

[0032] The drawing mark explanation is as follows:

[0033] 100, general computing circuit, 200, computing device

[0034] 1, processor, 2, linear feedback shift register, 3, weight storage, 4, membrane potential-local field computing array, 5, membrane potential-local field storage, 6, comparator array, 7, neuron-spin state storage, 8, pulse counter, 9, dynamic multiply-accumulate array, 10, exponential computing array, 11, output module, 12, selector Specific implementation

[0035] In order to make the purpose of the utility model, technical scheme and advantage more clear and obvious, the utility model is further explained in detail below by combining with the drawing and implementation example.It should be understood that the specific implementation example described here is only used to explain the utility model, and is not used to limit the utility model.

[0036] It should be noted that the terms "first" and "second" in the specification and claims of the utility model are used to distinguish different objects, and are not used to describe a specific order.

[0037] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In cases where one element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. As used herein the terms "upper", "lower", "right", "left", "front", "rear", "top", "bottom", "over", "under", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like are used for description only and are not intended to refer to an orientation or position in which the device, element or component is used, constructed or operated.

[0038] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0039] In addition, in addition to being used to indicate the orientation or positional relationship, the above-mentioned terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0040] In addition, the terms "mounting", "setting", "provided with", "connection", "connected" should be understood broadly. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0041] Liquid State Machine (LSM) is a computing model based on Spiking Neural Network (SNN). It simulates the neuron and synapse activity of the biological brain, and makes calculations and decisions by processing time-series data. It usually includes an input layer, a liquid layer and an output layer. The input layer receives external input signals such as sensor data or time series data; the liquid layer is composed of a large number of interconnected spiking neurons, forming a highly dynamic network. The connections between these neurons are random, forming a "liquid" network structure; the output layer extracts information from the liquid layer, and performs classification, regression or other tasks. The output layer is usually a simple linear classifier or regressor.

[0042] Ising Annealing is a computational method for solving combinatorial optimization problems, inspired by the Ising Model in physics. The Ising Model describes the interactions of spins in a magnetic material, finding the global optimal solution by simulating the annealing process of the system. Each spin in the initial state (which can be +1 or -1) is randomly initialized; by defining an energy function, representing the total energy of the system. The energy function usually includes the interaction term between spins and the external magnetic field term; by gradually lowering the temperature (or increasing the annealing time), the system gradually tends to the lowest energy state. At each temperature, the spin will flip according to certain probability rules (such as the Metropolis-Hastings algorithm). Finally, the system converges to a lower energy state, which is the approximate optimal solution of the problem.

[0043] Please refer to Figures 1 to 3 The utility model first embodiment provides a kind of liquid state machine and Ising Annealing general computing circuit 100, including processor 1, selector 12, linear feedback shift register 2, weight storage 3, membrane potential-local field calculation array 4, membrane potential-local field storage 5, comparator array 6, neuron-spin state storage 7, pulse counter 8, dynamic multiply-accumulate array 9, exponential calculation array 10 and output module 11;

[0044] When the computing circuit is in the liquid state machine mode, the output end of the processor 1 is connected with the input end of the selector 12 and the linear feedback shift register 2, the output end of the selector 12 is connected with the input end of the weight storage 3 and the membrane potential-local field calculation array 4;The output end of the linear feedback shift register 2 is connected with the input end of the weight storage 3;The output end of the weight storage 3 is connected with the input end of the membrane potential-local field calculation array 4 and the dynamic multiply-accumulate array 9 respectively;The input end and the output end of the membrane potential-local field calculation array 4 are connected with the output end and the input end of the membrane potential-local field storage 5 respectively;The output end of the membrane potential-local field storage 5 is connected with the input end of the comparator array 6;The output end of the comparator array 6 is connected with the input end of the neuron-spin state storage 7;The output end of the neuron-spin state storage 7 is connected with the input end of the pulse counter 8;The output end of the pulse counter 8 is connected with the input end of the dynamic multiply-accumulate array 9;The output end of the dynamic multiply-accumulate array 9 is connected with the input end of the exponential calculation array 10;The output end of the exponential calculation array 10 is connected with the input end of the output module 11;

[0045] When the computing circuit is in the Ising annealing mode, the output end of the processor 1 is connected with the input end of the selector 12 and the linear feedback shift register 2, the output end of the selector 12 is connected with the input end of the weight storage 3; the output end of the linear feedback shift register 2 is connected with the input end of the comparator array 6; the output end of the weight storage 3 is connected with the input end of the membrane potential-local field computing array 4; the output end of the membrane potential-local field computing array 4 is connected with the input end of the membrane potential-local field storage 5; the output end of the membrane potential-local field storage 5 is connected with the input end of the dynamic multiply-accumulate array 9; the output end of the comparator array 6 is connected with the input end of the neuron-spin state storage 7; the output end of the neuron-spin state storage 7 is connected with the input end of the membrane potential-local field computing array 4; the output end of the dynamic multiply-accumulate array 9 is connected with the input end of the exponential computing array 10; the output end of the exponential computing array 10 is connected with the input end of the output module 11 and the comparator array 6 respectively.

[0046] It can be understood that the liquid state machine and the Ising annealing general computing circuit 100 provided by the embodiment of the utility model can accelerate the processing of the liquid state machine and the Ising annealing task by using the same hardware circuit, can not only quickly process the identification, classification and prediction problems, but also can quickly solve the combinatorial optimization problems. Specifically, the same weight storage 3 is shared by the pulse neuron weight and the spin connection coefficient, the same membrane potential-local field storage 5 is shared by the pulse neuron membrane potential and the spin local field, and the same neuron-spin state storage 7 is shared by the pulse neuron pulse generation condition and the spin state, so that the memory resource consumption is reduced; the same linear feedback shift register 2 is shared by the random weight generation between the liquid layer pulse neurons and the spin state random flip, the same membrane potential-local field computing array 4 is shared by the neuron membrane potential calculation and the spin local field calculation, the same comparator array 6 is shared by the liquid layer pulse neuron pulse generation and the spin state calculation, the same dynamic multiply-accumulate array 9 is shared by the output layer neuron multiply-accumulate calculation and the spin energy difference and its temperature multiplication calculation, the same exponential computing array 10 is shared by the output layer neuron nonlinear activation calculation and the spin flip probability calculation, so that the computing resource consumption is reduced.

[0047] Specifically, in the embodiment, the processor 1 is an ARM processor 1, and the comparator array 6 is a two-input comparator array 6.

[0048] It should be noted that, in the embodiment, the processor 1, the linear feedback shift register 2, the weight storage 3, the membrane potential-local field computing array 4, the membrane potential-local field storage 5, the comparator array 6, the neuron-spin state storage 7, the dynamic multiply-accumulate array 9, the exponential computing array 10 and the output module 11 are common modules.

[0049] Here, the common module refers to the hardware modules that are used by the general-purpose computing circuit 100 regardless of whether it is in the liquid state machine mode or the Ising annealing mode.

[0050] Specifically, the processor 1 serves as a central controller that receives user configuration information. A central controller is needed to manage the overall process and configuration information regardless of whether it is in the liquid state machine mode or the Ising annealing mode.

[0051] Specifically, the linear feedback shift register 2 (LFSR) is used to generate random numbers. In the liquid state machine mode, the random numbers generated by the linear feedback shift register 2 are used to generate random weights for the liquid layer pulse neurons. In the Ising annealing mode, the random numbers generated by the linear feedback shift register 2 are used to generate random flip probabilities.

[0052] Specifically, the weight storage 3 is used to store the coupling weights between neurons or the connection coefficients between spins. The weight storage 3 stores different types of data in different modes, but is physically the same memory, reducing the occupation of hardware resources.

[0053] Specifically, the membrane potential-local field calculation array 4 is responsible for calculating the membrane potential of neurons in the liquid state machine mode and the local field of spins in the Ising annealing mode.

[0054] Specifically, the membrane potential-local field storage 5 is used to store the real-time membrane potential of neurons or the local field value of spins. The membrane potential and the local field have similar storage requirements in terms of physics, and sharing the same memory can reduce the waste of hardware resources.

[0055] Specifically, the comparator array 6 is used to compare the membrane potential with the threshold value to determine whether to generate a pulse in the liquid state machine mode, and to compare the spin flip probability with the random number to determine whether to flip the spin state in the Ising annealing mode. Understandably, the basic function of the comparator is numerical comparison, which can be reused in both the LSM mode and the Ising annealing mode.

[0056] Specifically, the neuron-spin state storage 7 is used to store the pulse generation state of neurons or the state of spins. The state storage requirement is similar in both modes, and sharing the same memory can simplify hardware design.

[0057] Specifically, the dynamic multiply-accumulate array 9 is used to calculate the multiply-accumulate value of the output layer neurons in the liquid state machine mode, and to calculate the spin energy change amount and its multiplication result with temperature in the Ising annealing mode. The multiply-accumulate operation is applied in both modes, and sharing the same array can save hardware resources.

[0058] Specifically, the exponent calculation array 10 is used to calculate the nonlinear activation value of the output layer neuron in the liquid state machine mode, and is used to calculate the probability of spin state flip in the Ising annealing mode. Exponent operation is applied in both modes, and sharing the same array can improve resource utilization.

[0059] Specifically, outputting the result through the output module 11 is necessary in both modes, and sharing the same output module 11 can simplify the design.

[0060] It should be noted that the pulse counter 8 is a non-shared module; a non-shared module means that the calculation circuit will only use these hardware modules in one state.

[0061] Specifically, the pulse counter 8 is used to count the number of pulses and complete the conversion of pulse information to real numbers. The pulse counter 8 is used to count the number of pulses in the liquid state machine mode, and there is no similar requirement in the Ising annealing mode, so it is not necessary to share.

[0062] As a possible implementation, the weight storage 3 includes a first block of storage, a second block of storage, and a third block of storage; the information stored in the first block of storage, the second block of storage, and the third block of storage is different when the calculation circuit is in different modes.

[0063] It can be understood that the embodiment reasonably utilizes storage resources by block storage, thereby improving the storage efficiency of the general-purpose calculation circuit 100.

[0064] As a possible implementation, in the liquid state machine mode, the first block of storage stores the coupling weights between the 128 pulse neurons of the input layer and the 1024 neurons of the liquid layer, the second block of storage stores the coupling weights between the 1024 neurons of the liquid layer, and the third block of storage stores the interconnection weights between the 1024 neurons of the liquid layer and the 1024 neurons of the output layer.

[0065] In the Ising annealing mode, the first block of storage stores the external field coefficients of the 1024 spins, and the second block of storage and the third block of storage are all used to store the connection coefficients between the 1024 spins, thereby reducing the waste of storage resources.

[0066] As a possible implementation, the membrane potential-local field calculation array 4 includes a plurality of calculation units, and each calculation unit includes an adder, a selector 12, and a NOT gate.

[0067] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, multiple computing units can process multiple computing tasks in parallel, improve the efficiency and speed of computing, and shorten the computing time; through the adder, the accuracy of membrane potential and local field calculation is ensured, the calculation error is reduced, and the reliability of the calculation result is improved; the selector 12 enables the computing unit to select appropriate calculation data according to different modes and input data, improves the flexibility and adaptability of the circuit, and enables the circuit to quickly adapt to different computing tasks; the NOT gate is used for logically inverting the input signal, can be used for realizing negative weight or inversion operation, and further increases the flexibility and diversity of the calculation.

[0068] As a feasible implementation manner, the membrane potential-local field calculation array 4 includes an input pulse port, a weight value port, a state information port, an old result port and a new membrane potential / local field value port; when the computing circuit is in a liquid state machine mode, the input pulse port is used for receiving an input pulse signal from the processor 1; the weight value port is used for receiving a weight value from the weight storage 3; the state information port is used for receiving neuron pulse generation state information from the neuron-spin state storage 7; the old result port is used for receiving an old membrane potential value from the membrane potential-local field storage 5; and the new membrane potential / local field value port is used for outputting a new membrane potential value obtained through calculation; when the computing circuit is in an Ising annealing mode, the input pulse port is used for receiving a 0 value signal; the weight value port is used for receiving a weight value from the weight storage 3; the state information port is used for receiving spin state information from the neuron-spin state storage 7; the old result port is used for receiving an old local field value from the membrane potential-local field storage 5; and the new membrane potential / local field value port is used for outputting a new local field value obtained through calculation.

[0069] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, the membrane potential-local field calculation array 4 is designed to include multiple ports, each port has different functions in different modes, so that the membrane potential-local field calculation array 4 can flexibly process data input and output in different modes; through accurate control of the multiple ports, the accuracy and consistency of the input data, the weight data, the state data and the old result data are ensured, so that the precision and reliability of the calculation result are improved.

[0070] As a feasible implementation manner, the input ends of the membrane potential-local field calculation array 4, the comparator array 6 and the dynamic multiply-accumulate array 9 are respectively provided with the selector 12.

[0071] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, the selector 12 enables the membrane potential-local field computing array 4, the comparator array 6 and the dynamic multiply-accumulate array 9 to select appropriate input data according to different modes and task requirements, improving the flexibility and adaptability of the circuit. Specifically, for the membrane potential-local field computing array 4, the selector 12 can select appropriate input data such as input pulses and weight values according to different modes, ensuring that the computing array can receive correct input data according to different computing requirements; for the comparator array 6, the selector 12 can select different input data for comparison, such as the membrane potential data of the membrane potential-local field memory 5 and the membrane potential threshold value, ensuring that the comparator can accurately compare according to different modes; for the dynamic multiply-accumulate array 9, the selector 12 can select different input data for multiply-accumulate operation, such as the output of the weight value and the pulse counter 8, ensuring that the dynamic multiply-accumulate array 9 can perform efficient operation according to different computing requirements.

[0072] Please combine Figure 1 and Figure 4 , as a feasible implementation, the computing unit is composed of 1 selector 12, 1 NOT gate and 1 adder. As shown in the figure, the pulse and state signal enters the sub-computing unit through the pulse+state port; according to the pulse and state signal, the selector 12 will select the corresponding input data value (one of the weight value, the weight inversion value and the 0 value); the NOT gate performs logical inversion operation on the received weight value; the adder performs addition operation on the selection result of the selector and the old result value of the old result input port, to obtain the new computing result; the computing result is output through the new result output port.

[0073] As a feasible implementation, when the computing circuit is in the liquid state machine mode, the neuron-spin state memory 7 is used to store the pulse generation state of each neuron; when the computing circuit is in the Ising annealing mode, the neuron-spin state memory 7 is used to store the current state of each spin.

[0074] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, the same neuron-spin state memory 7 is used to store different types of state information in different modes, reducing the redundancy of the memory and optimizing the use of storage resources; when switching between different modes, no additional memory switching and initialization operation is required, reducing the switching time and overhead.

[0075] Please combine Figure 1 , Figure 5 and Figure 6 , as a feasible implementation, the dynamic multiply-accumulate array 9 includes a plurality of multiply-accumulate units, and the multiply-accumulate unit includes a multiplier, an adder, a register, a shifter and a NOT gate.

[0076] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, the accuracy of multiplication and accumulation operation is ensured, the calculation error is reduced, and the reliability of the calculation result is improved through the combination of the multiplier and the adder; the register is used for storing the intermediate result, the dependence on the external memory is reduced, and the calculation efficiency is improved; the shifter is used for bit shift operation on data, the fast multiplication operation can be realized, the NOT gate is used for logical inversion on the input signal, and the negative weight or inversion operation can be realized, and the flexibility and diversity of the calculation are increased.

[0077] As a feasible implementation manner, the dynamic multiply-accumulate array 9 is composed of 1024 sub-computing units, each of which is composed of 1 right shift register (moving 1 bit), 1 NOT gate, 2 selectors 12, 1 multiplier, 1 adder and 1 register.

[0078] As a feasible implementation manner, the output module 11 comprises a first-in first-out buffer.

[0079] It can be understood that, in the universal computing circuit 100 of the embodiment of the utility model, the stability of data transmission is improved by setting the buffer in the output module 11, the burstness and discontinuity of data transmission are reduced, the data are output in sequence according to the principle of first-in first-out, and the data out-of-order and loss are avoided.

[0080] As a feasible implementation manner, the output module 11 further comprises a data sending unit, an input end of the data sending unit is connected with the first-in first-out buffer, and an output end of the data sending unit is connected with the processor 1.

[0081] Please combine Figures 1 to 7In this embodiment, the operation process / principle of the general computing circuit 100 in the liquid state machine mode is described as follows: the linear feedback shift register 2 generates a plurality of random numbers and stores them in the first block and the second block of the weight storage 3. The processor 1 receives the weight values of the liquid layer-output layer from the user and stores them in the third block of the weight storage 3. The membrane potential-local field storage 5 stores the real-time membrane potential values of 1024 pulse neurons. The neuron-spin state storage 7 stores the real-time pulse generation state (pulse generation: 1 or no pulse generation: 0) of 1024 pulse neurons. The membrane potential-local field computing array 4 is composed of four input ports (pulse, weight, state, and old result), one new result output port, and 1024 sub-computing units. The pulse port receives the input pulse generated from the processor 1, the weight port receives the weight data read from the weight storage 3, the state port receives the liquid layer neuron state from the neuron-spin state storage 7, and the old result port receives the neuron real-time membrane potential value stored in the membrane potential-local field storage 5.

[0082] When the input pulse is 0, the selector 12 transmits the 0 value to one input port of the adder, otherwise, the input weight value is transmitted to the same input port of the adder. At the same time, the input real-time membrane potential value is transmitted to the other input port of the selector 12, then the adder performs the addition operation on the two input data and stores the calculation result in the membrane potential-local field memory 5. Through multiple times of the above operation, the membrane potential value of the next time step of the liquid layer neuron is finally generated. All the 1024 computing units run according to the above process, and finally complete the latest membrane potential calculation of the 1024 neurons of the liquid layer. The two-input comparator array 6 receives the real-time membrane potential value of the neuron from the membrane potential-local field memory 5, and compares these values with the pre-defined membrane potential threshold through 1024 comparators. If the real-time membrane potential value is less than the membrane potential threshold, no pulse will be generated (represented by the number 0), otherwise, a pulse will be generated (represented by the number 1). Then, the pulse generation information is stored to the neuron-spin state memory 7. The pulse counter 8 counts the number of pulses generated by the 1024 pulse neurons of the liquid layer in one time step, and completes the conversion of pulse information to real number. The dynamic multiply-accumulate array 9 calculates the multiply-accumulate value of the output layer neuron according to the statistical result of the pulse counter 8 and the weight value between the liquid layer and the output layer of the weight storage 3. The statistical result of the pulse counter 8 is transmitted to one input port of the multiplier; at the same time, the weight value is transmitted to the other input port of the multiplier. Then, the multiplier completes the multiplication operation of the two numbers, and adds the previous result through the adder to complete the multiply-accumulate operation; finally, the calculation result is transmitted to the exponential calculation array 10. The 1024 sub-computing modules run in parallel and complete the multiply-accumulate operation of the 1024 neurons of the output layer in parallel. The exponential calculation array 10 performs exponential operation on the result generated from the dynamic multiply-accumulate array 9, completes the non-linear processing of the output layer neuron, and transmits the result to the first-in-first-out buffer. The first-in-first-out buffer sends the result to the processor 1, and the processor 1 forwards the data to the user. Through the above process, the general computing circuit 100 completes the accelerated processing of the liquid state machine, and can accelerate the solution of recognition, classification and prediction problems.

[0083] Please combine Figures 1 to 7In this embodiment, the operation process / principle of the general computing circuit 100 in Ising annealing mode is as follows: the processor 1 receives the combinatorial optimization problem from the user and maps the combinatorial optimization problem to the Ising model, that is, the external field coefficient of the spin and the connection coefficient between the spins, and finally stores it to the weight storage 3. The membrane potential-local field storage 5 is used to store the local field value of 1024 spins, and the neuron-spin state storage 7 is used to store the spin state, that is, up (1) or down (0). The membrane potential-local field calculation array 4 receives 0 value through the pulse port, receives the spin external field coefficient and the connection coefficient through the weight port, and receives the spin state from the neuron-spin state storage 7 through the state port. The membrane potential-local field calculation array 4 performs the NOT operation (the state is 1) or the original output (the state is 0) operation on the input coefficient according to the received spin state, and then performs the accumulation operation, completes the calculation of the local field of 1024 spins, and finally stores the calculation result to the membrane potential-local field storage 5. The dynamic multiply-accumulate array 9 receives the reciprocal value of the real-time annealing temperature through its multiplier port, instead of the pulse neuron weight value in the liquid state machine mode. The dynamic multiply-accumulate array 9 performs the multiplication by 2 operation on the spin local field value through its right shift register, and then performs the NOT operation (the state is 1) or the original output (the state is 0) operation on the multiplication by 2 operation result according to the spin state, completes the calculation of the spin energy change amount, and calculates the multiplication result of the spin energy change amount and the temperature reciprocal through the multiplier, and finally transmits the calculation result to the exponential calculation array 10. The exponential calculation array 10 performs the exponential operation on the input multiplication result, calculates the spin state flip probability value, and then transmits the result to the two-input comparator array 6. The two-input comparator array 6 receives the random number generated by the linear feedback shift register 2 and compares it with the spin state flip probability, if the spin state flip probability value is greater than the random number, the corresponding spin state is flipped, otherwise, the spin state remains unchanged, then the new spin state is stored in the neuron-spin state storage 7. Through the above working process, the general circuit completes an Ising annealing iteration. Through the above multiple iterations, the general circuit can converge the spin state to a certain determined state, which corresponds to the suboptimal solution or the optimal solution of the combinatorial optimization problem.

[0084] Please refer to Figure 8 Another scheme for solving the technical problem of the utility model is to provide a computing device 200 comprising the general computing circuit 100 as described above.

[0085] It can be understood that the computing device 200 has the beneficial effects consistent with the above general computing circuit 100, which will not be repeated here.

[0086] The above merely describes preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement, and improvement within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A liquid state machine and Ising annealing universal computing circuit, characterized in that: comprising a processor, a selector, a linear feedback shift register, a weight storage, a membrane potential-local field computation array, a membrane potential-local field memory, a comparator array, a neuron-spin state memory, a pulse counter, a dynamic multiply-accumulate array, an exponential computation array and an output module; when the computing circuit is in a liquid state machine mode, the output of the processor is connected to the input of the selector and the linear feedback shift register, the output of the selector is connected to the input of the weight storage and the membrane potential-local field computation array; the output of the linear feedback shift register is connected to the input of the weight storage; the output of the weight storage is connected to the input of the membrane potential-local field computation array and the dynamic multiply-accumulate array respectively; the input and output of the membrane potential-local field computation array are connected to the output and input of the membrane potential-local field memory respectively; the output of the membrane potential-local field memory is connected to the input of the comparator array; the output of the comparator array is connected to the input of the neuron-spin state memory; the output of the neuron-spin state memory is connected to the input of the pulse counter; the output of the pulse counter is connected to the input of the dynamic multiply-accumulate array; the output of the dynamic multiply-accumulate array is connected to the input of the exponential computation array; the output of the exponential computation array is connected to the input of the output module; when the computing circuit is in an Ising annealing mode, the output of the processor is connected to the input of the selector and the linear feedback shift register, the output of the selector is connected to the input of the weight storage; the output of the linear feedback shift register is connected to the input of the comparator array; the output of the weight storage is connected to the input of the membrane potential-local field computation array; the output of the membrane potential-local field computation array is connected to the input of the membrane potential-local field memory; the output of the membrane potential-local field memory is connected to the input of the dynamic multiply-accumulate array; the output of the comparator array is connected to the input of the neuron-spin state memory; the output of the neuron-spin state memory is connected to the input of the membrane potential-local field computation array; the output of the dynamic multiply-accumulate array is connected to the input of the exponential computation array; the output of the exponential computation array is connected to the input of the comparator array and the output module respectively. The weight storage comprises a first block storage, a second block storage and a third block storage; the information stored in the first block storage, the second block storage and the third block storage is different when the computing circuit is in different modes. The membrane potential-local field computation array comprises a plurality of computation units, each computation unit comprising an adder, a selector and a NOT gate. ​ 2. The universal computing circuit of claim 1, wherein: ​ 3. The universal computing circuit of claim 1, wherein: ​ 4. The universal computing circuit of claim 1, wherein: The membrane potential-local field computation array comprises an input pulse port, a weight value port, a state information port, an old result port and a new membrane potential / local field value port; When the computation circuit is in the liquid state machine mode, the input pulse port is used for receiving an input pulse signal from the processor; The weight value port is used for receiving a pulse neuron connection weight value from a weight storage; the state information port is used for receiving neuron pulse generation state information from a neuron-spin state storage; The old result port is used for receiving an old membrane potential value from a membrane potential-local field storage; The new membrane potential / local field value port is used for outputting a calculated new membrane potential value; When the computation circuit is in the Ising annealing mode, the input pulse port is used for receiving a 0 value signal; The weight value port is used for receiving an inter-spin coupling weight value from a weight storage; the state information port is used for receiving spin state information from a neuron-spin state storage; The old result port is used for receiving an old local field value from a membrane potential-local field storage; and the new membrane potential / local field value port is used for outputting a calculated new local field value.

5. The universal computing circuit of claim 1, wherein: The input ends of the membrane potential-local field computation array, the comparator array and the dynamic multiply-accumulate array are respectively provided with the selectors.

6. The general purpose computing circuit of claim 1, wherein: When the computation circuit is in the liquid state machine mode, the neuron-spin state storage is used for storing a pulse generation state of each neuron; when the computation circuit is in the Ising annealing mode, the neuron-spin state storage is used for storing a current state of each spin.

7. The general purpose computing circuit of claim 1, wherein: The dynamic multiply-accumulate array comprises a plurality of multiply-accumulate units, and each multiply-accumulate unit comprises a multiplier, an adder, a register, a selector, a shifter and a NOT gate.

8. The general purpose computing circuit of claim 1, wherein: The output module comprises a first-in-first-out buffer.

9. The general purpose computing circuit of claim 8, wherein: The output module further comprises a data sending unit, an input end of the data sending unit being connected with the first-in-first-out buffer, and an output end of the data sending unit being connected with the processor.

10. A computing device, comprising: The general-purpose computation circuit comprises the output module. The general-purpose computation circuit comprises the output module.

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