Semiconductor structure

Abstract

The embodiment of the utility model discloses a semiconductor structure, and the structure comprises a substrate which comprises a first substrate and a second substrate disposed on the first substrate; a first redistribution layer on the second substrate; a chip on the first redistribution layer; the heat conduction layer is located between the first substrate and the second substrate; and the heat conduction column is positioned below the chip, extends to the heat conduction layer from the upper surface of the second substrate and is connected with the heat conduction layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure. BACKGROUND

[0002] Glass substrate technology is an important technology in the field of semiconductor packaging, which uses glass material as the connecting medium between semiconductor chips and external circuits. Glass substrate has broad application prospects in packaging technology due to its excellent insulation, stability and surface flatness.

[0003] However, the thermal conductivity of glass material is relatively low, usually around 1 W / (m·K), which is much lower than that of metal (such as copper, which has a thermal conductivity of about 400 W / (m·K)) and some high-thermal-conductivity semiconductor materials. Therefore, glass substrate is not conducive to quickly conducting the heat generated by the chip downward, and the packaging structure using glass substrate has a serious heat dissipation problem. CONTENT OF THE UTILITY MODEL

[0004] The present disclosure provides a semiconductor structure, comprising:

[0005] a substrate comprising a first substrate and a second substrate located on the first substrate;

[0006] a first redistribution layer located on the second substrate;

[0007] a chip located on the first redistribution layer;

[0008] a thermal conductive layer located between the first substrate and the second substrate;

[0009] a thermal conductive column located below the chip, extending from the upper surface of the second substrate to the thermal conductive layer and connected with the thermal conductive layer.

[0010] In some embodiments, the substrate further comprises a recess located on a side surface of the first substrate close to the second substrate or a side surface of the second substrate close to the first substrate, and the thermal conductive layer is located in the recess.

[0011] In some embodiments, the substrate further comprises an adhesive layer located between the first substrate and the second substrate.

[0012] In some embodiments, the number of thermal conductive columns is one or more, and at least one of the thermal conductive columns has a first gap formed therein.

[0013] In some embodiments, the material of the thermal conductive layer comprises at least one of silicone grease, thermal conductive epoxy resin, thermal conductive phase change material, graphene, and thermal conductive film.

[0014] In some embodiments, the sidewall of the substrate is flush with at least one sidewall of the thermally conductive layer to expose the at least one sidewall of the thermally conductive layer; the semiconductor structure further comprises: a heat dissipation plate connected with the sidewall of the thermally conductive layer exposed by the substrate.

[0015] In some embodiments, the semiconductor structure further comprises: a second redistribution layer located on a side of the first substrate away from the second substrate; and a plurality of conductive columns distributed around the thermally conductive layer, the plurality of conductive columns extending from the upper surface of the second substrate to the lower surface of the first substrate and electrically connected with the first redistribution layer and the second redistribution layer.

[0016] In some embodiments, a ratio of the number of the plurality of conductive columns to the number of the plurality of thermally conductive columns is greater than or equal to 9; and / or, a ratio of a total volume of the plurality of conductive columns and the plurality of thermally conductive columns to a total volume of the first substrate and the second substrate is less than or equal to 0.01.

[0017] In some embodiments, the number of the plurality of conductive columns is one or more, and at least one of the plurality of conductive columns has a second void formed therein.

[0018] In some embodiments, the semiconductor structure further comprises: an adhesive layer between the plurality of thermally conductive columns and / or the plurality of conductive columns and the substrate.

[0019] The semiconductor structure provided by the present disclosure comprises: a substrate comprising a first substrate and a second substrate located on the first substrate; a first redistribution layer located on the second substrate; a chip located on the first redistribution layer; a thermally conductive layer located between the first substrate and the second substrate; and a plurality of thermally conductive columns located below the chip, extending from the upper surface of the second substrate to the thermally conductive layer and connected with the thermally conductive layer. In the embodiments of the present disclosure, the plurality of thermally conductive columns are located below the chip and connected with the thermally conductive layer, so that the heat generated by the chip during operation can be conducted to the thermally conductive layer through the plurality of thermally conductive columns, and then diffused to the outside of the substrate to complete heat dissipation, thereby improving the heat dissipation efficiency of the substrate. At the same time, the closer the thermally conductive layer is to the heat source (chip), the better the heat dissipation effect is. In the embodiments of the present disclosure, the thermally conductive layer is located between the first substrate and the second substrate, thereby effectively increasing the heat dissipation efficiency of the chip and flexibly adjusting the distance between the thermally conductive layer and the chip according to actual needs to increase the scene applicability.

[0020] Details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and description below. Other features and advantages of the present disclosure will become apparent from the description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A top view schematic diagram of a substrate provided in some embodiments of this disclosure; Figure 2 and Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure; wherein, Figure 2 The substrate in the middle is along Figure 1 A schematic diagram of the cross-sectional structure taken by line AA' in the diagram. Figure 3 The substrate in the middle is along Figure 1 A schematic diagram of the cross-sectional structure taken by line BB' in the middle;

[0023] Figure 4 for Figure 2 A bottom view of the second substrate in the diagram;

[0024] Figure 5a , Figure 6a and Figure 7a These are different examples of schematic diagrams of the substrate provided in the embodiments of this disclosure. Figure 5b and Figure 6b They are respectively Figure 5a and Figure 6a A bottom view of the second substrate. Figure 7b for Figure 7a A top view of the first substrate in the diagram;

[0025] Figure 8 Figures (1) and (2) are Figure 2 Different examples of magnified details of region Q1 in the image;

[0026] Figure 9 Figures (1) and (2) are Figure 3 Different examples of magnified details of the Q2 region in the image. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof. For example, the terms "including" and "comprising" should be given their broadest interpretative meanings, that is, "including", but not limited to.

[0029] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated for clarity. Like reference numerals in different drawings denote like elements.

[0030] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Conversely, a second element, component, region, layer or section discussed need not necessarily be termed a first element, component, region, layer or section.

[0031] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] Glass substrate technology is an important technology in the field of semiconductor packaging, which uses glass material as the connecting medium between semiconductor chips and external circuits. Glass substrate has broad application prospects in packaging technology due to its excellent insulation, stability and surface flatness.

[0034] However, the thermal conductivity of glass material is relatively low, usually around 1 W / (m·K), which is much lower than that of metal (such as copper, which has a thermal conductivity of about 400 W / (m·K)) and some high-thermal-conductivity semiconductor materials. Therefore, glass substrate is not conducive to quickly conducting the heat generated by the chip downward, and the packaging structure using glass substrate has a serious heat dissipation problem.

[0035] Based on this, the technical scheme of the embodiments of the present disclosure is proposed. The specific embodiments of the present disclosure will be described in detail below in conjunction with the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagram will be partially enlarged without general proportion, and the schematic diagram is only an example, which should not limit the protection scope of the present disclosure herein.

[0036] As shown in the figure, the semiconductor structure includes: a substrate 10, including a first substrate 101 and a second substrate 102 located on the first substrate 101; a first redistribution layer 15 located on the second substrate 102; a chip 20 located on the first redistribution layer 15; a heat-conducting layer 11 located between the first substrate 101 and the second substrate 102; and a heat-conducting column 13 located below the chip 20, extending from the upper surface of the second substrate 102 to the heat-conducting layer 11 and connected with the heat-conducting layer 11.

[0037] In the embodiment of the present disclosure, the heat-conducting column 13 is located below the chip 20 and connected with the heat-conducting layer 11, so that the heat generated by the chip 20 during operation can be conducted to the heat-conducting layer 11 through the heat-conducting column 13, and then diffused to the outside of the substrate 10 to complete heat dissipation, thereby improving the heat dissipation efficiency of the substrate 10; at the same time, the closer the heat-conducting layer 11 is to the heat source (chip 20), the better the heat dissipation effect is. In the embodiment of the present disclosure, the heat-conducting layer 11 is located between the first substrate 101 and the second substrate 102, thereby shortening the distance between the heat-conducting layer 11 and the chip 20, effectively increasing the heat dissipation efficiency of the chip 20, and flexibly adjusting the thickness of the first substrate 101 and the second substrate 102 according to actual needs, so as to flexibly adjust the distance between the heat-conducting layer 11 and the chip 20, thereby increasing the scene applicability.

[0038] In some embodiments, the materials of the first substrate 101 and the second substrate 102 can be the same or different. In some embodiments, the materials of the first substrate 101 and the second substrate 102 are both glass. Glass has excellent insulation, stability and surface flatness, and using glass as a packaging substrate can improve the packaging quality. However, the thermal conductivity of glass is poor. In the embodiment of the present disclosure, the heat-conducting column 13 and the heat-conducting layer 11 connected with the heat-conducting column 13 are formed in the glass substrate, thereby effectively improving the heat dissipation efficiency of the glass substrate. However, the technical solutions provided by the present disclosure can also be applied to other substrates, such as silicon substrates, plastic substrates, etc.

[0039] As shown in FIG. 1, Figure 4 In some embodiments, the substrate 10 further includes a groove S, and the groove S is located on the side surface of the second substrate 102 close to the first substrate 101, and the heat-conducting layer 11 is located in the groove S. In actual operation, laser ablation or laser-induced etching (LIERP) can be used to form the groove S on one side surface of the second substrate 102, and the heat-conducting layer 11 is formed in the groove S, and then the side surface of the second substrate 102 formed with the heat-conducting layer 11 is bonded to the first substrate 101.

[0040] However, as shown in FIG. 2, Figure 7a to Figure 7b the groove S can also be located on the side surface of the first substrate 101 close to the second substrate 102. In actual operation, laser ablation or laser-induced etching (LIERP) can be used to form the groove S on one side surface of the first substrate 101, and the heat-conducting layer 11 is formed in the groove S, and then the side surface of the first substrate 101 formed with the heat-conducting layer 11 is bonded to the second substrate 102.

[0041] In some embodiments, the material of the heat-conducting layer 11 includes but is not limited to one or a combination of materials with good heat-conducting properties such as silicone grease, heat-conducting epoxy resin, heat-conducting phase change material, graphene, heat-conducting film, etc.

[0042] In some embodiments, the substrate 10 further comprises an adhesive layer 12 between the first substrate 101 and the second substrate 102 for bonding the first substrate 101 and the second substrate 102. Specifically, as shown in Figure 2 and Figure 3 , the adhesive layer 12 can be between the second substrate 102 and the heat-conductive layer 11 and the first substrate 101, or as shown in Figure 7a to Figure 7b , the adhesive layer 12 can also be between the first substrate 101 and the heat-conductive layer 11 and the second substrate 102.

[0043] In some embodiments, the material of the adhesive layer 12 includes but is not limited to ultraviolet glue.

[0044] In some embodiments, the number of the heat-conductive layer 11 can be one or more, and the number and arrangement of the heat-conductive layer 11 can be related to the number and arrangement of the chip 20. For example, one heat-conductive layer 11 can be arranged under each chip 20, and one chip 20 can dissipate heat through one heat-conductive layer 11; or one heat-conductive layer 11 can be arranged under multiple chips 20, and multiple chips 20 can share one heat-conductive layer 11 to dissipate heat; or multiple heat-conductive layers 11 can be arranged under one chip 20, and one chip 20 can dissipate heat through multiple heat-conductive layers 11.

[0045] As shown in Figure 1 to Figure 4 , in some embodiments, the heat-conductive layer 11 can penetrate the substrate 10 along a direction parallel to the plane of the substrate 10 (the heat-conductive layer 11 shown in the figure penetrates the second substrate 102, but is not limited thereto, and the heat-conductive layer 11 can also penetrate the first substrate 101), and two chips 20 can share one heat-conductive layer 11 to dissipate heat. However, it is not limited thereto, as shown in Figure 5a and Figure 5b , the number of the heat-conductive layer 11 can be two, and the two heat-conductive layers 11 can be symmetrically arranged on both sides of the substrate 10, or as shown in Figure 6a and Figure 6b , the heat-conductive layer 11 can also be located on one side of the substrate 10, and two chips 20 can share one heat-conductive layer 11 to dissipate heat, thereby increasing the applicability of the scene.

[0046] Referring again to Figure 2 to Figure 7b , in some embodiments, the sidewall of the substrate 10 is flush with at least one sidewall of the heat-conductive layer 11 to expose at least one sidewall of the heat-conductive layer 11; the semiconductor structure further comprises a heat sink 19 connected to the sidewall of the heat-conductive layer 11 exposed by the substrate 10, so that the heat conducted to the heat-conductive layer 11 can be conducted out of the substrate 10 to the heat sink to complete heat dissipation.

[0047] In some embodiments, the surface of the heat sink 19 is distributed with heat dissipation fins 191 to increase the heat dissipation performance of the heat sink 19.

[0048] As shown in Figure 2 and Figure 3 In some embodiments, the first redistribution layer 15 includes a first dielectric layer 151, a plurality of first metal layers 152 in the first dielectric layer 151, and first plugs 153 for connecting two adjacent first metal layers 152, the first metal layers 152 and the first plugs 153 are distributed alternately in the vertical direction. Figure 2 and Figure 3 The number of the first metal layers 152 shown in

[0049] As shown in Figure 3 In some embodiments, the first redistribution layer 15 is formed with solder balls 17 on the side away from the substrate 10, the solder balls 17 are electrically connected with the first metal layers 152 in the first redistribution layer 15, and one or more chips 20 are fixed on the solder balls 17 and electrically connected with the first redistribution layer 15 through the solder balls 17. The number of the chips 20 shown in the figure is 2, but it is not limited thereto, and the number of the chips 20 fixed on the first redistribution layer 15 can be more or less.

[0050] In some embodiments, the gap between the chip 20 and the first redistribution layer 15 is also filled with a packaging compound 18. In some embodiments, the packaging compound 18 can also coat the chip 20 for protecting the chip 20.

[0051] But it is not limited thereto, the chip 20 and the first redistribution layer 15 can also be connected through hybrid bonding.

[0052] As shown in Figure 2 In some embodiments, the heat-conducting column 13 can be connected with part of the first metal layers 152 and part of the first plugs 153, and the first metal layers 152 and the first plugs 153 connected with the heat-conducting column 13 are located below the chip 20 and electrically insulated from the chip 20 (for example, the packaging compound 18 is used to separate the two), and the heat-conducting column 13 and the chip 20 do not transmit electrical signals, so that the heat generated by the chip 20 during work can be conducted to the heat-conducting column 13 through part of the first metal layers 152 and part of the first plugs 153 in the first redistribution layer 15, and then to the heat-conducting layer 11, the distance between the first redistribution layer 15 and the heat-conducting column 13 and the chip 20 is closer, which improves the heat dissipation efficiency of the chip 20 and the heat dissipation efficiency of the first redistribution layer 15.

[0053] In some embodiments, the heat-conducting column 13 is arranged below the chip 20, and the projection of the heat-conducting column 13 in the vertical direction falls within the projection of the heat-conducting layer 11 in the vertical direction. The number of heat-conducting columns 13 below each chip 20 can be one or more, and each chip 20 can transmit heat to the heat-conducting layer 11 through one or more heat-conducting columns 13.

[0054] As shown in FIG. 1, in some embodiments, the substrate 10 has a heat-conducting via T1 extending from the upper surface of the second substrate 102 to the heat-conducting layer 11, and the heat-conducting column 13 is located in the heat-conducting via T1. In some embodiments, the semiconductor structure further comprises an adhesion layer 21 located between the heat-conducting column 13 and the substrate 10. In some embodiments, the substrate 10 has poor adhesion, and the adhesion layer 21 is formed between the heat-conducting column 13 and the substrate 10 to increase the firmness of the combination of the heat-conducting column 13 and the substrate 10. Figure 8 In some embodiments, the heat-conducting column 13 comprises a first seed layer 131 covering the inner wall of the heat-conducting via T1 and a heat-conducting material layer 132 covering the first seed layer 131. In actual operation, the heat-conducting via T1 exposing the heat-conducting layer 11 can be first formed in the substrate 10 by using a laser-induced etching method, then the adhesion layer 21 can be formed on the sidewall of the heat-conducting via T1 by using a thin film process (such as a physical vapor deposition process), and the first seed layer 131 and the adhesion layer 21 are covered, and then the heat-conducting material layer 132 is formed by using an electroplating process.

[0055] In some embodiments, the aspect ratio of the heat-conducting via T1 ranges from 5 to 10, such as 5, 7, 10, etc. In some embodiments, the material of the adhesion layer 21 includes but is not limited to titanium, chromium. The material of the first seed layer 131 and the heat-conducting material layer 132 includes but is not limited to one or more of copper, tungsten, nickel, tin, etc. with high thermal conductivity, such as copper.

[0056] As shown in FIG. 1 (1), in some embodiments, at least one heat-conducting column 13 has a first void 22 formed therein, and the first void 22 can extend from the upper surface of the second substrate 102 to the inside of the heat-conducting column 13. However, the first void 22 can also be a closed void completely wrapped by the heat-conducting column 13. In some embodiments, a thin layer of heat-conducting layer 11 can be deposited when forming the heat-conducting material layer 132, thereby forming the first void 22 extending from the upper surface of the second substrate 102 to the inside of the heat-conducting column 13. However, the first void 22 can also be formed by using the high aspect ratio of the heat-conducting via T1 when forming the heat-conducting material layer 132.

[0057] Figure 8

[0058] ​​In the embodiments of the present disclosure, the thermal expansion coefficient of the material of the heat-conducting column 13 (for example, the thermal expansion coefficient of copper is about 18 ppm) is much higher than the thermal expansion coefficient of the material of the substrate 10 (for example, the thermal expansion coefficient of glass is about 3 ppm), and by arranging the first gap 22 in the heat-conducting column 13, the thermal mismatch of the semiconductor structure can be relieved, and the reliability of the semiconductor structure can be improved.

[0059] In some embodiments, in the case that the first gap 22 is arranged in the heat-conducting layer 11, the ratio of the thickness of the heat-conducting column 13 to the diameter of the heat-conducting via T1 is greater than or equal to 0.2, so as to avoid that the thickness of the heat-conducting column 13 is too small to cause poor heat-conducting performance of the heat-conducting column 13. Here, the thickness of the heat-conducting column 13 refers to the thickness in the radial direction of the heat-conducting column 13.

[0060] As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 8 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11.

[0061] As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 2 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 3 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11.

[0062] As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 3 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 3 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11.

[0063] As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 1 As shown in FIG. 2, the semiconductor structure further includes one or more heat-conducting columns 13 arranged in the heat-conducting layer 11. Figure 3As shown, in some embodiments, the semiconductor structure further comprises: a plurality of electrically conductive pillars 14 distributed around the thermally conductive layer 11, the electrically conductive pillars 14 extending from the upper surface of the second substrate 102 to the lower surface of the first substrate 101 and electrically connected to the first redistribution layer 15 and the second redistribution layer 16, the number of the electrically conductive pillars 14 can be one or more, and the chip 20 receives or outputs electrical signals through the first redistribution layer 15, the electrically conductive pillars 14 and the second redistribution layer 16. Specifically, the electrically conductive pillars 14 are electrically connected to part of the first metal layers 152 and part of the first plugs 153 in the first redistribution layer 15, and are electrically connected to the second metal layers 162 and the second plugs 163 in the second redistribution layer 16.

[0064] It should be noted that the part of the first metal layers 152 and the part of the first plugs 153 electrically connected to the electrically conductive pillars 14 and the part of the first metal layers 152 and the part of the first plugs 153 electrically connected to the thermally conductive pillars 13 are insulated from each other to avoid short circuit between the electrically conductive pillars 14 and the thermally conductive pillars 13.

[0065] As shown in FIG. 1, in some embodiments, the semiconductor structure further comprises: an adhesive layer 21 formed on the inner wall of the electrically conductive through hole T2. Figure 9 As shown, in some embodiments, the semiconductor structure further comprises: a plurality of electrically conductive pillars 14 distributed around the thermally conductive layer 11, the electrically conductive pillars 14 extending from the upper surface of the second substrate 102 to the lower surface of the first substrate 101 and electrically connected to the first redistribution layer 15 and the second redistribution layer 16, the number of the electrically conductive pillars 14 can be one or more, and the chip 20 receives or outputs electrical signals through the first redistribution layer 15, the electrically conductive pillars 14 and the second redistribution layer 16. Specifically, the electrically conductive pillars 14 are electrically connected to part of the first metal layers 152 and part of the first plugs 153 in the first redistribution layer 15, and are electrically connected to the second metal layers 162 and the second plugs 163 in the second redistribution layer 16.

[0066] As shown in FIG. 1, in some embodiments, the semiconductor structure further comprises: an adhesive layer 21 formed on the inner wall of the electrically conductive through hole T2.

[0067] As shown in FIG. 1, in some embodiments, the semiconductor structure further comprises: an adhesive layer 21 formed on the inner wall of the electrically conductive through hole T2.

[0068] As shown in FIG. 1, in some embodiments, the semiconductor structure further comprises: an adhesive layer 21 formed on the inner wall of the electrically conductive through hole T2. Figure 8As shown in Figure (2), in some embodiments, a second void 23 is formed within at least one conductive pillar 14, and the second void 23 extends from the upper surface of the second substrate 102 to the lower surface of the first substrate 101. However, it is not limited to this; the second void 23 can also be a closed void completely enclosed by the conductive pillar 14. In some embodiments, when forming the conductive layer 14, only a thin conductive layer 14 can be deposited, thereby forming a second void 23 extending from the upper surface of the second substrate 102 to the lower surface of the first substrate 101 within the conductive pillar 14. However, it is not limited to this; the second void 23 can also be formed using the high aspect ratio of the conductive via T2 when forming the conductive material layer 142.

[0069] In this embodiment, the coefficient of thermal expansion of the material of the conductive pillar 14 (e.g., the coefficient of thermal expansion of copper is about 18 ppm) is much higher than that of the material of the substrate 10 (e.g., the coefficient of thermal expansion of glass is about 3 ppm). By providing a second air gap 23 in the conductive pillar 14, the thermal mismatch of the semiconductor structure can be alleviated and the reliability of the semiconductor structure can be improved.

[0070] In some embodiments, when the conductive layer 14 has a second gap 23, the ratio of the thickness of the conductive post 14 to the diameter of the conductive via T2 is greater than or equal to 0.2, to avoid poor conductivity of the conductive post 14 due to insufficient thickness. Here, the thickness of the conductive post 14 is the thickness along the radial direction of the conductive post.

[0071] like Figure 8 As shown in Figure (2), one or more conductive pillars 14 may not have a second gap 23, and the conductive pillars 14 may be filled with conductive through holes T2. The conductive pillars 14 may be solid conductive pillars. For example, some conductive pillars 14 may have a second gap 23, some conductive pillars 14 may be solid conductive pillars, or all conductive pillars 14 may be solid conductive pillars, or all conductive pillars 14 may have a second gap 23. The specific configuration can be flexibly set according to actual needs.

[0072] In some embodiments, the ratio of the number of conductive pillars 14 to the number of heat-conducting pillars 13 is greater than or equal to 9, such as 9, 10, 12, 15, etc. Thus, by controlling the ratio of the number of conductive pillars 14 to the number of heat-conducting pillars 13 within the above range, the heat dissipation efficiency of the semiconductor structure can be improved while ensuring the transmission of electrical performance in the semiconductor structure.

[0073] In some embodiments, the ratio of the total volume of the electrically conductive pillars 14 and the thermally conductive pillars 13 to the total volume of the first substrate 101 and the second substrate 102 is less than or equal to 0.01, and the thermal expansion coefficient of the electrically conductive pillars 14 and the thermally conductive pillars 13 is relatively high compared to the substrate 10. By controlling the ratio of the total volume of the electrically conductive pillars 14 and the thermally conductive pillars 13 to the total volume of the first substrate 101 and the second substrate 102 within the above range, the volume proportion of the electrically conductive pillars 14 and the thermally conductive pillars 13 is prevented from being too large, and the thermal expansion of the electrically conductive pillars 14 and the thermally conductive pillars 13 causes the stability problem of the semiconductor structure. Here, the total volume of the electrically conductive pillars 14 and the thermally conductive pillars 13 does not include the volume of the first gap 22 and the second gap 23; the total volume of the first substrate 101 and the second substrate 102 does not include the volume of the thermally conductive layer 11, the thermally conductive pillars 13, the electrically conductive pillars 14 and other structures located in the substrate 102.

[0074] Referring again to Figure 2 and Figure 3 In some embodiments, the semiconductor structure further includes a heat spreader 24 arranged on the chip 20 to further improve the heat dissipation efficiency of the chip 20. In some embodiments, the heat spreader 24 can be adhered to the chip 20 by a thermal interface material.

[0075] It should be noted that the above only describes the preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a first substrate and a second substrate on the first substrate; a first redistribution layer on the second substrate; a chip on the first redistribution layer; a thermal conductive layer between the first substrate and the second substrate; a thermal conductive pillar under the chip, extending from an upper surface of the second substrate to the thermal conductive layer and connected with the thermal conductive layer.

2. The semiconductor structure of claim 1, wherein, The substrate further comprises a groove on a side surface of the first substrate close to the second substrate or on a side surface of the second substrate close to the first substrate, and the thermal conductive layer is located in the groove.

3. The semiconductor structure of claim 1, wherein, The substrate further comprises an adhesive layer between the first substrate and the second substrate.

4. The semiconductor structure of claim 1, wherein, The number of the thermal conductive pillars is one or more, and at least one of the thermal conductive pillars has a first void formed therein.

5. The semiconductor structure of claim 1, wherein, The material of the thermal conductive layer comprises at least one of silicone grease, thermal conductive epoxy resin, thermal conductive phase change material, graphene, and thermal conductive film.

6. The semiconductor structure of claim 1, wherein, The sidewall of the substrate is flush with at least one sidewall of the thermal conductive layer to expose the at least one sidewall of the thermal conductive layer; the semiconductor structure further comprises a heat sink connected with the sidewall of the thermal conductive layer exposed by the substrate.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a second redistribution layer on a side of the first substrate away from the second substrate, and a conductive pillar distributed around the thermal conductive layer, extending from an upper surface of the second substrate to a lower surface of the first substrate and electrically connected with the first redistribution layer and the second redistribution layer.

8. The semiconductor structure of claim 7, wherein, The ratio of the number of the conductive pillars to the number of the thermal conductive pillars is greater than or equal to 9; and / or, the ratio of the total volume of the conductive pillars and the thermal conductive pillars to the total volume of the first substrate and the second substrate is less than or equal to 0.

01.

9. The semiconductor structure of claim 7, wherein, The number of the conductive pillars is one or more, and at least one of the conductive pillars has a second void formed therein.

10. The semiconductor structure of claim 7, wherein, The semiconductor structure further comprises an adhesive layer between the thermal conductive pillar and / or the conductive pillar and the substrate.

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