Switching converter, zero cross detection circuit thereof, chip and display device

Abstract

The utility model discloses a switching converter and a zero-cross detection circuit, a chip and a display device thereof, and the zero-cross detection circuit comprises a comparator which is used for comparing the voltage of a switching node with the output voltage of the switching converter to obtain a first comparison signal; the turn-on time control circuit is used for generating a turn-on time control signal according to the first comparison signal; and the adjustable delay circuit is used for adjusting the conduction duration of the synchronous switching tube in each switching period according to the conduction time control signal, so that the light load efficiency of the switching converter is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit technical field especially relates to a switching converter and zero -crossing detection circuit, chip, display device thereof. BACKGROUND

[0002] Switching converter is a kind of power supply using modern power electronics technology, control the on and off time ratio of switch tube, maintain stable output voltage.Synchronous DC-DC (DC-DC) converter is widely used because of its low conduction loss, but because MOS tube has bidirectional conduction characteristic, when DC-DC converter is in light load mode, current backflow phenomenon occurs easily, leading to energy loss, so its efficiency in light load mode is significantly reduced, therefore, prior art will increase inductance current zero-crossing detection circuit (ZCD) in DC-DC converter to prevent inductance current backflow, to improve the efficiency of DC-DC converter in light load mode.

[0003] Figure 1 The structure diagram of prior art switching converter is shown.Referring to Figure 1 , switching converter 100 includes power element L and main switch tube MN connected in series between input voltage Vin and ground, synchronous switch tube MP and capacitor Cout connected in series between the common node SW of inductance L and main switch tube MN and ground, load RL in parallel with capacitor Cout, and the common node of synchronous switch tube MP and capacitor Cout provides output voltage Vout.Switching converter 100 also includes drive unit 110 and 120, PWM logic control circuit 130 and comparator 140 used as zero-crossing detection circuit, PWM logic control circuit 130 is used to provide control signal to drive unit 110 and 120 respectively, to make drive unit 110 and 120 drive the conduction and shutdown of main switch tube MN and synchronous switch tube MP respectively, comparator 140 is used to detect the voltage change across synchronous switch tube MP, and the comparison result is output to PWM logic control circuit 130.When the voltage Vsw of switching node SW is less than output voltage Vout, inductance current IL appears backflow, and the zero-crossing detection signal ZCD emitted by comparator 140 shuts down synchronous switch tube MP, because comparator 140 itself has offset and delay, and signal transmission also has delay, therefore, in order to ensure that synchronous switch tube MP is shut down at the zero-crossing point of inductance current IL, prior art will increase a certain amount of offset in comparator 140, but this scheme is only applicable to the case that input voltage Vin and output voltage Vout of switching converter 100 are fixed, when output voltage Vout changes, the slope of inductance current IL changes, which can cause the shutdown time of synchronous switch tube MP to be too early or too late.

[0004] Referring to Figure 2awhich is a schematic diagram of the variation of the inductor current IL when the turn-off time of the synchronous switch tube MP is too late, at this time, the inductor current IL will appear a stage of current reversal, in which the capacitor Cout is discharged reversely, resulting in energy loss. Figure 2b which is a schematic diagram of the variation of the inductor current IL when the turn-off time of the synchronous switch tube MP is too early, at this time, the inductor current IL will appear a stage of flowing through the body diode of the synchronous switch tube MP to the load RL, in which the on-voltage drop of the body diode will result in energy loss. Therefore, the turn-off time of the synchronous switch tube MP being too early or too late will both lead to the reduction of the efficiency of the switching converter 100.

[0005] Therefore, a new switching converter and its zero-crossing detection circuit need to be proposed to solve the above problems. Invention content

[0006] In view of the above problems, the purpose of the present application is to provide a switching converter and its zero-crossing detection circuit, chip and display device, so as to improve the light load efficiency of the switching converter.

[0007] According to the first aspect of the present application, a zero-crossing detection circuit of a switching converter is provided, the switching converter comprising a main switch tube and a synchronous switch tube, a common node of the main switch tube and the synchronous switch tube being a switching node, the zero-crossing detection circuit comprising a comparator for comparing the voltage of the switching node with the output voltage of the switching converter to obtain a first comparison signal according to the comparison result; a turn-on time control circuit for generating a turn-on time control signal according to the first comparison signal; and an adjustable delay circuit for adjusting the turn-on duration of the synchronous switch tube in each switching period according to the turn-on time control signal.

[0008] Optionally, the adjustable delay circuit comprises a delay capacitor and a first current source for charging the delay capacitor, and the adjustable delay circuit is configured to control the synchronous switch tube to turn off when the voltage of the delay capacitor is charged to a set threshold, so as to control the turn-on duration of the synchronous switch tube in each switching period, wherein the adjustable delay circuit is further configured to adjust the capacitance value of the delay capacitor according to the turn-on time control signal, so as to adaptively adjust the turn-on duration of the synchronous switch tube in each switching period.

[0009] Optionally, the turn-on time control circuit is configured to perform increment or decrement counting operation according to the level state of the first comparison signal in each switching period, so as to generate the turn-on time control signal.

[0010] Optionally, the on-time control circuit comprises a D flip-flop for sampling and holding the first comparison signal in each switching cycle to obtain a trigger signal corresponding to the level state of the first comparison signal; and an add-subtract counter for adjusting the value of the on-time control signal according to the value of the trigger signal in each switching cycle.

[0011] Optionally, the on-time control circuit further comprises a SAR logic circuit for providing a logic digital signal to the add-subtract counter when the zero-crossing detection circuit fails to calibrate the turn-off instant of the synchronous switch tube within a set time through the add-subtract counter, so that the add-subtract counter directly outputs the logic digital signal as the on-time control signal.

[0012] Optionally, the on-time control circuit further comprises a count control module for counting the number of times that the trigger signal is continuously at the same level in a plurality of continuous switching cycles to obtain a count value, and obtaining a count enable signal according to the count value, the count enable signal being used to control the working state of the add-subtract counter and the SAR logic circuit, wherein, when the count enable signal is at a first level state, the add-subtract counter is in a pass-through mode and the SAR logic circuit is working, and when the count enable signal is at a second level state, the add-subtract counter is in an add-subtract counting mode and the SAR logic circuit is not working.

[0013] Optionally, the comparator is a dynamic comparator, which compares the voltage of the switching node and the output voltage of the switching converter at the turn-off instant of the synchronous switch tube to obtain the first comparison signal according to the comparison result.

[0014] Optionally, the count control module counts the number of times that the trigger signal is continuously at a first level and a second level respectively by using a first count value and a second count value, resets the other count value when adding 1 to one of the count values, and flips the count enable signal from the second level to the first level when the first count value or the second count value is greater than or equal to a preset value; the SAR logic circuit converts the trigger signal in a plurality of continuous switching cycles into a logic digital signal by using a successive approximation algorithm, and outputs a reset signal to the count control module after the conversion is completed, and also outputs a corresponding logic digital signal to the add-subtract counter in each switching cycle of the plurality of switching cycles; and the count control module is further configured to reset the count values after receiving the reset signal.

[0015] Optionally, the adjustable delay circuit further comprises a first switch and a second switch connected in sequence between the first current source and a charging path of the delay capacitor, the first switch and the second switch turn on the charging path at the turn-on time of the synchronous switch to output a first voltage signal at a first node between the first switch and the second switch; a voltage comparison module connected with the first node, configured to compare the first voltage signal with the set threshold to obtain a second comparison signal according to the comparison result; and an output module configured to generate a zero-crossing detection signal according to the second comparison signal and a driving signal of the main switch, wherein the zero-crossing detection signal controls the synchronous switch to turn off when the voltage of the delay capacitor is charged to the set threshold.

[0016] Optionally, the adjustable delay circuit further comprises a third switch connected between the power supply voltage and the first node, the third switch turns on when the first voltage signal rises to the set threshold to maintain the voltage of the first node at the power supply voltage; a fourth switch connected between the two ends of the delay capacitor, the fourth switch turns on when the first voltage signal rises to the set threshold to reset the voltage of the delay capacitor; and a fifth switch connected between the first node and a ground end, the fifth switch turns on when the main switch turns on to reset the voltage of the first node.

[0017] Optionally, the adjustable delay circuit further comprises a control signal generation module configured to perform an OR operation on the second comparison signal and the driving signal of the main switch to obtain a first control signal, and invert the first control signal to obtain a second control signal, the first control signal is provided to a control end of the fourth switch, and the second control signal is provided to control ends of the second switch and the third switch; and the output module is configured to perform an AND operation on an inverted signal of the second comparison signal and an inverted signal of the driving signal of the main switch to obtain the zero-crossing detection signal.

[0018] Optionally, the charging current provided by the first current source to the delay capacitor is related to a voltage difference between a preset output voltage and an input voltage.

[0019] Optionally, the first current source receives an adjustment signal related to a preset output voltage and outputs the charging current; the voltage comparison module comprises a second current source and a first transistor, which are connected in sequence between a power supply voltage and a ground terminal, a control terminal of the first transistor receives the first voltage signal, the second current source provides a bias current, and an intermediate node of the second current source and the first transistor provides the second comparison signal, and the set threshold value is equal to a threshold voltage of the first transistor; the delay capacitor comprises a first capacitor and a switched capacitor array connected in parallel, the switched capacitor array comprises a plurality of capacitor branches with the same number of bits as the on-time control signal, and the first to last capacitor branches are controlled by the lowest bit to the highest bit of the on-time control signal in sequence, and are selectively connected in parallel with the first capacitor.

[0020] According to the second aspect of the present application, a switching converter is provided, comprising a main switch tube and a synchronous switch tube, and a switching node between the main switch tube and the synchronous switch tube; an inductor connected to the switching node; a first driving unit for generating a first driving signal according to a first switch control signal to drive the main switch tube to turn on and turn off; a second driving unit for generating a second driving signal according to a second switch control signal to drive the synchronous switch tube to turn on and turn off; a PWM logic control circuit for providing the first switch control signal and the second switch control signal to the first driving unit and the second driving unit respectively; and the zero-crossing detection circuit as described above for providing the zero-crossing detection signal to the second driving unit.

[0021] According to the third aspect of the present application, a chip is provided, comprising the switching converter as described above.

[0022] According to the fourth aspect of the present application, a display device is provided, comprising a display panel for displaying an image; a driving circuit for controlling the display state of the display panel; and the switching converter as described above.

[0023] The switching converter, the zero-crossing detection circuit thereof, the chip and the display device provided by the present application have the following advantages: the comparator compares the voltage of the switching node with the output voltage of the switching converter to obtain a first comparison signal according to the comparison result; the on-time control circuit generates an on-time control signal according to the first comparison signal; and the adjustable delay circuit is used to adjust the on-time of the synchronous switch tube in each switching cycle according to the on-time control signal, thereby improving the light load efficiency of the switching converter.

[0024] In the preferred embodiment, by setting the count control module and the SAR logic circuit in the on-time control circuit, the switching converter can realize fast switching between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) of the inductor current when the load current changes, so that the switching converter can quickly enter a stable state.

[0025] In the preferred embodiment, the adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor, and the adjustable delay circuit controls the synchronous switch tube to be turned off when the voltage of the delay capacitor is charged to a set threshold value, and by setting the charging current provided by the first current source to be related to the voltage difference between the preset output voltage and the input voltage, the zero-crossing detection circuit can maintain the same accuracy under different preset output voltages, so that the synchronous switch tube can be accurately turned off at the zero-crossing point of the inductor current, thereby further improving the light load efficiency of the switching converter. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application taken with reference to the accompanying drawings, in which:

[0027] Figure 1 A structure schematic diagram of a switching converter according to the prior art is shown;

[0028] Figures 2a-2b A schematic diagram of the inductor current change of the switching converter when the synchronous switch tube is turned off too early or too late is shown;

[0029] Figure 3 A structure schematic diagram of a switching converter according to the present application is shown;

[0030] Figure 4 A circuit schematic diagram of an on-time control circuit according to the present application is shown;

[0031] Figure 5 A circuit schematic diagram of a count control module according to the present application is shown;

[0032] Figure 6 A working schematic diagram of a SAR logic circuit according to the present application is shown;

[0033] Figure 7 A circuit schematic diagram of an adjustable delay circuit according to the present application is shown;

[0034] Figure 8 A timing schematic diagram of an adjustable delay circuit according to the present application is shown;

[0035] Figure 9 A working schematic diagram of the zero-crossing detection circuit is shown. DETAILED DESCRIPTION

[0036] Various embodiments of the present application will be described hereinafter with reference to the accompanying drawings. In the drawings, like reference numerals are used to represent the same or similar elements throughout the various drawings. For the purpose of clarity, not every component is called out in every drawing.

[0037] It should be understood that, in the following description, "circuitry" can include a single or multiple components, or a combination of hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that store instructions for execution by a programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "between" two elements, it can be directly coupled to the other element or be coupled to the other element with intervening elements between them, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements between them.

[0038] Meanwhile, some terms are used throughout this patent document to refer to particular components. As one skilled in the art will appreciate, hardware manufacturers can refer to the same component by different names. This document does not intend to distinguish between components that differ in name but not in function. In this document, a component referred to by two different names can be a single component or different components unless otherwise indicated.

[0039] In addition, it should also be noted that, in this document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an expression "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0040] Figure 3 A structural schematic diagram of the switching converter is shown.

[0041] Referring to Figure 3The switch converter 200 provided by the embodiment of the utility model includes power element L and synchronous switch tube MP connected in series between the input end and the output end of the switch converter 200, main switch tube MN connected in series between switch node SW and ground terminal, capacitor Cout connected between the output end of the switch converter 200 and the ground terminal, and load RL connected in parallel with the capacitor Cout. Wherein, the power element L adopts inductance, the main switch tube MN adopts NMOS tube for example, and the synchronous switch tube MP adopts PMOS tube for example. The switch node SW is the intermediate node of the power element L and the main switch tube MN, the output end of the switch converter 200, that is, the common node of the synchronous switch tube MP and the capacitor Cout provides output voltage Vout, and the input end of the switch converter 200 receives input voltage Vin.

[0042] The switch converter 200 further includes driving units 210 and 220, PWM logic control circuit 230 and zero-crossing detection circuit. The PWM logic control circuit 230 is used to provide switch control signals Lg_ctrl and Hg_ctrl to the driving units 210 and 220 respectively, and the switch control signals Lg_ctrl and Hg_ctrl are PWM signals for example. The driving unit 210 is used to generate driving signal Lg_drv according to the switch control signal Lg_ctrl to drive the main switch tube MN to turn on and turn off. The driving signal Lg_drv drives the main switch tube MN to turn on when it is at high level, and drives the main switch tube MN to turn off when it is at low level for example. The driving unit 220 is used to generate driving signal Hg_drv according to the switch control signal Hg_ctrl and zero-crossing detection signal ZCD to drive the synchronous switch tube MP to turn on and turn off. The driving signal Hg_drv drives the synchronous switch tube MP to turn on when it is at high level, and drives the synchronous switch tube MP to turn off when it is at low level for example. Wherein, the driving unit 220 drives the synchronous switch tube MP to turn off when the inductance current IL reaches the zero-crossing point represented by the zero-crossing detection signal ZCD. The zero-crossing detection circuit is used to output zero-crossing detection signal ZCD according to the size relationship of the voltage across the synchronous switch tube MP. The zero-crossing detection circuit includes comparator 240, turn-on time control circuit 250 and adjustable delay circuit 260.

[0043] Optionally, the zero-crossing detection signal ZCD is represented by the second level flipping to the first level when the inductance current IL reaches the zero-crossing point. The first level can be low level or high level, and the second level is low level when the first level is high level, and the second level is high level when the first level is low level. In subsequent embodiments, the first level is high level and the second level is low level are taken as examples.

[0044] The comparator 240 is used to compare the voltage Vsw of the switch node SW and the output voltage Vout to obtain a comparison signal Q according to the comparison result. The comparator 240, for example, adopts a dynamic comparator. Alternatively, the comparator 240 only works once in a switching period (i.e. the interval time between the two off moments of the synchronous switch tube MP), i.e. it only compares the voltage Vsw and the output voltage Vout at the off moment of the synchronous switch tube MP.

[0045] Alternatively, the positive and negative input terminals of the comparator 240 are connected to the first end (i.e. the switch node SW) and the second end (i.e. the output end of the switch converter 200) of the synchronous switch tube MP respectively, and the output terminal provides the comparison signal Q. Therefore, when Vsw>Vout, Q=1.

[0046] Alternatively, the comparator 240 compares the voltage Vsw and the output voltage Vout in the high voltage domain of Vout-5V to Vout, and converts the comparison result through the internal level converter thereof to obtain the comparison signal Q in the low voltage domain.

[0047] The on-time control circuit 250 is connected to the output terminal of the comparator 240, and is used to generate an on-time control signal T <n:0>and provides it to the adjustable delay circuit 260 to control the on-time of the synchronous switch tube MP.

[0048] The adjustable delay circuit 260 is used to control the on-time of the synchronous switch tube MP according to the on-time control signal T <n:0>The conduction duration of the synchronous switch tube MP in each switching cycle is adjusted. The adjustable delay circuit 260 includes a delay capacitor 263 and a current source 261 charging the delay capacitor 263. The adjustable delay circuit 260 is used to control the synchronous switch tube MP to be turned off when the voltage of the delay capacitor 263 is charged to a set threshold value, so as to control the conduction duration of the synchronous switch tube MP in each switching cycle. In addition, the adjustable delay circuit 260 is also used to control the conduction duration of the synchronous switch tube MP according to the conduction time control signal T <n:0>The capacitance value of the delay capacitor 263 is adjusted to adaptively adjust the conduction time of the synchronous switch tube MP in each switching cycle. The charging current I provided by the current source 261 follows the voltage difference between the preset output voltage Vout1 and the input voltage Vin. The delay capacitor 263 needs to complete the adjustment of the capacitance value before the main switch tube MN is turned off.

[0049] The on-time control circuit 250 is also used to perform increment / decrement counting operation according to the level state of the comparison signal Q in each switching cycle, so as to generate the on-time control signal T <n:0>.

[0050] Figure 4 A circuit schematic diagram of the turn-on time control circuit is shown according to an embodiment of the utility model.

[0051] Referring to Figure 4 , the turn-on time control circuit 250 comprises a D flip-flop 252 and an add-subtract counter 255.

[0052] The D flip-flop 252 is used for sampling and holding the comparison signal Q to obtain a trigger signal Q1 corresponding to the level state of the comparison signal Q in each switching cycle. The D flip-flop 252 has an input end D, a clock end Clk, a reset end Reset and an output end Q, the input end D receives the comparison signal Q, the clock end Clk receives a clock signal clk_q, the reset end Reset receives an enable signal en_auto, and the output end Q provides the trigger signal Q1. The enable signal en_auto is an enable signal of the zero-crossing detection circuit.

[0053] The add-subtract counter 255 is used for performing an add-subtract operation according to the value of the trigger signal Q1 to adjust the turn-on time control signal T <n:0>of the current switching period trigger signal Q1 is 1, the up-down counter 255 counts the on-time control signal T of the previous switching period. If the value of the current switching period trigger signal Q1 is 0, the up-down counter 255 counts the off-time control signal S of the previous switching period. The up-down counter 255 outputs the counted value to the comparator 260. <n:0>A plus 1 operation is performed to obtain the on-time control signal T of the current switching period <n:0>, if the value of the current switching period trigger signal Q1 is 0, the add-subtract counter 255 adds the on-time control signal T <n:0>performing a subtract 1 operation to obtain the on-time control signal T of the current switching period <n:0>Optionally, the turn-on time control signal T <n:0>The n+1 (n>0) bit binary digital signal is composed, and the on-time control signal T <n:0>The greater the value is, the longer the on-time of the synchronous switch tube MP is. The add-subtract counter 255 also receives an enable signal en auto.

[0054] The on-time control circuit 250 further comprises a delay circuit 251, a count control module 253 and a SAR logic circuit 254.

[0055] The delay circuit 251 is used to control the working sequence of the D flip-flop 252, the count control module 253, the SAR logic circuit 254 and the add-subtract counter 255 in each switching cycle. Specifically, the delay circuit 251 obtains clock signals clk q, clk check, clk SAR and clk count by delaying the clock signal clk in different ways, and provides the clock signals clk q, clk check, clk SAR and clk count to the D flip-flop 252, the count control module 253, the SAR logic circuit 254 and the add-subtract counter 255 respectively.

[0056] The delay circuit 251 can be implemented by any delay circuit in the prior art. For example, the delay circuit 251 comprises five buffers, which are connected between the clock signal clk and the clock signal clk count in sequence, and the clock signals clk q, clk check and clk SAR are provided by the outputs of the second to fourth buffers in sequence.

[0057] The SAR logic circuit 254 is used to provide a logic digital signal B to the add-subtract counter 255 when the zero-crossing detection circuit fails to calibrate the off-time of the synchronous switch tube MP by the add-subtract counter 255 within a set time (i.e. fails to make the synchronous switch tube MP turn off at the zero-crossing point of the inductor current IL within a set period). <n:0>so that the up-down counter 255 directly converts the logic digital signal B <n:0>The output is the on-time control signal T <n:0>.

[0058] The count control module 253 is configured to count the number of times that the trigger signal Q1 is continuously at the same level (i.e. count the number of times that the trigger signal Q1 is continuously at 0 or 1) in a plurality of continuous switching cycles to obtain a count value, and obtain the count enable signal en SAR according to the count value. The count enable signal en SAR is configured to control the working state of the add-subtract counter 255 and the SAR logic circuit 254. When the count enable signal en SAR is at the second level, the add-subtract counter 255 works in the add-subtract counting mode, and the SAR logic circuit does not work. When the count enable signal en SAR is at the first level, the add-subtract counter 255 works in the pass-through mode, and the SAR logic circuit 254 normally works. When the add-subtract counter 255 works in the add-subtract counting mode, it performs add-subtract operation according to the value of the trigger signal Q1 in each switching cycle to adjust the on-time control signal T <n:0>the value of the logic digital signal B <n:0>The output is the on-time control signal T <n:0>.

[0059] Optionally, the counting control module 253 counts the number of times that the trigger signal Q1 is continuously at the first level and the second level respectively by using the first counting value and the second counting value. Specifically, in the current switching period, if the trigger signal Q1 is at the first level, the first counting value is increased by 1 and the second counting value is reset to 0, and if the trigger signal Q1 is at the second level, the first counting value is reset to 0 and the second counting value is increased by 1. For example, when the first counting value and the second counting value are both less than a preset value Y, the counting enable signal en SAR is at the second level, and when the first counting value or the second counting value is greater than or equal to the preset value Y (Y > 1), it indicates that the zero-crossing detection circuit cannot complete the calibration of the synchronization switch tube MP off time in Y periods by using the adder-subtractor 255, at this time, the counting enable signal en SAR is at the first level. For example, the first level is high (i.e. 1) and the second level is low (i.e. 0). After the counting enable signal en SAR is flipped from the second level to the first level, the counting control module 253 will keep the counting enable signal en SAR at the first level until it receives the reset signal reset chk.

[0060] The counting control module 253 is also used to reset the counting values to 0 when the reset signal reset chk is received, that is, the first counting value and the second counting value are both reset to 0.

[0061] Figure 5 A circuit schematic diagram of the counting control module according to an embodiment of the present application is shown.

[0062] Referring to Figure 5 The counting control module 253 includes switches S11-S16, counters 253a and 253b, NOT gates 253c and 253g, comparators 253d and 253e, and an OR gate 253f. For example, the counters 253a and 253b can use any counter in the prior art, and the comparators 253d and 253e can use any comparator in the prior art.

[0063] The switches S11 and S13 are connected in sequence between the trigger signal Q1 and the input terminal of the counter 253a, the switch S15 is connected between the reset terminal of the counter 253a and the trigger signal Q1, the control terminal of the switch S11 receives the trigger signal Q1, the control terminals of the switches S13 and S15 receive the counting enable signal en SAR through the NOT gate 253g, the output terminal of the counter 253a provides the first counting value, and the two input terminals of the comparator 253d receive the first counting value and the preset value Y respectively, and the output terminal is connected to the first input terminal of the OR gate 253f.

[0064] Switches S14 and S12 are connected in sequence between the trigger signal Q1 and the input terminal of the counter 253b, the NOT gate 253c and the switch S16 are connected in sequence between the trigger signal Q1 and the reset terminal of the counter 253b, the control terminal of the switch S12 receives the trigger signal Q1 through the NOT gate 253c, the control terminals of the switches S14 and S16 receive the count enable signal en SAR through the NOT gate 253g, the output terminal of the counter 253b provides the second count value, the two input terminals of the comparator 253e receive the second count value and the preset value Y respectively, and the output terminal is connected to the second input terminal of the OR gate 253f, and the output terminal of the OR gate 253f provides the count enable signal en SAR.

[0065] The initial value of the count enable signal en SAR is 0, when en SAR = 0, the switches S13-S16 are turned on, if Q1 = 1, the switch S11 is turned on, the input terminal of the counter 253a receives the trigger signal Q1, the count value of the counter 253a is incremented by 1 to obtain the first count value, the comparator 253d compares the first count value with the preset value Y, and outputs the number 1 when the first count value is greater than or equal to Y, otherwise outputs the number 0, at the same time, the switch S12 is turned off, the connection between the input terminal of the counter 253b and the trigger signal Q1 is disconnected, and the reset terminal of the counter 253b receives the trigger signal Q1 through the NOT gate 253c, so that the second count value is reset to 0. If Q1 = 0, the switch S11 is turned off, the connection between the input terminal of the counter 253a and the trigger signal Q1 is disconnected, the reset terminal of the counter 253a receives the trigger signal Q1, so that the first count value is reset to 0, at the same time, the switch S12 is turned on, the input terminal of the counter 253b receives the trigger signal Q1, the count value of the counter 253b is incremented by 1 to obtain the second count value, the comparator 253e compares the second count value with the preset value Y, and outputs the number 1 when the second count value is greater than or equal to Y, otherwise outputs the number 0.

[0066] When en SAR = 1, the switches S13-S16 are turned off, the input terminal and the reset terminal of the counter 253a are disconnected from the trigger signal Q1, the input terminal and the reset terminal of the counter 253b are disconnected from the trigger signal Q1, the first count value and the second count value remain unchanged, and the count enable signal en SAR maintains a high level. When the reset signal reset chk comes, the reset signal reset chk is provided to the reset terminals of the counters 253a and 253b, so that the first count value and the second count value are reset, and en SAR is flipped to 0.

[0067] It can be understood that, Figure 5 The shown counting control module 253 is only one embodiment of the present application. Any circuit composed of logical circuit or other existing circuit elements and / or devices that can realize the function of the counting control module 253 of the present application is within the protection scope of the present application.

[0068] After the SAR logic circuit 254 is started, the logical digital signal B <n:0>reset, and then the trigger signal Q1 in the next consecutive n+1 switching cycles is converted into a logic digital signal B through a successive approximation algorithm <n:0>and outputs a reset signal reset_chk to the count control module 253 after the conversion is completed. The S AR logic circuit 254 also outputs a corresponding logic digital signal B <n:0>To add or subtract the counter 255.

[0069] Figure 6 A working schematic diagram of the SAR logic circuit is shown according to the embodiment of the utility model.

[0070] The working principle of the SAR logic circuit 254 is explained below Figure 6 The SAR logic circuit 254 is started when the count enable signal en_SAR is flipped from the second level to the first level, and after being started, the logic digital signal B <n:0>Reset, and the logical digital signal B <n:0>the highest bit n is set to 1, while the highest bit n is set to 1 and the remaining bits are 0 <n:0>Output to the up-down counter 255; if the next switch cycle trigger signal Q1 is 1, then the determination logic digital signal B <n:0>the highest bit is 1, if the trigger signal Q1 is 0 in the next switching cycle, the logic digital signal B <n:0>the highest bit of the result is 0, and then the logical digital signal B <n:0>a logic digital signal B with the highest bit x (x represents the value of the highest bit determined before) and the second highest bit 1, and the rest of the bits as 0 <n:0>Output to add-subtract counter 255; repeat the above process for n+1 cycles, and the logic digital signal B <n:0>The all bits are determined, the successive approximation operation ends, and the SAR logic circuit 254 outputs a reset signal reset_chk. The SAR logic circuit 254 may, for example, be implemented by any SAR logic circuit in the prior art.

[0071] Optionally, the active edge of the clock signal clk is synchronized with the turn-off time of the synchronous switch tube MP; the active edge of the clock signal clk_q has a certain delay relative to the active edge of the clock signal clk, so as to ensure that the D flip-flop 252 samples the comparison signal Q only after the comparator 240 outputs the comparison signal Q in each switching period; the active edge of the clock signal clk_check has a certain delay relative to the active edge of the clock signal clk_q, so as to ensure that the count control module 253 counts the trigger signal Q1 only after the trigger signal Q1 is stable; the active edge of the clock signal clk_SAR has a certain delay relative to the active edge of the clock signal clk_check, so as to ensure that the SAR logic circuit 254 performs the successive approximation operation only after the count enable signal en_SAR is output. The clock signal clk_count has a certain delay relative to the clock signal clk_SAR, so as to ensure that the add-subtract counter 255 starts to work only after the SAR logic circuit 254 or the count control module 253 completes the work in the current switching period.

[0072] Figure 7 A circuit schematic diagram of the adjustable delay circuit according to an embodiment of the present application is shown.

[0073] Referring to Figure 7 The adjustable delay circuit 260 further comprises a voltage comparison module 262, an output module 264, a control signal generation module 265, and switch tubes M1-M5.

[0074] The current source 261 is configured to receive an adjustment signal Vo_sel <m:0>and according to the output charging current I. Wherein the adjustment signal Vo_sel <m:0>The preset output voltage Vout1 is related to a preset output voltage Vout1, which can be selected by a register for example, and represents an output voltage desired by the switching converter 200. The charging current I is related to a voltage difference between the preset output voltage Vout1 and the input voltage Vin. The expression of the calibration accuracy of the charging current I is:

[0075] ,

[0076] wherein, represents the calibration accuracy of the charging current I, k represents a slope of the inductor current when the synchronous switch tube MP is turned on, L represents an inductance value of the inductor L, Vout1 represents the preset output voltage, Vin represents the input voltage of the switching converter 200, represents a calibration step of the turn-on time of the synchronous switch tube MP.

[0077] The relationship between the charging time t, the capacitance value C of the delay capacitor 263, the voltage V of the delay capacitor 263 and the charging current I is:

[0078] .

[0079] The switch tubes M4 and M2 are connected in sequence between the current source 261 and the charging path of the delay capacitor 263, and are used to turn on the charging path at the turn-on time of the synchronous switch tube MP, so as to output a first voltage signal Va at a first node between the switch tubes M4 and M2. The control end of the switch tube M4 receives a driving signal Lg_drv, and the control end of the switch tube M2 receives a control signal Vp.

[0080] The voltage comparison module 262 is connected with the first node, and is used to compare the first voltage signal Va with a set threshold value, so as to obtain a comparison signal Vb according to the comparison result.

[0081] The output module 264 is used to generate a zero-crossing detection signal ZCD according to the comparison signal Vb and the driving signal Lg_drv. Specifically, the output module 264 is used to perform AND operation on the inverse signal of the comparison signal Vb and the inverse signal of the driving signal Lg_drv to obtain the zero-crossing detection signal ZCD. When the voltage of the delay capacitor 263 is charged to the set threshold value, the zero-crossing detection signal ZCD controls the synchronous switch tube MP to be turned off.

[0082] The switch tube M5 is connected between a power supply voltage AVDD and the first node, and the control end of the switch tube M5 receives the control signal Vp. The switch tube M5 is used to be turned on when the first voltage signal Va rises to the set threshold value, so as to maintain the potential of the first node at the power supply voltage AVDD.

[0083] The switch tube M3 is connected between both ends of the delay capacitor 263, and the control end of the switch tube M3 receives the control signal Vpb. The switch tube M3 is used to be turned on when the first voltage signal Va rises to a set threshold value, so as to reset the voltage of the delay capacitor 263.

[0084] The control signal generation module 265 is used to generate the control signal Vpb and the control signal Vp opposite to the control signal Vpb according to the comparison signal Vb and the driving signal Lg_drv. Specifically, the control signal generation module 265 is used to perform an or non-operation on the comparison signal Vb and the driving signal Lg_drv to obtain the control signal Vpb, and to invert the control signal Vpb to obtain the control signal Vp. Wherein, the control signal Vpb is high only when the comparison signal Vb flips to low and the driving signal Lg_drv has not flipped from low to high, that is, only in the dead time between the turn-off time of the synchronous switch tube MP and the turn-on time of the main switch tube MN.

[0085] The switch tube M1 is connected between the first voltage signal Va and the ground end, and the control end of the switch tube M1 receives the driving signal Lg_drv. The switch tube M1 is used to be turned on when the main switch tube MN is turned on, so as to reset the voltage of the first node.

[0086] Specifically, the voltage comparison module 262 includes a current source 262a and a transistor M6 connected between the power supply voltage AVDD and the ground end in sequence, wherein the control end of the transistor M6 receives the first voltage signal Va, the output end of the current source 262a provides a bias current Ibias, and the intermediate node of the transistor M6 and the current source 262a provides the comparison signal Vb. The set threshold value is the threshold voltage Vth6 of the transistor M6. The working principle of the voltage comparison module 262 is that when the first voltage signal Va does not reach the set threshold value Vth6, the transistor M6 is turned off, and the current source 262a pulls up the comparison signal Vb to the power supply voltage AVDD. When the first voltage signal Va reaches the set threshold value Vth6, the transistor M6 is turned on to pull down the comparison signal Vb to the ground voltage.

[0087] The delay capacitor 263 includes a capacitor C FIX and a switched capacitor array 263a connected in parallel, wherein the capacitance value of the capacitor C FIX is fixed, and the capacitance value of the switched capacitor array 263a follows the turn-on time control signal T <n:0>variations. The switched capacitor array 263a includes n+1 capacitor branches, a first capacitor branch to an n+1th capacitor branch, respectively controlled by the on-time control signals T <n:0>The least significant bit to the most significant bit control, selectively interacting with capacitor C. FIX Parallel connection. Each capacitor branch includes a switch and a capacitor connected in series, with the capacitance values ​​of the first to the (n+1)th capacitor branches being 2. 0 C0, 2 1 C0……2 n C0. The voltage at the first terminal of delay capacitor 263 is the voltage of delay capacitor 263 itself. Calibration step size for the conduction time of synchronous switch MP. The calibration accuracy of the charging current I is related to the set threshold Vth6, the unit capacitance value C0, and the charging current I. It can also be expressed as:

[0088]

[0089] Where L represents the inductance value of the inductor, g fsw The coefficient represents the positive correlation with the switching frequency of the main switch transistor MN, C0 represents the unit capacitance value of the switched capacitor array 263a, and V represents the set threshold Vth6.

[0090] Output module 264 includes NOT gate 264a, NOT gate 264b, and AND gate 264c. The input of NOT gate 264a receives the comparison signal Vb. The input of NOT gate 264b receives the drive signal Lg_drv. The first input of AND gate 264c is connected to the output of NOT gate 264b, the second input of AND gate 264c is connected to the output of NOT gate 264a, and the output of AND gate 264c provides a zero-crossing detection signal ZCD.

[0091] The control signal generation module 265 includes NOT gate 265a, NOR gate 265b, and NOT gate 265c. The input of NOT gate 265a is connected to the output of NOT gate 264a. The first input of NOR gate 265b is connected to the output of NOT gate 265a, its second input receives the drive signal Lg_drv, and its output provides the control signal Vpb. The input of NOT gate 265c receives the control signal Vpb, and its output provides the control signal Vp.

[0092] Figure 8 A timing diagram of an adjustable delay circuit according to an embodiment of the present invention is shown.

[0093] The following is combined with Figure 8 Explain the working principle of the adjustable delay circuit 260, ignoring dead time, with Figure 8 When the switch period T in the figure is taken as an example, when the driving signal Lg_drv flips to high level, the main switch tube MN is turned on, the zero-crossing detection signal ZCD is low level, and the first voltage signal Va is pulled down to the ground voltage by the switch tube M1. When the driving signal Lg_drv flips to low level, i.e. the main switch tube MN is turned off, the zero-crossing detection signal ZCD remains low level, the synchronous switch tube MP starts to be turned on, the charging current I provided by the output end of the current source 261 charges the delay capacitor 263 through the switch tubes M4 and M2, and the voltage value of the first voltage signal Va starts to rise. When the voltage value of the first voltage signal Va rises to the threshold voltage Vth6 of the transistor M6, the transistor M6 is turned on, the comparison signal Vb is pulled down to the ground voltage, so that the zero-crossing detection signal ZCD flips to high level, the synchronous switch tube MP is turned off, the control signal Vpb flips to high level, the control signal Vp flips to low level, the switch tube M5 is turned on, the first voltage signal Va is pulled up to the power supply voltage AVDD, the switch tube M3 is turned on, and the delay capacitor 263 is discharged to the ground voltage, until the driving signal Lg_drv flips to high level, and a new switch period is started again.

[0094] Figure 9 The working schematic diagram of the zero-crossing detection circuit is shown.

[0095] The working principle of the zero-crossing detection circuit of the embodiment of the utility model will be described below. Figure 9 The working principle of the zero-crossing detection circuit of the embodiment of the utility model will be described below. When the comparison signal Q is 1, the first count value is added by 1, the second count value is reset to 0, when the comparison signal Q is 0, the first count value is reset to 0, and the second count value is added by 1, the count enable signal en_SAR is output according to the first count value and the second count value, and whether the count enable signal en_SAR is 0 is judged. <n:0>a plus 1 operation is performed, and the on-time control signal T is set to 0 when the comparison signal Q is 0 <n:0>The subtraction 1 operation is performed; if the count enable signal en_SAR = 1, the SAR logic circuit 254 is started, and the successive approximation operation on the comparison signal Q1 is performed by the SAR logic circuit 254 in the next n + 1 switching cycles, and the SAR logic circuit 254 also outputs the corresponding logic digital signal B in each switching cycle <n:0>As the on-time control signal T <n:0>And the adjustable delay circuit 260 turns off the synchronous switch tube MP after a preset time delay after the main switch tube MN is turned off to enter the next switching period.

[0096] Optionally, the switch tubes M1-M3 and the transistor M6 are N-channel Metal-Oxide-Semiconductor (NMOS) tubes, and the switch tubes M4 and M5 are P-channel Metal-Oxide-Semiconductor (PMOS) tubes.

[0097] The switch converter and the zero-crossing detection circuit thereof provided in the embodiment of the utility model, the comparator compares the voltage of the switch node with the output voltage of the switch converter to obtain the first comparison signal according to the comparison result; the on-time control circuit generates the on-time control signal according to the first comparison signal; the adjustable delay circuit is used for adjusting the on duration of the synchronous switch tube in each switching period according to the on-time control signal, thereby improving the light load efficiency of the switch converter.

[0098] Further, by setting the counting control module and the SAR logic circuit in the on-time control circuit, the switch converter can realize fast switching between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) of the inductor current when the load current suddenly changes, so that the switch converter can quickly enter a stable state.

[0099] Further, the adjustable delay circuit includes a delay capacitor and a first current source for charging the delay capacitor, and the adjustable delay circuit controls the synchronous switch tube to be turned off when the voltage of the delay capacitor is charged to a set threshold value; by setting the charging current provided by the first current source to be related to the voltage difference between the preset output voltage and the input voltage, the zero-crossing detection circuit can maintain the same accuracy under different preset output voltages, the synchronous switch tube can be accurately turned off at the zero-crossing point of the inductor current, and the light load efficiency of the switch converter is further improved.

[0100] It can be understood that the utility model further provides a chip, including the switch converter 200 described above.

[0101] It can be understood that the utility model further provides a display device, including a display panel for displaying images; a driving circuit for controlling the display state of the display panel; and the switch converter 200 described above. The switch converter 200 provides a stable power supply for the display device.

[0102] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details, nor limit the present application to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications on the basis of the present application. The protection scope of the present application should be limited by the scope defined by the claims of the present application and their equivalents.

Claims

1. A zero-crossing detection circuit for a switching converter, characterized by, The switch converter comprises a main switch tube and a synchronous switch tube, a common node of the main switch tube and the synchronous switch tube being a switch node, and the zero-crossing detection circuit comprises: a comparator configured to compare a voltage of the switch node with an output voltage of the switch converter to obtain a first comparison signal according to a comparison result; a conduction time control circuit configured to generate a conduction time control signal according to the first comparison signal; an adjustable delay circuit configured to adjust a conduction duration of the synchronous switch tube in each switching cycle according to the conduction time control signal.

2. The zero-crossing detection circuit of claim 1, wherein, The adjustable delay circuit comprises a delay capacitor and a first current source for charging the delay capacitor, and the adjustable delay circuit is configured to control the synchronous switch tube to be turned off when a voltage of the delay capacitor is charged to a set threshold value, so as to control the conduction duration of the synchronous switch tube in each switching cycle. The adjustable delay circuit is further configured to adjust a capacitance value of the delay capacitor according to the conduction time control signal, so as to adaptively adjust the conduction duration of the synchronous switch tube in each switching cycle.

3. The zero-crossing detection circuit of claim 2, wherein, The conduction time control circuit is configured to perform increment / decrement counting operation according to a level state of the first comparison signal in each switching cycle, so as to generate the conduction time control signal.

4. The zero-crossing detection circuit of claim 3, wherein, The conduction time control circuit comprises: a D flip-flop configured to sample and hold the first comparison signal in each switching cycle to obtain a trigger signal corresponding to the level state of the first comparison signal; an increment / decrement counter configured to perform increment / decrement operation according to a value of the trigger signal in each switching cycle to adjust a value of the conduction time control signal.

5. The zero-crossing detection circuit of claim 4, wherein, The conduction time control circuit further comprises: an SAR logic circuit configured to provide a logic digital signal to the increment / decrement counter when the zero-crossing detection circuit fails to calibrate a turn-off moment of the synchronous switch tube within a set time by the increment / decrement counter, so as to make the increment / decrement counter directly output the logic digital signal as the conduction time control signal.

6. The zero-crossing detection circuit of claim 5, wherein, The conduction time control circuit further comprises: a counting control module configured to count a number of times that the trigger signal is continuously at a same level in a plurality of continuous switching cycles to obtain a counting value, and obtain a counting enable signal according to the counting value, the counting enable signal being configured to control working states of the increment / decrement counter and the SAR logic circuit, wherein, when the counting enable signal is at a first level state, the increment / decrement counter is in a pass-through mode, and the SAR logic circuit works, when the counting enable signal is at a second level state, the increment / decrement counter is in an increment / decrement counting mode, and the SAR logic circuit does not work.

7. The zero-crossing detection circuit of claim 1, wherein, The comparator is a dynamic comparator, and the comparator compares the voltage of the switch node with the output voltage of the switch converter at a turn-off moment of the synchronous switch tube to obtain the first comparison signal according to a comparison result.

8. The zero-crossing detection circuit of claim 6, wherein, The count control module counts the number of times that the trigger signal is continuously at the first level and the second level by using a first count value and a second count value, resets one of the count values when the other count value is incremented by 1, and flips the count enable signal from the second level to the first level when the first count value or the second count value is greater than or equal to a preset value; The SAR logic circuit converts the trigger signal in a plurality of consecutive switching periods into a logic digital signal by using a successive approximation algorithm, and outputs a reset signal to the count control module after the conversion is completed, and the SAR logic circuit also outputs a corresponding logic digital signal to the add-subtract counter in each of the plurality of switching periods; The count control module is further configured to reset the count values after receiving the reset signal.

9. The zero-crossing detection circuit of claim 2, wherein, The adjustable delay circuit further comprises: a first switch and a second switch connected in sequence between the first current source and a charging path of the delay capacitor, the first switch and the second switch turn on the charging path at the turn-on moment of the synchronous switch to output a first voltage signal at a first node between the first switch and the second switch; a voltage comparison module connected with the first node, configured to compare the first voltage signal with the set threshold value to obtain a second comparison signal according to a comparison result; an output module configured to generate a zero-crossing detection signal according to the second comparison signal and a driving signal of the main switch, wherein when the voltage of the delay capacitor is charged to the set threshold value, the zero-crossing detection signal controls the synchronous switch to turn off.

10. The zero-crossing detection circuit of claim 9, wherein, The adjustable delay circuit further comprises: a third switch connected between a power supply voltage and the first node, the third switch turns on when the first voltage signal rises to the set threshold value to maintain the voltage of the first node at the power supply voltage; a fourth switch connected between the delay capacitor, the fourth switch turns on when the first voltage signal rises to the set threshold value to reset the voltage of the delay capacitor; a fifth switch connected between the first node and a ground terminal, the fifth switch turns on when the main switch turns on to reset the voltage of the first node.

11. The zero-crossing detection circuit of claim 10, wherein, The adjustable delay circuit further comprises: a control signal generation module configured to perform an OR operation on the second comparison signal and the driving signal of the main switch to obtain a first control signal, and perform an inversion operation on the first control signal to obtain a second control signal, the first control signal is provided to a control terminal of the fourth switch, and the second control signal is provided to control terminals of the second switch and the third switch; the output module is configured to perform an AND operation on an inverted signal of the second comparison signal and an inverted signal of the driving signal of the main switch to obtain the zero-crossing detection signal.

12. The zero-crossing detection circuit of claim 11, wherein, The charging current provided by the first current source to the delay capacitor is related to a voltage difference between a preset output voltage and an input voltage.

13. The zero-crossing detection circuit of claim 12, wherein The first current source receives an adjustment signal related to a preset output voltage and outputs the charging current; The voltage comparison module comprises: A second current source and a first transistor are connected in sequence between a power supply voltage and a ground terminal, a control terminal of the first transistor receives the first voltage signal, the second current source provides a bias current, and a middle node of the second current source and the first transistor provides the second comparison signal, and the set threshold value is equal to a threshold voltage of the first transistor; The delay capacitor comprises: A first capacitor and a switched capacitor array connected in parallel, the switched capacitor array comprises a plurality of capacitor branches with the same number of bits as the on-time control signal, and the first to last capacitor branches are controlled by the lowest to highest bits of the on-time control signal in sequence, and are selectively connected in parallel with the first capacitor.

14. A switching converter, characterized by Comprise: A main switch tube and a synchronous switch tube, and a middle node of the main switch tube and the synchronous switch tube is a switching node; An inductor connected to the switching node; A first drive unit for generating a first drive signal according to a first switch control signal to drive the main switch tube to turn on and turn off; A second drive unit for generating a second drive signal according to a second switch control signal to drive the synchronous switch tube to turn on and turn off; A PWM logic control circuit for providing the first switch control signal and the second switch control signal to the first drive unit and the second drive unit respectively; And The zero-crossing detection circuit of any one of claims 1-13 is used to provide the zero-crossing detection signal to the second drive unit.

15. A chip, characterized by The switching converter of claim 14 is included.

16. A display device comprising: Comprise: A display panel for displaying an image; A drive circuit for controlling the display state of the display panel; And The switching converter of any one of claims 1-13 is included.

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