Clock test board card and clock test system

Abstract

The embodiment of the utility model provides a clock test board card and a clock test system, the clock test board card is designed, a first control chip and at least one relay are arranged in the clock test board card, the at least one relay is responsible for connecting a to-be-tested clock and a test instrument, and the first control chip is used for testing the to-be-tested clock based on a clock test instruction of an industrial personal computer. The on-off states of the relays are controlled according to the test conditions of the to-be-tested clocks, so that the connection relations between the to-be-tested clocks and the various test instruments are switched, automatic test of various clock performances of the to-be-tested clocks is achieved, and a user can obtain various performance data of all the to-be-tested clocks only by starting the test after the test environment is established. The circuit does not need to be adjusted manually, and the clock testing efficiency and safety are improved.

Description

Technical Field

[0001] This disclosure relates to automated testing techniques, and in particular to a clock test board and a clock test system. Background Technology

[0002] During chip manufacturing and testing, the operating reference clock provides a time base for the chip's operation. Each chip under test (DUT) requires a dedicated operating reference clock, referred to as the user clock. The DUT on the load board has high performance requirements for the user clock; if the user clock performance is poor, the performance of the DUT will also be reduced. Therefore, it is usually necessary to perform performance testing on the user clock before conducting chip testing.

[0003] The performance indicators of user clocks mainly include power accuracy, frequency accuracy, phase noise, second harmonic magnitude, third harmonic magnitude, and spurious emissions, requiring testing with various instruments. Currently, user clock testing typically involves technicians manually connecting various user clocks to test instruments and manually switching between different instruments to perform various performance tests. However, this manual testing method results in low testing efficiency. Utility Model Content

[0004] This disclosure provides a clock test board and a clock test system that can improve the efficiency and security of clock testing.

[0005] In one aspect of this disclosure, a clock test board is provided, wherein the clock test board is provided with a first control chip and at least one relay;

[0006] One end of the at least one relay is connected to the corresponding clock under test, and the other end of the at least one relay is connected to the corresponding test instrument;

[0007] The first control chip is connected to the first communication link and is used to receive clock test commands sent by the industrial control computer through the first communication link, and control the switching state of the at least one relay based on the clock test commands, so as to realize the switching of the connection relationship between the clock under test and the test instrument.

[0008] Optionally, the clock test board also includes a driver chip;

[0009] In the at least one relay, each relay includes a relay coil and a relay switch, wherein the relay coil is used to trigger different switching states of the relay switch under different power supply voltages;

[0010] The input terminal of the driver chip is connected to the first control chip, and the output terminal of the driver chip is connected to the relay coil of the corresponding relay in the at least one relay. The driver chip is used to control the voltage value across each relay coil based on the clock test command sent by the first control chip, so as to drive the switching of the switching state of each relay switch in the at least one relay.

[0011] Optionally, the at least one relay is a single-pole multi-throw relay. The relay switch of the single-pole multi-throw relay includes a moving contact and at least two stationary contacts. The relay coil is used to trigger the moving contact to connect with different stationary contacts under different power supply voltages, so as to realize the connection relationship between the connected object at the moving contact end and the connected object at different stationary contact ends.

[0012] The clock test board includes a first relay module and a second relay module:

[0013] The first relay module includes m-level first relays. When m is greater than 1, the moving contact of each level of first relay is connected to a stationary contact of the corresponding next level of first relay, and the stationary contact of each level of first relay is connected to the moving contact of the corresponding previous level of first relay. The stationary contact of the first level of first relay is connected to the corresponding clock under test through a second communication link. The number of the m-th level of first relay is 1, and m is a positive integer.

[0014] The second relay module includes n levels of second relays. When n is greater than 1, the moving contact of each level of second relay is connected to a stationary contact of the corresponding next level of second relay, and the stationary contact of each level of second relay is connected to the moving contact of the corresponding previous level of second relay. The stationary contact of the first level of second relay is connected to the corresponding test instrument. The number of the nth level of second relay is 1, and n is a positive integer.

[0015] The moving contact of the first relay of the m-th stage in the first relay module is connected to the moving contact of the second relay of the n-th stage in the second relay module.

[0016] Optionally, the industrial control computer stores a truth table corresponding to the at least one relay. The truth table is used to indicate the voltage magnitude of each of the first relays and the second relays when each clock under test is connected to each test instrument. The industrial control computer is used to continuously generate the clock test instructions based on the clock test sequence and the truth table.

[0017] Optionally, the clock test board is mounted on a load board, which is used to load the chip under test during the chip testing phase. The load board is equipped with a clock block and a communication block.

[0018] The first control chip is connected to the first communication link through the communication block;

[0019] The at least one relay is connected to the second communication link through the clock block, and is used to receive the clock signal of the clock under test through the second communication link.

[0020] Optionally, the clock under test is set in the clock board of the test head, and the clock under test is connected to the second communication link through a connector, and the clock signal is sent through the second communication link;

[0021] The test head is also equipped with at least one resource board, which is used to provide test resources to the chip under test during the chip testing phase, and the at least one resource board is in operation during the testing of the clock under test.

[0022] Optionally, the test head is further provided with a main control board, and the main control board is provided with a second control chip;

[0023] The second control chip is connected to the industrial computer via a third communication link and to the first control chip via the first communication link. The second control chip is used to receive the clock test command sent by the industrial computer and to forward the clock test command to the first control chip.

[0024] In another aspect of the present disclosure, a clock testing system is provided, including an electrical cabinet, a test head, and a load board. The load board is equipped with a clock testing board as described above. An industrial control computer is installed in the electrical cabinet, and a main control board and a clock board are installed in the test head.

[0025] The clock board is equipped with at least one clock under test, and the at least one clock under test is connected to the clock test board.

[0026] The main control board is used to receive clock test commands sent by the industrial computer and forward the clock test commands to the clock test board, so that the clock test board controls the switching of the connection relationship between the clock under test and the test instrument based on the clock test commands.

[0027] Optionally, the test head is further provided with at least one resource board, which is used to provide test resources to the chip under test during the chip testing phase, and the at least one resource board is in operation during the testing of the clock under test.

[0028] Optionally, the electrical cabinet is further provided with a first power supply unit, and the test head is further provided with a second power supply unit. The first power supply unit is electrically connected to the second power supply unit, and the second power supply unit is electrically connected to the at least one resource board.

[0029] Based on the embodiments of this disclosure, a clock test board is designed, in which a first control chip and at least one relay are set. The at least one relay is responsible for connecting the clock under test and the test instrument. The first control chip controls the switching state of each relay based on the clock test instructions of the industrial control computer, thereby switching the connection relationship between each clock under test and various test instruments, realizing automated testing of various clock performances of multiple clocks under test. Users only need to start the test after the test environment is set up to obtain various performance data of all clocks under test without manually adjusting the circuit, thus improving the efficiency and safety of clock testing.

[0030] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0032] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0033] Figure 1 A schematic diagram of the structure of a clock test board provided in an exemplary embodiment of this disclosure;

[0034] Figure 2 A schematic diagram of a single-pole double-throw relay provided as an exemplary embodiment of this disclosure;

[0035] Figure 3 A simplified schematic diagram of a single-pole double-throw relay provided for an exemplary embodiment of this disclosure;

[0036] Figure 4 A schematic diagram of the structure of a clock test board provided in another exemplary embodiment of this disclosure;

[0037] Figure 5 A schematic diagram of the structure of a driver chip provided in an exemplary embodiment of this disclosure;

[0038] Figure 6 A schematic diagram illustrating the connection relationship between a first control chip, a driver chip, and a relay coil, provided for an exemplary embodiment of this disclosure;

[0039] Figure 7 A schematic diagram of the structure of a first relay module and a second relay module provided for an exemplary embodiment of this disclosure;

[0040] Figure 8 This is a schematic diagram of the structure of a load card provided in an exemplary embodiment of the present disclosure;

[0041] Figure 9 A schematic diagram illustrating the communication method between a clock test board and an industrial control computer, provided as an exemplary embodiment of this disclosure;

[0042] Figure 10 This is a schematic diagram of the structure of a clock testing system provided as an exemplary embodiment of the present disclosure.

[0043] The attached figures are labeled as follows:

[0044] Load cell board-1; Test head-2; Electrical cabinet-3;

[0045] Clock test board-101; Main control board-201; Clock board-202; Resource board-203; Second power supply unit-204; Industrial computer-301; First power supply unit-302;

[0046] First control chip - 101a; relay - 101b; driver chip - 101c; second control chip 201a. Detailed Implementation

[0047] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0048] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0049] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0050] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0051] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0052] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0053] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0054] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0055] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.

[0056] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0057] Figure 1 This is a structural block diagram of a clock test board 1 provided in an exemplary embodiment of the present disclosure. The clock test board 1 is provided with a first control chip 101a and at least one relay 101b.

[0058] At least one relay 101b has one end connected to the corresponding clock under test, and the other end connected to the corresponding test instrument. Illustratively, at least one relay 101b can be a single-pole single-throw relay, a single-pole double-throw relay, a double-pole four-throw relay, or other types of relays. All relays in at least one relay 101b can be of the same type, or multiple types of relays can be used; this disclosure does not limit this approach.

[0059] The first control chip 101a is connected to the first communication link and is used to receive clock test commands sent by the industrial control computer through the first communication link, and control the switching state of at least one relay 101b based on the clock test commands, so as to realize the switching of the connection relationship between the clock under test and the test instrument.

[0060] Indicatively, the first control chip 101a can be a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), etc. This embodiment uses an FPGA as an example for illustration. Test instruments may include, but are not limited to, a power meter (for testing power accuracy), a frequency meter (for testing frequency accuracy), a phase noise meter (for testing phase noise), and a spectrum analyzer (for testing the magnitude of the second harmonic, the third harmonic, spurious emissions, etc.).

[0061] Optionally, the industrial control computer runs a clock test program that generates clock test commands according to a preset test sequence (the order of the clocks under test and the order of the performance tests corresponding to each clock under test), and sends the clock test commands to the first control chip 101a through the first communication link. The first control chip 101a controls the switching state of each relay 101b according to the test sequence indicated by the clock test commands. Optionally, at any given time, one clock under test is connected to one (or more) test instruments, while the clock under test is disconnected from other test instruments, and other clocks under test are disconnected from each test instrument. After completing the current performance test (e.g., reaching a preset time interval or acquiring corresponding performance data from the test instrument), the next switching of the relay 101b is performed, until all performance tests of all clocks under test are completed.

[0062] Based on the embodiments of this disclosure, a clock test board is designed, in which a first control chip and at least one relay are set. The at least one relay is responsible for connecting the clock under test and the test instrument. The first control chip controls the switching state of each relay based on the clock test instructions of the industrial control computer, thereby switching the connection relationship between each clock under test and various test instruments, realizing automated testing of various clock performances of multiple clocks under test. Users only need to start the test after the test environment is set up to obtain various performance data of all clocks under test without manually adjusting the circuit, thus improving the efficiency and safety of clock testing.

[0063] Optionally, in at least one relay 101b, each relay 101b includes a relay coil and a relay switch, wherein the relay coil is used to trigger different switching states of the relay switch corresponding to different power supply voltages. Figure 2A schematic diagram of a single-pole double-throw (SPDT) relay is shown. Pins a and b of the SPDT relay are the pins at both ends of the relay coil, pin f is the common terminal of the relay switch (moving contact), and pins c and e are the two switchable stationary contacts of the relay switch. When the relay coil is not powered (or at a low level), the SPDT relay is in its default state, and pins c and f are connected. When the power supply voltage across the relay coil reaches a preset voltage value (e.g., 5V), the coil starts to operate, pins c and f are no longer connected, and the connection switches to pins e and f. Figure 3 A simplified schematic diagram of a single-pole double-throw relay is shown, as follows: Figure 3 As shown, the single-pole double-throw relay Kn is simplified to a relay switch and a relay coil. The voltage change of the right relay coil will cause the switching state of the left relay switch to change.

[0064] Since the first control chip 101a cannot directly control the voltage across the relay coil, voltage control of the relay coil can be achieved by setting a driver. In one possible implementation, such as... Figure 4 As shown, the clock test board 101 also includes a driver chip 101c.

[0065] The input terminal of the driver chip 101c is connected to the first control chip 101a, and the output terminal of the driver chip 101c is connected to the relay coil of the corresponding relay in at least one relay 101b. The driver chip 101c is used to control the voltage value across each relay coil based on the clock test command sent by the first control chip 101a, so as to drive the switching of the switching state of each relay switch in at least one relay 101b. Each output terminal of the driver chip 101c is connected to the relay coil of one relay 101b.

[0066] Indicatively, the driver chip 101c can be a ULN2001 chip, CN8023 chip, TPM2003 chip, etc. This disclosure uses the TPM2003 chip as an example for illustration. Figure 5 A schematic diagram of a driver chip 101c is shown. In the diagram, one TPM2003 chip can drive seven relays 101b. Figure 4 For example, such as Figure 6 As shown, when the clock test board 101 ( Figure 4 There are 18 relays 101b on it (including Figure 6 When using K1 to K18, at least three TPM2003 chips are required for driving. Figure 5As shown, the TPM2003 chip has the same 7-channel driver circuit structure. Taking one of the channels as an example, when the voltage at the IN1 terminal (input terminal) is greater than or equal to 1.5V, the TPM2003 chip recognizes that the IN1 terminal has a high level input and controls the N-MOS transistor at the OUT1 terminal (output terminal) to conduct. The OUT1 terminal is connected to the signal ground, thereby generating a 5V voltage drop across the relay coil of the relay 101b connected to the OUT1 terminal, causing the relay coil to start working, and the relay switch switches to the point where pins e and f are connected. Figure 3 When the voltage at IN1 is less than 1.5V, the TPM2003 chip recognizes that IN1 has a low level input and controls the N-MOS transistor at OUT1 (output terminal) to not conduct, disconnecting OUT1 from signal ground. This prevents a voltage drop across the relay coil of relay 101b connected to OUT1, causing the relay coil to stop working and the relay switch to return to its default state, i.e., pins c and f (…). Figure 3 ) connection. Therefore, the first control chip 101a ( Figure 4 This can be achieved by changing the input driver chip 101c. Figure 4 The voltage values ​​at each port are used to control at least one relay 101b. Figure 4 Switching between on / off states.

[0067] In one possible implementation, at least one relay 101b is a single-pole multi-throw (SPMD) relay. The SPMD relay switch includes one moving contact and at least two stationary contacts. The relay coil is used to trigger the moving contact to connect with different stationary contacts under different supply voltages, thereby establishing the connection relationship between the object connected to the moving contact and the objects connected to the different stationary contacts. For example, at least one relay 101b can be a single-pole double-throw (SPMD) relay, a single-pole four-throw (SPMD) relay, etc. This embodiment of the disclosure uses at least one SPMD relay 101b as an example.

[0068] The clock test board 101 includes a first relay module and a second relay module. The first relay module includes m levels of first relays. When m is greater than 1, the moving contact of each level of first relay is connected to a stationary contact of the corresponding next-level first relay, and the stationary contact of each level of first relay is connected to the moving contact of the corresponding previous-level first relay. The stationary contact of the first level of first relays is connected to the corresponding clock under test via a second communication link. The number of the m-th level of first relays is 1, and m is a positive integer. The second relay module includes n levels of second relays. When n is greater than 1, the moving contact of each level of second relay is connected to a stationary contact of the corresponding next-level second relay, and the stationary contact of each level of second relay is connected to the moving contact of the corresponding previous-level second relay. The stationary contact of the first level of second relays is connected to the corresponding test instrument. The number of the n-th level of second relays is 1, and n is a positive integer.

[0069] The moving contact of the m-th level first relay in the first relay module is connected to the moving contact of the n-th level second relay in the second relay module. When clock testing involves multiple clocks under test and various testing instruments, by setting up a first relay module and a second relay module, and designing the relays 101b in the first and second relay modules in a hierarchical manner, at least one relay 101b connected to a clock under test ultimately converges to a single first relay. By controlling the switching state of each first relay, the moving contact of the m-th level first relay can be connected to any clock under test. Similarly, by controlling the switching state of each second relay, the moving contact of the n-th level second relay can be connected to any testing instrument. The connection between the moving contact of the m-th level first relay in the first relay module and the moving contact of the n-th level second relay in the second relay module, combined with the control of the first and second relays, allows each clock under test to be connected to a different testing instrument.

[0070] Indicative Figure 7 The diagram illustrates the structure of a first relay module and a second relay module for performing four performance tests on 16 clock channels under test. Both modules employ single-pole double-throw relays with one channel automatically activated by default. Figure 7As shown, the first relay module includes 15 first relays. Each pair of clocks under test corresponds to two moving contacts of one first-level first relay, requiring a total of 8 first-level first relays. Each pair of stationary contacts of one first-level first relay corresponds to two moving contacts of one second-level first relay, requiring a total of 4 second-level first relays. Each pair of stationary contacts of one second-level first relay corresponds to two moving contacts of one third-level first relay, requiring a total of 2 third-level first relays. Each pair of stationary contacts of one third-level first relay corresponds to two moving contacts of one fourth-level first relay, requiring a total of 1 fourth-level first relay. The second relay module includes 3 second relays. Each pair of test instruments corresponds to two moving contacts of one first-level second relay via a connector, requiring a total of 2 first-level second relays. Each pair of stationary contacts of one first-level second relay corresponds to two moving contacts of one second-level second relay, requiring a total of 1 second-level second relay. The moving contacts of the fourth-level first relay are connected to the moving contacts of the second-level second relays.

[0071] Based on the embodiments of this disclosure, by implementing a layered design for at least one relay 101b, the number of relays 101b can be minimized while enabling any clock under test to be connected to any test instrument, thereby reducing the complexity of the circuit and the size and manufacturing cost of the clock test board 101.

[0072] In one possible implementation, the industrial control computer stores a truth table corresponding to at least one relay 101b. The truth table is used to indicate the voltage magnitude of each first relay and second relay when each clock under test is connected to each test instrument. The industrial control computer is used to continuously generate clock test instructions based on the clock test sequence and the truth table.

[0073] Optionally, the industrial control computer can store a first truth table corresponding to the first relay module and a second truth table corresponding to the second relay module, respectively. Table 1 illustrates this schematically. Figure 7 The first truth table corresponding to the first relay module shown in Table 2 is as follows: Figure 7 The second truth table corresponding to the second relay module is shown. Here, "low" indicates that a low-level control signal needs to be input to the corresponding port of the driver chip 101c, and "high" indicates that a high-level control signal needs to be input to the corresponding port of the driver chip 101c.

[0074]

[0075] Table 1

[0076]

[0077] Table 2

[0078] By storing truth tables and running test programs, industrial control computers can automatically switch each clock under test to connect to and test each type of test instrument, thus achieving automated testing.

[0079] In one possible implementation, such as Figure 8 As shown, the clock test board 101 is mounted on the load board 1. The load board 1 is used to load the chip under test during the chip testing phase. The load board 1 has a clock block (HPC block) and a communication block (block 1). Figure 9 As shown, the first control chip 101a is connected to the first communication link through communication block 1. Figure 10 As shown, at least one relay 101b is connected to the second communication link via a clock block (HPC block) to receive the clock signal of the clock to be tested via the second communication link.

[0080] Optionally, the frame shape of the clock test board 101 can be the same as that of the load board 1, and the size of the clock test board 101 is smaller than that of the load board 1. The clock test board 101 can be fixed to the communication block 1 and the clock block HPC block by means of automatic locking.

[0081] In one possible implementation, the clock under test (DUT) is housed in a clock board within the test head. The DUT is connected to a second communication link via a connector and transmits clock signals through this link. The test head also includes at least one resource board, which provides test resources to the chip under test during the chip testing phase, and this resource board is operational throughout the testing process of the DUT.

[0082] During chip testing, the operating reference clock for the chip under test (DUT) is placed in a standardized system environment. This system environment refers to an environment consistent with the equipment used by the user, constructed with standard electrical cabinets, standard test heads, and standard resource boards. Both the operating reference clock and resource boards are housed within the test head. Due to the presence of multiple resource boards, their operation can affect the performance of the operating reference clock through factors such as power supply quality, spatial radiated interference, or conducted interference. Clock testing in related technologies is typically conducted in an independent environment for the DUT. This independent environment refers to a separate clock test board powered by an external power supply, connected to the testing instrument. Therefore, the testing environment for related technologies is overly idealized, with clean power supplies and minimal external interference, making the test results unreliable.

[0083] This embodiment of the disclosure performs clock testing in a complete machine environment, controls the operation of resource boards, and simulates the environment in which the clock under test is located during chip testing. It can take into account various interferences that the clock under test is subjected to during actual operation, making the performance test results more reliable.

[0084] In one possible implementation, Figure 9 The communication link between the first control chip 101a and the industrial computer is shown. The test head also includes a main control board 201, which houses a second control chip 201a. The second control chip 201a is connected to the industrial computer 301 via a third communication link and to the first control chip 101a via a first communication link. The third communication link can be an optical communication link. The first communication link includes a connector on the main control board 201, a communication cable between the connector and communication block 1, and a communication link between the second control chip 201a and the connector. The second control chip 201a receives clock test commands from the industrial computer 301 and forwards clock test commands to the first control chip 101a.

[0085] This disclosure also provides a clock testing system. Figure 10 A schematic diagram of a clock testing system is shown. Figure 10 As shown, the clock testing system includes an electrical cabinet 3, a test head 2, and a load board 1. The load board 1 is equipped with a clock test board 101 as provided in the above embodiments. The electrical cabinet 3 is equipped with an industrial control computer 301, and the test head 2 is equipped with a main control board 201 and a clock board 202.

[0086] The clock board 202 is equipped with at least one clock under test, which is connected to the clock test board 101. The main control board 201 is used to receive clock test commands sent by the industrial computer 301 and forward the clock test commands to the clock test board 101, so that the clock test board 101 controls the switching of the connection relationship between the clock under test and the test instrument based on the clock test commands.

[0087] Optionally, the test head 2 is also provided with at least one resource board 203, which is used to provide test resources to the chip under test during the chip testing phase, and the at least one resource board 203 is in operation during the testing of the clock under test.

[0088] Optionally, the electrical cabinet 3 is also provided with a first power supply unit 302, and the test head 2 is also provided with a second power supply unit 204. The first power supply unit 302 is electrically connected to the second power supply unit 204, and the second power supply unit 204 is electrically connected to at least one resource board 203, thereby supplying power to at least one resource board 203 so that at least one resource board 203 can operate normally.

[0089] The clock testing system of this disclosure provides a complete machine environment for clock testing. By performing clock testing in this complete machine environment and controlling the operation of resource boards, the system simulates the environment in which the clock under test is located during chip testing. This takes into account various interferences that the clock under test is subjected to during actual operation, making the performance test results more reliable.

[0090] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or corresponding parts between embodiments can be referred to interchangeably. The basic principles of this disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the specific details required for its implementation.

[0092] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0093] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0094] The apparatus and device of this disclosure may be implemented in many ways. For example, the apparatus and device of this disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware.

[0095] It should also be noted that in the apparatus and equipment disclosed herein, the components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered as equivalent solutions to this disclosure.

[0096] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0097] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, adjustments, additions, and sub-combinations therein.

Claims

1. A clock test board, characterized in that, The clock test board is equipped with a first control chip and at least one relay. One end of the at least one relay is connected to the corresponding clock under test, and the other end of the at least one relay is connected to the corresponding test instrument; The first control chip is connected to the first communication link and is used to receive clock test commands sent by the industrial control computer through the first communication link, and control the switching state of the at least one relay based on the clock test commands, so as to realize the switching of the connection relationship between the clock under test and the test instrument.

2. The clock test board according to claim 1, characterized in that, The clock test board is also equipped with a driver chip; In the at least one relay, each relay includes a relay coil and a relay switch, wherein the relay coil is used to trigger different switching states of the relay switch under different power supply voltages; The input terminal of the driver chip is connected to the first control chip, and the output terminal of the driver chip is connected to the relay coil of the corresponding relay in the at least one relay. The driver chip is used to control the voltage value across each relay coil based on the clock test command sent by the first control chip, so as to drive the switching of the switching state of each relay switch in the at least one relay.

3. The clock test board according to claim 2, characterized in that, The at least one relay is a single-pole multi-throw relay. The relay switch of the single-pole multi-throw relay includes a moving contact and at least two stationary contacts. The relay coil is used to trigger the moving contact to connect with different stationary contacts under different power supply voltages, so as to realize the connection relationship between the connected object at the moving contact end and the connected object at different stationary contact ends. The clock test board includes a first relay module and a second relay module: The first relay module includes m-level first relays. When m is greater than 1, the moving contact of each level of first relay is connected to a stationary contact of the corresponding next level of first relay, and the stationary contact of each level of first relay is connected to the moving contact of the corresponding previous level of first relay. The stationary contact of the first level of first relay is connected to the corresponding clock under test through a second communication link. The number of the m-th level of first relay is 1, and m is a positive integer. The second relay module includes n levels of second relays. When n is greater than 1, the moving contact of each level of second relay is connected to a stationary contact of the corresponding next level of second relay, and the stationary contact of each level of second relay is connected to the moving contact of the corresponding previous level of second relay. The stationary contact of the first level of second relay is connected to the corresponding test instrument. The number of the nth level of second relay is 1, and n is a positive integer. The moving contact of the first relay of the m-th stage in the first relay module is connected to the moving contact of the second relay of the n-th stage in the second relay module.

4. The clock test board according to claim 3, characterized in that, The industrial control computer stores a truth table corresponding to the at least one relay. The truth table is used to indicate the voltage magnitude of each first relay and second relay when each clock under test is connected to each test instrument. The industrial control computer is used to continuously generate clock test instructions based on the clock test sequence and the truth table.

5. The clock test board according to any one of claims 1 to 4, characterized in that, The clock test board is mounted on the load board, which is used to load the chip under test during the chip testing phase. The load board is equipped with a clock block and a communication block. The first control chip is connected to the first communication link through the communication block; The at least one relay is connected to the second communication link through the clock block, and is used to receive the clock signal of the clock under test through the second communication link.

6. The clock test board according to claim 5, characterized in that, The clock under test is set in the clock board of the test head. The clock under test is connected to the second communication link through a connector and sends the clock signal through the second communication link. The test head is also equipped with at least one resource board, which is used to provide test resources to the chip under test during the chip testing phase, and the at least one resource board is in operation during the testing of the clock under test.

7. The clock test board according to claim 6, characterized in that, The test head is also equipped with a main control board, and the main control board is equipped with a second control chip; The second control chip is connected to the industrial computer via a third communication link and to the first control chip via the first communication link. The second control chip is used to receive the clock test command sent by the industrial computer and to forward the clock test command to the first control chip.

8. A clock testing system, characterized in that, It includes an electrical cabinet, a test head, and a load board. The load board is equipped with a clock test board as described in any one of claims 1 to 7. The electrical cabinet contains an industrial control computer, and the test head contains a main control board and a clock board. The clock board is equipped with at least one clock under test, and the at least one clock under test is connected to the clock test board. The main control board is used to receive clock test commands sent by the industrial computer and forward the clock test commands to the clock test board, so that the clock test board controls the switching of the connection relationship between the clock under test and the test instrument based on the clock test commands.

9. The clock testing system according to claim 8, characterized in that, The test head is also equipped with at least one resource board, which is used to provide test resources to the chip under test during the chip testing phase, and the at least one resource board is in operation during the testing of the clock under test.

10. The clock testing system according to claim 9, characterized in that, The electrical cabinet is also equipped with a first power supply unit, and the test head is also equipped with a second power supply unit. The first power supply unit is electrically connected to the second power supply unit, and the second power supply unit is electrically connected to the at least one resource board.

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