Power-on loop of solid state disk and solid state disk
By adding a buck converter circuit to the power management IC of the solid-state drive (SSD), the problem that the power management IC cannot cope with different flash memory power-on sequences is solved, realizing flexible adjustment of power-on sequences and cost-effectiveness, and promoting the rapid development of SSDs.
Patent Information
- Application Number
- CN202422823221.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-11-19
AI Technical Summary
The power management ICs of existing solid-state drives (SSDs) cannot flexibly meet the power-on timing requirements of different flash memory flash memory, resulting in the inability to flexibly adjust the power-on timing of SSDs.
Based on the original power management integrated circuit, a buck converter circuit is added. By receiving the control signal from the solid-state drive controller, the output signal of the power output unit to be adjusted is disconnected, and the buck converter circuit is used to power on the back end of the solid-state drive, so as to achieve flexible adjustment of the power-on timing.
Without altering the original power management integrated circuit circuitry, flexible adjustments to the power-on timing were achieved, reducing costs and accelerating the development process of solid-state drives.
Smart Images
Figure CN223539336U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of solid-state drive power supply technology, and in particular to a power-on circuit for a solid-state drive and a solid-state drive. Background Technology
[0002] During the research and development phase, different manufacturers have different power-on timing requirements for the flash memory when pairing SSD controllers with different flash memory chips. Currently, the power-on timing of the power management ICs in SSDs is fixed and cannot flexibly adapt to the different power-on timing requirements of flash memory chips. Utility Model Content
[0003] In view of this, the purpose of this utility model is to overcome the shortcomings of the prior art and provide a power-on circuit and solid-state drive for solid-state drives, which is used to change the power-on timing of the flash memory in the back end of the solid-state drive based on the original power management integrated circuit.
[0004] This utility model provides the following technical solution:
[0005] In a first aspect, this utility model proposes a power-on circuit for a solid-state drive, comprising: a power management integrated circuit and a buck converter circuit;
[0006] The power management integrated circuit includes: a power management chip and a power conversion module. The power management chip includes multiple power output units, and the power conversion module includes multiple power conversion units. Each power output unit is electrically connected to the back end of the solid-state drive through a power conversion unit.
[0007] The input terminal of the buck converter circuit is electrically connected to the main controller of the solid-state drive, and the output terminal of the buck converter circuit is electrically connected to the back end of the solid-state drive.
[0008] When there is a power output unit to be adjusted in each of the power output units, the output signal of the power conversion unit corresponding to the power output unit to be adjusted is disconnected, and the buck converter circuit powers on the back end of the solid-state drive.
[0009] In one specific embodiment, the buck converter circuit includes a voltage conversion chip and a voltage divider module;
[0010] The first input terminal of the voltage conversion chip is electrically connected to the power supply terminal, and the second input terminal of the voltage conversion chip is electrically connected to the main controller of the solid-state drive.
[0011] The first output terminal of the voltage conversion chip is electrically connected to the input terminal of the voltage divider module, and the third input terminal of the voltage conversion chip is electrically connected to the first output terminal of the voltage divider module.
[0012] The second output terminal of the voltage divider module is grounded.
[0013] In one specific embodiment, the voltage conversion chip includes a power supply pin, an enable pin, an inductor pin, and a feedback pin;
[0014] The power pin is electrically connected to the power supply terminal, and the enable pin is electrically connected to the solid-state drive controller.
[0015] The inductor pin is electrically connected to the back end of the solid-state drive through the input terminal of the voltage divider module, and the feedback pin is electrically connected to the first output terminal of the voltage divider module.
[0016] The power supply pin is the first input terminal of the voltage conversion chip, and the enable pin is the second input terminal of the voltage conversion chip.
[0017] The inductor pin is the first output terminal of the voltage conversion chip, and the feedback pin is the third input terminal of the voltage conversion chip.
[0018] In one specific embodiment, the voltage divider module includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a switching transistor;
[0019] The input terminals of the first voltage divider resistor are electrically connected to the inductor pin and the rear end of the solid-state drive, respectively. The output terminals of the first voltage divider resistor are electrically connected to the feedback pin, the input terminals of the second voltage divider resistor and the third voltage divider resistor, respectively.
[0020] The output terminals of the second and third voltage divider resistors are both electrically connected to the input terminal of the switching transistor, and the output terminal of the switching transistor is grounded.
[0021] The input terminal of the first voltage divider resistor is the input terminal of the voltage divider module, the output terminal of the first voltage divider resistor is the first output terminal of the voltage divider module, and the output terminal of the switching transistor is the second output terminal of the voltage divider module.
[0022] In one specific embodiment, the buck converter circuit further includes a fourth resistor;
[0023] The enable pin is electrically connected to the solid-state drive controller via the fourth resistor.
[0024] In one specific embodiment, the buck converter circuit further includes a filtering module;
[0025] The first input terminal of the filtering module is electrically connected to both the power supply terminal and the first input terminal of the voltage conversion chip. The second input terminal of the filtering module is electrically connected to the first output terminal of the voltage divider module.
[0026] The first output terminal of the filtering module is electrically connected to the back end of the solid-state drive, and the second, third and fourth output terminals of the filtering module are all grounded.
[0027] In one specific embodiment, the filtering module includes a first filtering capacitor, a second filtering capacitor, and a third filtering capacitor;
[0028] The first terminal of the first filter capacitor is electrically connected to both the power supply terminal and the power supply pin. The first terminal of the second filter capacitor is electrically connected to the input terminal of the first voltage divider resistor. The first terminal of the second filter capacitor is electrically connected to the rear end of the solid-state drive through the first terminal of the third filter capacitor.
[0029] The second terminal of the first filter capacitor, the second terminal of the second filter capacitor, and the second terminal of the third filter capacitor are all grounded.
[0030] The first terminal of the first filter capacitor is the first input terminal of the filter module, the first terminal of the second filter capacitor is the second input terminal of the filter module, and the first terminal of the third filter capacitor is the first output terminal of the filter module.
[0031] The second terminal of the first filter capacitor is the second output terminal of the filter module, the second terminal of the second filter capacitor is the third output terminal of the filter module, and the second terminal of the third filter capacitor is the fourth output terminal of the filter module.
[0032] In one specific embodiment, the buck converter circuit further includes an LC circuit;
[0033] The inductor pin is electrically connected to the input terminal of the LC circuit, the first output terminal of the LC circuit is electrically connected to the input terminal of the first voltage divider resistor, and the second output terminal of the LC circuit is electrically connected to the feedback pin and the output terminal of the first voltage divider resistor, respectively.
[0034] In one specific embodiment, the voltage conversion chip includes a signal ground pin, a power ground pin, and a pad pin, all of which are grounded.
[0035] Secondly, this utility model proposes a solid-state drive, including the power-on circuit of the solid-state drive as described in the first aspect.
[0036] This utility model discloses a power-on circuit for a solid-state drive (SSD) and the SSD itself. The power-on circuit includes a power management integrated circuit (IC) and a buck converter circuit. The IC includes a power management chip and a power conversion module. The power management chip includes multiple power output units, and the power conversion module includes multiple power conversion units. Each power output unit is electrically connected to the back end of the SSD via a power conversion unit. The input terminal of the buck converter circuit is electrically connected to the SSD's main controller, and the output terminal is electrically connected to the back end of the SSD. When there is a power output unit to be adjusted among the power output units, the output signal of the power conversion unit corresponding to the power output unit to be adjusted is disconnected, and the buck converter circuit powers on the back end of the SSD. Thus, without changing the original circuitry of the IC, the power-on sequence can be changed by adding a buck converter circuit and receiving control signals from the SSD's main controller. This method is cost-effective, flexible, and can accelerate the development of SSDs. Attached Figure Description
[0037] To more clearly illustrate the technical solution of this utility model, the drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this utility model and therefore should not be regarded as a limitation on the protection scope of this utility model. In the various drawings, similar components are numbered similarly.
[0038] Figure 1 A schematic diagram of the power-on circuit of the solid-state drive proposed in this embodiment is shown;
[0039] Figure 2 A schematic diagram of the power management integrated circuit proposed in this embodiment is shown;
[0040] Figure 3 A schematic diagram of the fixed timing proposed in this embodiment is shown;
[0041] Figure 4 This embodiment shows a schematic diagram of the measured timing waveform before modification.
[0042] Figure 5 This embodiment shows a schematic diagram of the modified measured timing waveform.
[0043] Figure 6 A schematic diagram of the buck converter circuit proposed in this embodiment is shown.
[0044] Explanation of reference numerals in the attached diagram:
[0045] 100 - Power management integrated circuit; 200 - Buck converter circuit; 300 - Solid-state drive back-end; 400 - Solid-state drive controller; 101 - Power management chip; 102 - Power conversion module; 1011 - Power output unit; 1021 - Power conversion unit; 201 - Voltage conversion chip; 202 - Voltage divider module; 203 - Filtering module; 204 - LC circuit. Detailed Implementation
[0046] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.
[0047] The components of the present invention, as described and illustrated in the accompanying drawings, can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0048] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.
[0049] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this invention pertain. The terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this invention.
[0051] Example 1
[0052] This disclosure provides a power-on circuit for a solid-state drive (SSD) to change the power-on timing of the flash memory in the back end of the SSD, based on the existing power management integrated circuit.
[0053] Please see Figure 1 A power-on circuit for a solid-state drive includes a power management integrated circuit 100 and a buck converter circuit 200.
[0054] The power management integrated circuit 100 includes a power management chip 101 and a power conversion module 102. The power management chip 101 includes multiple power output units 1011, and the power conversion module 102 includes multiple power conversion units 1021. Each power output unit 1011 is electrically connected to the back end of the solid-state drive 300 through a power conversion unit 1021.
[0055] The input terminal of the buck converter circuit 200 is electrically connected to the solid-state drive controller 400, and the output terminal of the buck converter circuit is electrically connected to the back end of the solid-state drive 300.
[0056] When there is a power output unit to be adjusted in each of the power output units 1011, the output signal of the power conversion unit 1021 corresponding to the power output unit to be adjusted is disconnected, and the buck converter circuit 200 powers on the back end of the solid-state drive.
[0057] In this embodiment, the power management integrated circuit 100 is a complex system integrating power management and conversion functions to ensure that the solid-state drive controller 400 can obtain a stable and reliable power supply. The power management integrated circuit 100 consists of two main parts: a power management chip 101 and a power conversion module 102.
[0058] The power management chip 101 is the core component of the power management integrated circuit 100, responsible for monitoring and controlling the operation of the entire power system. This chip contains multiple power output units 1011, which are independent power supply sections within the chip, each capable of outputting a specific voltage or current.
[0059] The power conversion module 102 is another key component of the power management integrated circuit 100, responsible for converting the input power into voltage and current suitable for use by the solid-state drive backend 300. This module contains multiple power conversion units 1021, each an independent converter capable of converting the input power into the required output voltage.
[0060] In the power management integrated circuit 100, each power output unit 1011 is electrically connected to the input terminal of a power conversion unit 1021. This connection method ensures that the power management chip 101 can accurately control the input power of each power conversion unit 1021, thereby achieving precise regulation of the output voltage and current.
[0061] The outputs of all power conversion units 1021 are electrically connected to the back end of the solid-state drive (SSD), and the outputs of some power conversion units 1021 are electrically connected to the SSD controller 400. When the power management chip 101 receives a power-on command or detects that power needs to be supplied to the back end of the SSD 300, it sends a control signal to the corresponding power conversion unit 1021 through the power output unit 1011.
[0062] These control signals instruct the power conversion unit 1021 to start operating, converting the input power into voltage and current suitable for use by the solid-state drive back-end 300, and supplying power to the solid-state drive back-end 300 through its output terminal. In addition, some power conversion units 1021 also output control signals to the solid-state drive controller 400.
[0063] When the power-on timing of the SSD flash memory in the back end of the SSD needs to be adjusted, the power output unit to be adjusted is the power output unit A1 corresponding to the SSD flash memory. It is also necessary to determine the power output unit A0 corresponding to the previous power-on timing of the SSD flash memory after the power-on timing adjustment.
[0064] At this time, the input terminal of the buck converter circuit 200 receives the control signal pulled up by the power output unit A0 of the solid-state drive controller 400 to start the voltage signal conversion and output it to the solid-state drive flash memory to perform power-on.
[0065] Exemplary, in accordance with Figure 2 The power management chip 101 shown is powered on. Before timing adjustment, the timing during the power-on process is fixed as follows: Figure 3 As shown in the figure. CH1 to CH6 are power output units 1011.
[0066] from Figure 3 It can be seen that in the fixed timing, the timing of CH1 is before CH3, that is, the Default NAND CORE starts first and the FLASHIO starts later; but the requirement at this time is that the order of CH1 is after CH3.
[0067] Therefore, CH3, as the power output unit to be adjusted, disconnects the FLASH IO signal output by the power conversion unit 1021 corresponding to CH3 to the back end of the solid-state drive 300, and instead uses the buck converter circuit 200 to output the FLASH IO signal to the back end of the solid-state drive 300.
[0068] Please see Figure 4 Before disconnecting the FLASH IO signal output from the power conversion unit 1021 corresponding to CH3 to the solid-state drive flash memory in the solid-state drive back end 300, the timing waveform measured in the actual timing waveform is NAND CORE => Flash IO.
[0069] Please see Figure 5After replacing the output of the FLASH IO signal with a step-down converter circuit 200, the timing in the measured timing waveform changed to Flash IO => NAND CORE. Thus, the timing on the existing line was adjusted to meet the NAND specification requirements.
[0070] Please see Figure 6 In one specific embodiment, the buck converter circuit 200 includes a voltage conversion chip 201 and a voltage divider module 202.
[0071] The first input terminal of the voltage conversion chip 201 is electrically connected to the power supply terminal, and the second input terminal of the voltage conversion chip 201 is electrically connected to the solid-state drive controller 400.
[0072] The first output terminal of the voltage conversion chip 201 and the input terminal of the voltage divider module 202 are electrically connected to the back end 300 of the solid-state drive, and the third input terminal of the voltage conversion chip 201 is electrically connected to the first output terminal of the voltage divider module 202.
[0073] The second output terminal of the voltage divider module 202 is grounded.
[0074] In this embodiment, the power supply voltage is received from the power supply terminals +VIN and +VIN_REG_VDDFD through the first input terminal of the voltage conversion chip 201, and is used to power the buck converter circuit 200.
[0075] When CH5 is powered on, it outputs control signals to the SSD controller 400. At this time, the SSD controller 400 pulls up multiple general purpose input / output (GPIO) signals.
[0076] The voltage converter chip 201 receives one of the GPIOs from the solid-state drive controller 400 through the second input terminal to control the voltage converter chip 201 to start outputting the voltage signal VDDFD_DC. Therefore, CH3 will be powered on immediately after CH5.
[0077] If the voltage signal VDDFD_DC output by the voltage conversion chip 201 fluctuates, the voltage signal VDDFD_DC is divided by the voltage divider module 202 to obtain the voltage signal FB VDDFD.
[0078] The third input terminal of the voltage conversion chip 201 is electrically connected to the first output terminal of the voltage divider module 202. The third input terminal of the voltage conversion chip 201 can feed back the voltage signal FB VDDFD after voltage division to the voltage conversion chip 201, so that the voltage conversion chip 201 adjusts and outputs a stable voltage signal VDDFD_DC, thereby ensuring that the voltage divider module 202 outputs a voltage suitable for the operation of the solid-state drive back end 300 in the solid-state drive.
[0079] Among them, according to Figure 5 As can be seen, CH3 supplies power to the flash memory of the solid-state drive. When the output signal of CH3 is disconnected, the voltage conversion chip 201 outputs a stable voltage signal VDDFD_DC as a FLASH IO signal to power on the flash memory of the solid-state drive.
[0080] It should be noted that the buck converter circuit 200 also includes VIN_S13, which can be used to analyze fault detection points.
[0081] In one specific embodiment, the voltage conversion chip 201 includes a power supply pin VIN, an enable pin EN, an inductor pin LX, and a feedback pin FB.
[0082] The power pin VIN is electrically connected to the power supply terminal, and the enable pin EN is electrically connected to the solid-state drive controller 400.
[0083] The inductor pin LX is electrically connected to the back end 300 of the solid-state drive through the input terminal of the voltage divider module 202, and the feedback pin FB is electrically connected to the first output terminal of the voltage divider module 202.
[0084] The power supply pin VIN is the first input terminal of the voltage conversion chip 201, and the enable pin EN is the second input terminal of the voltage conversion chip 201.
[0085] The inductor pin LX is the first output terminal of the voltage conversion chip 201, and the feedback pin FB is the third input terminal of the voltage conversion chip 201.
[0086] In this embodiment, specifically, the power supply voltage is received from the power supply terminal through the power supply pin VIN of the voltage conversion chip 201.
[0087] After receiving one of the GPIOs from the SSD controller 400 via the enable pin EN of the voltage conversion chip 201, the voltage conversion chip 201 starts voltage conversion. Through the regulation of the feedback pin FB, the inductor pin LX of the voltage conversion chip 201 outputs a stable voltage signal to the back end of the SSD, thus powering it on.
[0088] In one specific embodiment, the voltage divider module 202 includes a first voltage divider resistor R1, a second voltage divider resistor R2, a third voltage divider resistor R3, and a switching transistor SW1.
[0089] The input terminal of the first voltage divider resistor R1 is electrically connected to the inductor pin LX and the back end 300 of the solid-state drive, respectively. The output terminal of the first voltage divider resistor R1 is electrically connected to the feedback pin FB, the input terminal of the second voltage divider resistor R2 and the input terminal of the third voltage divider resistor R3, respectively.
[0090] The output terminals of the second voltage divider resistor R2 and the third voltage divider resistor R3 are both electrically connected to the input terminal of the switching transistor SW1, and the output terminal of the switching transistor SW1 is grounded; the input terminal of the first voltage divider resistor R1 is the input terminal of the voltage divider module 202, the output terminal of the first voltage divider resistor R1 is the first output terminal of the voltage divider module 202, and the output terminal of the switching transistor SW1 is the second output terminal of the voltage divider module 202.
[0091] In this embodiment, voltage division is performed using a voltage divider module 202. The second voltage divider resistor R2 and the third voltage divider resistor R3 have different resistance parameters to meet different voltage division requirements.
[0092] For example, the resistance parameter of the first voltage divider resistor R1 is 205K / 1%, the resistance parameter of the second voltage divider resistor R2 is 200K / 1%, and the resistance parameter of the third voltage divider resistor R3 is 100K / 1%.
[0093] If the first voltage divider resistor R1 and the second voltage divider resistor R2 are selected, a voltage of 1.2V can be output. If the first voltage divider resistor R1 and the third voltage divider resistor R3 are selected, a voltage of 1.8V can be output.
[0094] In addition, the second voltage divider resistor R2 is electrically connected to the first input terminal of the switching transistor SW1, the third voltage divider resistor R3 is electrically connected to the second input terminal of the switching transistor SW1, and the output terminal of the switching transistor SW1 is grounded.
[0095] When the first voltage divider resistor R1 and the second voltage divider resistor R2 are selected, the first input terminal and the output terminal of the switching transistor SW1 are connected. When the first voltage divider resistor R1 and the third voltage divider resistor R3 are selected, the second input terminal and the output terminal of the switching transistor SW1 are connected, thereby achieving effective voltage division.
[0096] In one specific embodiment, the buck converter circuit 200 further includes a fourth resistor R4; the enable pin EN is electrically connected to the solid-state drive controller 400 through the fourth resistor R4.
[0097] In this embodiment, the enable pin EN is connected to the solid-state drive controller 400 through the fourth resistor R4, so that the voltage conversion chip 201 can stably receive the GPIO pulled up by the solid-state drive controller 400 to start the voltage conversion output.
[0098] In one specific embodiment, the buck converter circuit 200 further includes a filter module 203.
[0099] The first input terminal of the filter module 203 is electrically connected to the power supply terminal and the first input terminal of the voltage conversion chip 201, respectively, and the second input terminal of the filter module 203 is electrically connected to the first output terminal of the voltage divider module 202.
[0100] The first output terminal of the filter module 203 is electrically connected to the rear end 300 of the solid-state drive, and the second, third and fourth output terminals of the filter module 203 are all grounded.
[0101] In this embodiment, the filtering module 203 is used to filter out noise and spurious signals in the voltage signal, thereby providing a stable and clean voltage signal for the voltage conversion chip 201 and the solid-state drive backend 300, thus ensuring the stable operation and performance of the entire circuit system.
[0102] In one specific embodiment, the filtering module 203 includes a first filtering capacitor C1, a second filtering capacitor C2, and a third filtering capacitor C3.
[0103] The first end of the first filter capacitor C1 is electrically connected to the power supply terminal and the power supply pin VIN, respectively. The first end of the second filter capacitor C2 is electrically connected to the input terminal of the first voltage divider resistor R1. The first end of the second filter capacitor C2 is electrically connected to the back end 300 of the solid-state drive through the first end of the third filter capacitor C3.
[0104] The second terminal of the first filter capacitor C1, the second terminal of the second filter capacitor C2, and the second terminal of the third filter capacitor C3 are all grounded.
[0105] The first terminal of the first filter capacitor C1 is the first input terminal of the filter module 203, the first terminal of the second filter capacitor C2 is the second input terminal of the filter module 203, and the first terminal of the third filter capacitor C3 is the first output terminal of the filter module 203.
[0106] The second terminal of the first filter capacitor C1 is the second output terminal of the filter module 203, the second terminal of the second filter capacitor C2 is the third output terminal of the filter module 203, and the second terminal of the third filter capacitor C3 is the fourth output terminal of the filter module 203.
[0107] In this embodiment, the first end of the first filter capacitor C1 is electrically connected to the power supply terminal and the power supply pin VIN, respectively. The first filter capacitor C1 is used to smooth and filter the voltage input from the power supply terminal. The second end of the first filter capacitor C1 is grounded and connected to the ground potential of the circuit to form a complete current loop.
[0108] The first terminal of the second filter capacitor C2 is electrically connected to the input terminal of the first voltage divider resistor R1. Simultaneously, this terminal is also electrically connected to the back end of the solid-state drive 300 via the first terminal of the third filter capacitor C3. The first terminal of the third filter capacitor C3 is connected to the first terminal of the second filter capacitor C2 and is also electrically connected to the back end of the solid-state drive 300. The second filter capacitor C2 is used to further smooth and stabilize the voltage signal VDFDD_DC, obtaining the voltage signal +PWR VDFDD, to provide a stable voltage to the back end of the solid-state drive 300.
[0109] In one specific embodiment, the buck converter circuit 200 further includes an LC circuit 204; the inductor pin LX is electrically connected to the input terminal of the LC circuit 204, the first output terminal of the LC circuit 204 is electrically connected to the input terminal of the first voltage divider resistor R1, and the second output terminal of the LC circuit 204 is electrically connected to the feedback pin FB and the output terminal of the first voltage divider resistor R1, respectively.
[0110] In this embodiment, the LC circuit 204 consists of an inductor L1 and a capacitor C4. Inductors are typically used to store magnetic field energy, while capacitors are used to store electric field energy.
[0111] The combination of these two elements can create resonance in the circuit, thereby filtering or smoothing signals of a specific frequency. The smoothed and filtered voltage signal will be passed to the first voltage divider resistor R1 for further adjustment of the voltage level.
[0112] In one specific embodiment, the voltage conversion chip 201 includes a signal ground pin SGND, a power ground pin PGND, and a pad pin Exposed Pad, all of which are grounded.
[0113] In this embodiment, in the voltage conversion chip 201, the signal ground pin SGND, the power ground pin PGND, and the pad pin Exposed Pad are all grounded to ensure normal circuit operation and improve stability and reliability. These pins, through grounding, form a complete current loop and a common reference potential, providing the necessary conditions for the chip's normal operation. At the same time, grounding also helps reduce the impact of interference and noise, protecting the circuit from damage.
[0114] The power-on circuit for a solid-state drive (SSD) proposed in this embodiment includes a power management integrated circuit (IC) and a buck converter circuit. The IC includes a power management chip and a power conversion module. The power management chip includes multiple power output units, and the power conversion module includes multiple power conversion units. Each power output unit is electrically connected to the back end of the SSD via a power conversion unit. The input terminal of the buck converter circuit is electrically connected to the SSD's main controller, and the output terminal is electrically connected to the back end of the SSD. When there is a power output unit to be adjusted among the power output units, the output signal of the power conversion unit corresponding to the power output unit to be adjusted is disconnected, and the buck converter circuit powers on the back end of the SSD. Thus, without changing the original circuitry of the IC, the power-on sequence can be changed by adding a buck converter circuit and receiving control signals from the SSD's main controller. This method is cost-effective, flexible, and can accelerate the development of SSDs.
[0115] Example 2
[0116] In addition, this disclosure provides a solid-state drive, including the power-on circuit of the solid-state drive provided in embodiment 1, which will not be described again to avoid repetition.
Claims
1. A power-on circuit for a solid-state drive, characterized in that, include: Power management integrated circuits and buck converter circuits; The power management integrated circuit includes: a power management chip and a power conversion module. The power management chip includes multiple power output units, and the power conversion module includes multiple power conversion units. Each power output unit is electrically connected to the back end of the solid-state drive through a power conversion unit. The input terminal of the buck converter circuit is electrically connected to the main controller of the solid-state drive, and the output terminal of the buck converter circuit is electrically connected to the back end of the solid-state drive. When there is a power output unit to be adjusted in each of the power output units, the output signal of the power conversion unit corresponding to the power output unit to be adjusted is disconnected, and the buck converter circuit powers on the back end of the solid-state drive.
2. The power-on circuit of the solid-state drive according to claim 1, characterized in that, The buck converter circuit includes a voltage conversion chip and a voltage divider module; The first input terminal of the voltage conversion chip is electrically connected to the power supply terminal, and the second input terminal of the voltage conversion chip is electrically connected to the main controller of the solid-state drive. The first output terminal of the voltage conversion chip is electrically connected to the input terminal of the voltage divider module, and the third input terminal of the voltage conversion chip is electrically connected to the first output terminal of the voltage divider module. The second output terminal of the voltage divider module is grounded.
3. The power-on circuit of the solid-state drive according to claim 2, characterized in that, The voltage conversion chip includes a power supply pin, an enable pin, an inductor pin, and a feedback pin; The power pin is electrically connected to the power supply terminal, and the enable pin is electrically connected to the solid-state drive controller. The inductor pin is electrically connected to the back end of the solid-state drive through the input terminal of the voltage divider module, and the feedback pin is electrically connected to the first output terminal of the voltage divider module. The power supply pin is the first input terminal of the voltage conversion chip, and the enable pin is the second input terminal of the voltage conversion chip. The inductor pin is the first output terminal of the voltage conversion chip, and the feedback pin is the third input terminal of the voltage conversion chip.
4. The power-on circuit of the solid-state drive according to claim 3, characterized in that, The voltage divider module includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a switching transistor; The input terminals of the first voltage divider resistor are electrically connected to the inductor pin and the rear end of the solid-state drive, respectively. The output terminals of the first voltage divider resistor are electrically connected to the feedback pin, the input terminals of the second voltage divider resistor and the third voltage divider resistor, respectively. The output terminals of the second and third voltage divider resistors are both electrically connected to the input terminal of the switching transistor, and the output terminal of the switching transistor is grounded. The input terminal of the first voltage divider resistor is the input terminal of the voltage divider module, the output terminal of the first voltage divider resistor is the first output terminal of the voltage divider module, and the output terminal of the switching transistor is the second output terminal of the voltage divider module.
5. The power-on circuit of the solid-state drive according to claim 3, characterized in that, The buck converter circuit also includes a fourth resistor; The enable pin is electrically connected to the solid-state drive controller via the fourth resistor.
6. The power-on circuit of the solid-state drive according to claim 4, characterized in that, The buck converter circuit also includes a filtering module; The first input terminal of the filtering module is electrically connected to both the power supply terminal and the first input terminal of the voltage conversion chip. The second input terminal of the filtering module is electrically connected to the first output terminal of the voltage divider module. The first output terminal of the filtering module is electrically connected to the back end of the solid-state drive, and the second, third and fourth output terminals of the filtering module are all grounded.
7. The power-on circuit of the solid-state drive according to claim 6, characterized in that, The filtering module includes a first filtering capacitor, a second filtering capacitor, and a third filtering capacitor; The first terminal of the first filter capacitor is electrically connected to both the power supply terminal and the power supply pin. The first terminal of the second filter capacitor is electrically connected to the input terminal of the first voltage divider resistor. The first terminal of the second filter capacitor is electrically connected to the rear end of the solid-state drive through the first terminal of the third filter capacitor. The second terminal of the first filter capacitor, the second terminal of the second filter capacitor, and the second terminal of the third filter capacitor are all grounded. The first terminal of the first filter capacitor is the first input terminal of the filter module, the first terminal of the second filter capacitor is the second input terminal of the filter module, and the first terminal of the third filter capacitor is the first output terminal of the filter module. The second terminal of the first filter capacitor is the second output terminal of the filter module, the second terminal of the second filter capacitor is the third output terminal of the filter module, and the second terminal of the third filter capacitor is the fourth output terminal of the filter module.
8. The power-on circuit of the solid-state drive according to claim 4, characterized in that, The buck converter circuit also includes an LC circuit; The inductor pin is electrically connected to the input terminal of the LC circuit, the first output terminal of the LC circuit is electrically connected to the input terminal of the first voltage divider resistor, and the second output terminal of the LC circuit is electrically connected to the feedback pin and the output terminal of the first voltage divider resistor, respectively.
9. The power-on circuit of the solid-state drive according to claim 2, characterized in that, The voltage conversion chip includes a signal ground pin, a power ground pin, and a pad pin, all of which are grounded.
10. A solid-state drive, characterized in that, Includes the power-on circuit of the solid-state drive as described in any one of claims 1 to 9.