Package structure

Abstract

The utility model provides a packaging structure. The package structure includes a substrate, a wafer disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed over the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

Description

Technical Field

[0001] This disclosure relates to packaging technology, and more particularly to a packaging structure. Background Technology

[0002] Electronic components are evolving towards lighter, thinner, shorter, smaller, and higher-performance, high-efficiency components, resulting in increasingly higher heat generation per unit area. For example, the heat generated by a Pentium processor in the past was only 20W, while the Pentium 4 exceeded 80W, with CPU operating temperatures reaching over 150°C. According to the International Technology Roadmap for Semiconductors (ITRS), which predicts the future development of the semiconductor industry, in the next few years, the heat generation of low-end computers will increase from approximately 100W to nearly 120W, while the heat generation of high-end computers will rise significantly from 150W to over 180W. Operating frequencies will also increase from 2GHz to over 4GHz. As the functionality and heat power density of electronic components increase dramatically, the requirements for thermal management technology become increasingly stringent.

[0003] Thermal interface materials (TIMs) are widely used in integrated circuit (IC) packaging and electronic component heat dissipation. The main function of TIMs is to fill the contact gap between two materials, improve system heat dissipation, and effectively reduce thermal resistance. A good TIM should possess the following characteristics: (1) good heat dissipation properties, i.e., high thermal conductivity and low thermal resistance; (2) ease of assembly and rework; (3) high compressibility to withstand external compressive stress when fixed to the joint surface and to appropriately fill the gaps between interfaces to facilitate heat flow; (4) good wettability with electronic components and heat sinks; and (5) high reliability and long service life. Current TIMs mainly include thermal grease, elastomeric thermal pads, phase change materials, and low-melting-point alloys.

[0004] Although current packaging technology using thermal interface materials largely meets the requirements, it is not satisfactory in all aspects, and there is still room for improvement in terms of process simplification and manufacturing cost. Utility Model Content

[0005] The purpose of this invention is to propose a packaging structure to solve at least one of the above-mentioned problems.

[0006] This disclosure provides a packaging structure including: a substrate, a wafer disposed on the substrate and having a back surface away from the substrate, a heat sink disposed above the substrate and having a surface facing the back surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

[0007] According to one embodiment of the present invention, the wafer includes a metal layer located on the back surface of the wafer, the metal layer having a thickness of 0.001 to 10 micrometers.

[0008] According to one embodiment of the present invention, the wafer further includes an outermost metal layer adjacent to the thermal interface material, the outermost metal layer having a thickness of 0.001 to 10 micrometers.

[0009] According to one embodiment of the present invention, the outermost metal layer of the wafer is used to at least partially incorporate the thermal interface material.

[0010] According to one embodiment of the present invention, the heat sink includes a metal layer on the surface having a thickness of 0.001 to 10 micrometers.

[0011] According to one embodiment of the present invention, there are multiple wafers, and the metal layer of the heat sink includes multiple portions that are separated from each other, corresponding to the wafers.

[0012] According to one embodiment of the present invention, the heat sink further includes an outermost metal layer adjacent to the thermal interface material, the outermost metal layer having a thickness of 0.001 to 10 micrometers.

[0013] According to one embodiment of the present invention, there are multiple wafers, and the outermost metal layer of the heat sink includes multiple portions that are separated from each other, corresponding to the wafers.

[0014] According to one embodiment of the present invention, the outermost metal layer of the heat sink is used to at least partially incorporate the thermal interface material.

[0015] According to one embodiment of the present invention, there are multiple wafers, and the thermal interface material comprises multiple parts that are separated from each other, corresponding to the wafers.

[0016] According to one embodiment of the present invention, the thermal interface material is pure indium and has a melting point of 150°C to 160°C.

[0017] According to one embodiment of the present invention, the thermal interface material has a coverage of more than 90% on the wafer.

[0018] According to one embodiment of the present invention, the radiator is a heat dissipation metal cover and / or heat dissipation fins.

[0019] The beneficial effect of this utility model is that it provides a packaging structure that eliminates the need for an organic adhesive between the wafer and the heat sink. Because the thermal interface material is fixed to the wafer or heat sink through indentation bonding before the wafer and heat sink are pressed together, a temporary positioning effect is achieved for the thermal interface material, thereby preventing the thermal interface material from slipping before the heat sink and wafer are pressed together. Attached Figure Description

[0020] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model. It should also be noted that the accompanying drawings only illustrate typical embodiments of this disclosure and should not be considered as limiting its scope; this disclosure is equally applicable to other embodiments.

[0021] Figures 1 to 4 This is a cross-sectional schematic diagram illustrating various stages of the packaging structure process according to some embodiments of the present disclosure.

[0022] Figure 5 This is a cross-sectional schematic diagram of the packaging structure according to some embodiments of the present disclosure.

[0023] Figures 6 to 8 This is a cross-sectional schematic diagram illustrating various stages of the packaging structure process according to other embodiments of this disclosure.

[0024] Figures 9 to 13 The present disclosure provides further embodiments, illustrating cross-sectional schematic diagrams of various packaging structures.

[0025] The attached figures are labeled as follows:

[0026] 100, 200, 300, 400, 500, 600: Package structure

[0027] 102:Substrate

[0028] 104: Chip

[0029] 104S: Crystal back surface

[0030] 1040: Metal layer

[0031] 1042: Outermost metal layer

[0032] 106, 106A: Thermal interface materials

[0033] 108, 108F: Radiator

[0034] 108B: Bottom surface

[0035] 108C: Groove

[0036] 108S: Surface

[0037] 1080: Metal layer

[0038] 1082: Outermost metal layer

[0039] 110, 110C: Adhesive

[0040] 700: Pressure Head

[0041] 702: Indentation

[0042] 800: Hot pressing process

[0043] W1, W2: Width Detailed Implementation

[0044] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of the embodiments of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0045] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0046] The following describes some embodiments of the present invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. The packaging structure may add additional components. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a specific order, these steps may still be performed in another logical order.

[0047] In existing technologies, to prevent the thermal interface material from slipping before the heatsink and chip are laminated, thus failing to fill the contact gaps, an organic adhesive must first be used to bond the thermal interface material to the heatsink or chip. Therefore, in the package structure obtained after laminating the chip and heatsink, an organic adhesive (such as fixative or flux) exists between the heatsink and chip. The heat dissipation effect is affected by the properties of the organic adhesive itself. Furthermore, there are costs associated with obtaining and applying the organic adhesive, leading to an increase in final production costs. Additionally, solids in the organic adhesive may remain at the bonding interface, creating voids, which reduces the reliability of the package structure and results in incomplete adhesion between the thermal interface material and the chip or heatsink, further reducing heat dissipation.

[0048] To address the aforementioned issues, this disclosure employs an indentation bonding technique that eliminates the need for additional organic adhesives and allows for the fixation of the thermal interface material at room temperature (above 0°C). By applying pressure to the thermal interface material before bonding the wafer to the heatsink, the material directly contacts and is fixed to the wafer or heatsink, achieving temporary positioning and preventing slippage before bonding. This eliminates the need for organic adhesives found in existing technologies. Therefore, the packaging structure provided by this disclosure saves on the cost of acquiring and applying organic adhesives. Furthermore, because the thermal interface material directly contacts the wafer and heatsink, rather than being in contact with them through an organic adhesive, the heat generated during wafer operation can be directly conducted to the heatsink via the thermal interface material, resulting in superior heat dissipation.

[0049] Figures 1 to 4 This is a cross-sectional schematic diagram illustrating various stages of the process of the packaging structure 100 according to some embodiments of the present disclosure.

[0050] Reference Figure 1In one embodiment, a wafer 104 is disposed on a substrate 102. In some embodiments, the substrate 102 may include a printed circuit board (PCB), a wafer substrate, an integrated circuit (IC) substrate, an interposer, a wafer carrier, a circuit carrier, and a display device. In some embodiments, the wafer 104 may include a semiconductor wafer. A semiconductor wafer may be, for example, a small piece of semiconductor wafer formed by separating the semiconductor wafer into individual dies after performing semiconductor processes on the semiconductor wafer. The wafer 104 may include integrated circuits for processing and / or storing data, such as a field-programmable gate array (FPGA), a processing unit (e.g., a graphics processing unit (GPU)) or a central processing unit (CPU), an application-specific integrated circuit (ASIC), a memory device (e.g., a memory controller, a memory), etc. In some embodiments, the wafer 104 may include single crystals of the following materials: silicon (Si), germanium (Ge), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), and gallium nitride (GaN). In some embodiments, the wafer 104 may be attached to the substrate 102 using a polymer adhesive, solder, or a combination thereof.

[0051] In one embodiment, the wafer 104 has a back surface 104S that is remote from the substrate 102. Figure 1 (The surface of the wafer 104 facing upwards). In one embodiment, the wafer 104 may optionally include a metal layer 1040 on the back surface 104S and an outermost metal layer 1042 on the metal layer 1040. Specifically, the outermost metal layer 1042 is located on the side of the metal layer 1040 away from the substrate 102. In some embodiments, the metal layer 1040 and the outermost metal layer 1042 are configured to improve the heat dissipation effect of the package structure 100 and reduce the thermal resistance of the package structure 100, but this disclosure is not limited thereto.

[0052] In some embodiments, the metal layer 1040 may include at least one of the following: aluminum / titanium / nickel-vanadium (Al / Ti / NiV), aluminum / chromium / nickel-vanadium (Al / Cr / NiV), aluminum / nickel-vanadium (Al / NiV), aluminum / tungsten (Al / W), titanium / nickel-vanadium (Ti / NiV), titanium-tungsten (TiW), tungsten-titanium (WTi), tungsten-titanium / titanium (WTi / Ti), chromium / nickel-vanadium (Cr / NiV), chromium (Cr), tungsten (W), titanium / nickel (Ti / Ni), aluminum / titanium / nickel (Al / Ti / Ni), and titanium (Ti). In some embodiments, the thickness of the metal layer 1040 may be from 0.001 to 10 micrometers (e.g., 0.5 to 1.6 micrometers). In some embodiments, the outermost metal layer 1042 may include at least one of the following: gold (Au), silver (Ag), copper (Cu), rhodium (Rh), iridium (Ir), palladium (Pd), and platinum (Pt) or any suitable metallic material, and has a thickness of 0.001 to 10 micrometers (e.g., 0.1 to 2 micrometers). In some embodiments, the formation of the metal layer 1040 and the outermost metal layer 1042 may include sputtering, vapor deposition, electroplating or any suitable deposition process.

[0053] Reference Figures 2 to 3 In one embodiment, thermal interface material 106 is disposed on wafer 104 by indentation bonding. In some embodiments, thermal interface material 106 is configured to fill the gap between wafer 104 and heat sink 108 (shown in...). Figure 4 The contact gap between the components improves the overall heat dissipation of the package structure 100 and effectively reduces the thermal resistance of the package structure 100.

[0054] In some embodiments, the thermal interface material 106 is disposed on the wafer 104 by indentation bonding, specifically referring to... Figures 2 to 3 The downward arrow indicates the direction of pressure application. By applying pressure to the thermal interface material 106 (e.g., using an indenter 700), an indentation 702 is formed at the pressure point on the thermal interface material 106. Due to the pressure, diffusion bonding occurs between the thermal interface material 106 and the wafer 104, thus fixing the thermal interface material 106 onto the wafer 104. This achieves the effect of temporarily positioning the thermal interface material 106, preventing it from adhering to the heat sink 108 (shown in...). Figure 4 The chip can slide before being pressed with wafer 104, thus eliminating the need for setting the organic adhesive. Figure 2 The diagram illustrates applying pressure to a single point on the surface of the thermal interface material 106 using an indenter 700 to create an indentation 702. Figure 3 The diagram illustrates multi-point pressure application to the surface of the thermal interface material 106 using two pressure heads 700. It should be noted that although in Figures 2 to 3The illustration only shows single-point and two-point indentations, but this disclosure is not limited thereto. In other embodiments, single-point or multi-point pressure can be applied at any location on the surface of the thermal interface material 106 as needed, thereby forming single-point or more than two-point indentations on the thermal interface material 106, for example... Figures 2 to 3 In this process, pressure is applied to the thermal interface material 106 at one or more points (e.g., using a pressure head 700) in a direction toward the surface of the outermost metal layer 1042 of the wafer 104. Furthermore, although... Figures 2 to 3 The pressure head 700 and indentation 702 shown in the figures have circular outlines, but this disclosure is not limited thereto. In other embodiments, the pressure head 700 may have an outline of any shape, and the indentation 702 may have an outline corresponding to the pressure head 700. Furthermore, although the side of the pressure head 700 shown in the figures for applying pressure to the thermal interface material 106 at one or more points is hemispherical, this disclosure is not limited thereto. In other embodiments, it may also be a strip, a square, a matrix, a polygon, an irregular shape, or other different shapes.

[0055] In some embodiments, indentation bonding can be achieved by applying pressure to the surface of the thermal interface material 106 at a temperature greater than 0°C (e.g., 5°C, 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, 40°C, or greater than 40°C), and the pressure applied can be greater than 0.1 gf / mm². 2 (gf / mm 2 The thermal interface material 106 is fixed to the outermost metal layer 1042 for a period of time greater than 0.1 seconds (e.g., 0.5 seconds, 1 second, 5 seconds, 10 seconds, 15 seconds, 20 seconds, 25 seconds, 30 seconds, 45 seconds, 1 minute, or greater than 1 minute). In some embodiments, the indentation bonding involves applying pressure to the thermal interface material 106 at multiple points, wherein the force applied at each point is greater than 0.1 gf / mm. 2 (gf / mm 2 (For example, 0.5 gf / mm) 2 (gf / mm 2 ), 1 g / mm 2 (gf / mm 2 5 g / mm 2 (gf / mm 2 )wait).

[0056] In some embodiments, the thermal interface material 106 may include at least one of a phase transformation material, a metallic alloy, or any other suitable thermal interface material. In some embodiments, the thermal interface material may include an indium-based alloy. Hereinafter, "indium-based alloy" means an alloy comprising at least one indium, which may be formed of (1) indium and (2) at least one of bismuth, tin, and silver, such as an indium-bismuth alloy, an indium-bismuth-tin alloy, an indium-tin alloy, or an indium-silver alloy. In some embodiments, the indium-based alloy comprises at least one of the following: 30 to 35 wt% bismuth, 15 to 18 wt% tin, and the balance indium, having a melting point of 55 to 65°C; 30 to 35 wt% bismuth and the balance indium, having a melting point of 70 to 75°C; 52 to 60 wt% bismuth, 15 to 18 wt% tin, and the balance indium, having a melting point of 80 to 85°C; 48 to 50 wt% tin and the balance indium, having a melting point of 110 to 120°C; and 0.1 to 15 wt% silver and the balance indium, having a melting point of 140 to 280°C. In some embodiments, the thermal interface material may be pure indium, i.e., 100 wt% indium, having a melting point of 150 to 160°C.

[0057] Reference Figure 4 In one embodiment, a heat sink 108 is provided. In some embodiments, the heat sink 108 may be a metal lid and / or a finned heat sink, but this disclosure is not limited thereto, and any type and shape of heat dissipation device (e.g., heat pipes, cooling fans, water-cooled circulation heat dissipation elements, or other suitable heat dissipation elements) may be selected according to actual needs. As shown in the figure, in one embodiment, the heat sink 108 is a metal lid and has a recess 108C for accommodating the chip 104.

[0058] In some embodiments, the recess 108C is located on the side of the heat sink 108 adjacent to the wafer 104. Figure 4 The side of the heat sink 108 facing downwards), and the lateral width W1 of the groove 108C is greater than the lateral width W2 of the chip 104, to ensure that the heat sink 108 and the chip 104 are pressed together (on the side facing downwards), and the groove 108C has a lateral width W1 greater than the lateral width W2 of the chip 104. Figure 4 When the wafer 104 is placed in the recess 108C, the heat sink 108 may be accommodated in the recess. In some embodiments, the material of the heat sink 108 may include metals and / or metal alloys, such as copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), nickel-plated copper, or combinations thereof, or any suitable metallic material. In other embodiments, the heat sink 108 may also be a composite material, such as alloys, silicon carbide (SiC), aluminum nitride (AlN), graphite, the like, or combinations thereof.

[0059] In one embodiment, the heat sink 108 has a surface 108S corresponding to the back surface 104S of the wafer 104. In one embodiment, the surface 108S of the heat sink 108 ( Figure 4 The surface of the heat sink 108 facing downwards is located on the recess 108C of the heat sink 108. In one embodiment, the heat sink 108 may optionally include a metal layer 1080 located on the surface 108S and an outermost metal layer 1082 located on the metal layer 1080. Specifically, the outermost metal layer 1082 is located on the side of the metal layer 1080 away from the heat sink 108. In some embodiments, the metal layer 1080 and the outermost metal layer 1082 are configured to improve the heat dissipation effect of the package structure 100 and reduce the thermal resistance of the package structure 100, but this disclosure is not limited thereto.

[0060] In some embodiments, the metal layer 1080 may include at least one of the following: gold (Au), silver (Ag), copper (Cu), titanium (Ti), titanium / nickel (Ti / Ni), nickel (Ni), and tungsten (W). In some embodiments, the thickness of the metal layer 1080 may be from 0.001 to 10 micrometers (e.g., 0.5 to 1.6 micrometers). In some embodiments, the outermost metal layer 1082 may include at least one of the following: gold (Au), silver (Ag), copper (Cu), rhodium (Rh), iridium (Ir), palladium (Pd), and platinum (Pt) or any suitable metallic material, and have a thickness of 0.001 to 10 micrometers (e.g., 0.1 to 2 micrometers). In some embodiments, the formation of the metal layer 1080 and the outermost metal layer 1082 may include sputtering, vapor deposition, electroplating, or any suitable deposition process.

[0061] Still refer to Figure 4 In one embodiment, the heat sink 108 is bonded to the chip 104, with a thermal interface material 106 disposed between the chip 104 and the heat sink 108. In another embodiment, adhesive 110 is applied to the substrate 102, and then the bottom surface 108B of the heat sink 108 is bonded to the substrate 102 using the adhesive 110, allowing the heat sink 108 to directly contact the thermal interface material 106. Therefore, the thermal interface material 106 directly contacts both the chip 104 and the heat sink 108 simultaneously. Next, the thermal interface material 106 is melted using a hot-pressing process 800, and the adhesive 110 is simultaneously softened (i.e., the adhesive 110 forms a semi-cured adhesive 110C). This simplifies the process steps, reduces production costs, and shortens production time.

[0062] In one embodiment, the hot pressing process 800 may include applying a force greater than 1 gram per centimeter to the heat sink 108 in a process cavity at a temperature greater than 50°C (e.g., 135°C, 145°C, 155°C, or 165°C). 2 (gf / cm 2The force exerted (e.g., 55 gf / cm) 2 900 grams per centimeter 2 Or 3700 g / cm 2 The hot pressing process 800 can be performed for a duration of 2 seconds to 10 minutes (e.g., 5 seconds, 10 seconds, 20 seconds, 30 seconds, 45 seconds, 1 minute, 3 minutes, 5 minutes, etc.). The process chamber in which the hot pressing process 800 is performed can be a pressurized or vacuum process chamber. A pressurized process chamber is defined as a process chamber with an internal pressure greater than 1 atmosphere. A vacuum process chamber is defined as a process chamber with an internal pressure less than 1 atmosphere. By performing the hot pressing process 800 in a pressurized or vacuum process chamber, residual gas in the thermal interface material 106 can be effectively removed, thereby reducing the chance of voids forming between the thermal interface material 106 and the wafer 104 and heat sink 108, and increasing the coverage of the thermal interface material 106 on the wafer 104 (e.g., coverage greater than 90%, greater than 95%, or greater than 99%). This, in turn, improves the reliability and heat dissipation effect of the packaging structure 100. In this article, the term "coverage" refers to the ratio of the projected area of ​​the thermal interface material 106 on the wafer 104 projected onto the surface 108S of the heat sink 108 by ultrasound or X-ray to the projected area of ​​the wafer 104 projected onto the surface 108S of the heat sink 108 after the packaging process is completed. Generally speaking, the higher the coverage, the fewer pores are generated in the thermal interface material 106.

[0063] Figure 5 This is a cross-sectional schematic diagram of a packaging structure according to some embodiments of the present disclosure. In one embodiment, the packaging structure 100 includes a substrate 102, a wafer 104 disposed on the substrate 102, a heat sink 108 disposed above the substrate 102, and a thermal interface material 106 disposed between the wafer 104 and the heat sink 108. The wafer 104 has a back surface 104S away from the substrate 102. The heat sink 108 has a surface 108S facing the back surface 104S. There is no organic adhesive between the wafer 104 and the heat sink 108. In this embodiment, the thermal interface material 106 directly contacts the outermost metal layer 1042 on the wafer 104 and the outermost metal layer 1082 on the heat sink 108.

[0064] Still refer to Figure 5Since there is no organic adhesive between the chip 104 and the heat sink 108, the risk of pores caused by solid residues in the organic adhesive remaining at the bonding interface can be avoided, further improving the reliability and heat dissipation effect of the package structure 100. Therefore, in this embodiment, the heat generated by the chip 104 during operation is directly guided to the heat sink 108 through the thermal interface material 106. In contrast, in the prior art, there is an organic adhesive (such as fixative or flux) between the chip and the heat sink. Therefore, the heat dissipation effect is affected by the properties of the organic adhesive itself, and the solid residues in the organic adhesive may remain at the bonding interface, causing pores, which leads to a decrease in the reliability of the package structure and also results in incomplete adhesion between the thermal interface material and the chip and heat sink, leading to a decrease in heat dissipation effect.

[0065] Figures 6 to 8 These are cross-sectional schematic diagrams illustrating various stages of the packaging structure process according to other embodiments of this disclosure. It should be noted that processes or elements identical or similar to those in the foregoing embodiments will use the same element symbols, and their details will not be repeated. Compared to the foregoing embodiments where the thermal interface material 106 is disposed on the wafer 104, this embodiment first disposes of the thermal interface material 106 on the heat sink 108 via indentation bonding.

[0066] Reference Figure 6 In some embodiments, a heat sink 108 is provided. In this embodiment, the heat sink 108 is a heat-dissipating metal cover, and therefore the heat sink 108 has a recess 108C for accommodating the chip 104. However, this disclosure is not limited thereto, and any type and shape of heat dissipation device (e.g., heat sink fins, heat pipes, cooling fans, water-cooled circulation heat dissipation elements, or other suitable heat dissipation elements) can be selected according to actual needs.

[0067] Reference Figures 7 to 8 The thermal interface material 106 is disposed on the heat sink 108. The method of disposing the thermal interface material 106 on the heat sink 108 is to deposit the thermal interface material 106 onto the heat sink 108 through indentation bonding. Specifically, refer to... Figures 7 to 8 The upward arrow indicates the direction of pressure application. By applying pressure to the thermal interface material 106 (e.g., using an indenter 700), an indentation 702 is formed at the pressure point on the thermal interface material 106. Due to the pressure, diffusion bonding occurs between the thermal interface material 106 and the heat sink 108, thus fixing the thermal interface material 106 to the heat sink 108. This achieves the effect of temporarily positioning the thermal interface material 106, preventing the thermal interface material 106 from adhering to the wafer 104 (shown on the wafer 104). Figure 1 The device slides in position before being pressed against the heat sink 108, thus eliminating the need for applying an organic adhesive. Figure 7The diagram illustrates applying pressure to a single point on the surface of the thermal interface material 106 using an indenter 700 to create an indentation 702. Figure 8 The figure illustrates multi-point pressure application to the surface of the thermal interface material 106 using two indenters 700. It should be noted that although only single-point and two-point indentations are shown in the figures, this disclosure is not limited thereto. In other embodiments, single-point or multi-point pressure can be applied at any location on the surface of the thermal interface material 106 as needed, thereby forming single-point or more indentations on the thermal interface material 106, for example... Figures 7 to 8 In this process, pressure is applied to the thermal interface material 106 at one or more points in a direction toward the surface of the outermost metal layer 1082 of the heat sink 108 (e.g., using an indenter 700). Furthermore, although the indenter 700 and indentation 702 are shown in the figures to have circular outlines, this disclosure is not limited thereto; in other embodiments, the indenter 700 may have an outline of any shape, and the indentation 702 may have an outline corresponding to the indenter 700.

[0068] In some embodiments, indentation bonding can be achieved by applying pressure to the surface of the thermal interface material 106 at a temperature greater than 0°C, with the applied pressure being greater than 0.1 gf / mm. 2 (gf / mm 2 The indentation bonding process is performed for a duration greater than 0.1 seconds, thereby fixing the thermal interface material 106 onto the outermost metal layer 1082. In some embodiments, the indentation bonding involves applying pressure to the thermal interface material 106 at multiple points, wherein the force applied at each point is greater than 0.1 gf / mm². 2 (gf / mm 2 ).

[0069] Figures 7 to 8 Continued Figures 4 to 5 In one embodiment, the heat sink 108 is bonded to the chip 104, with a thermal interface material 106 disposed between the chip 104 and the heat sink 108. In another embodiment, adhesive 110 is applied to the substrate 102, and then the bottom surface 108B of the heat sink 108 is bonded to the substrate 102 using the adhesive 110, allowing the heat sink 108 to directly contact the thermal interface material 106. Therefore, the thermal interface material 106 directly contacts both the chip 104 and the heat sink 108 simultaneously. Next, the thermal interface material 106 is melted using a hot-pressing process 800, and the adhesive 110 is simultaneously softened (i.e., the adhesive 110 forms a semi-cured adhesive 110C). This simplifies the process steps, reduces production costs, and shortens production time.

[0070] Figures 9 to 13 The following are cross-sectional schematic diagrams of various packaging structures 200, 300, 400, 500, and 600, according to further embodiments of the present disclosure.

[0071] In some embodiments, Figure 9 The packaging structure 200 is similar to Figure 5 The packaging structure 100 differs in that the heat sink 108 bonded to the substrate 102 is a heat dissipation metal cover, and after the heat sink 108 is bonded to the chip 104, another heat sink 108F is provided on the heat dissipation metal cover, wherein the heat sink 108F is a heat dissipation fin. Therefore, the heat dissipation area is further increased by the heat dissipation fin, achieving a better heat dissipation effect. Specifically, in one embodiment, after the heat sink 108 is bonded to the chip 104, a thermal interface material 106A is provided on the surface of the heat sink 108 away from the chip 104, and then the heat sink 108F is provided on the thermal interface material 106A. The method of providing the thermal interface material 106A on the heat sink 108 can also be provided by indentation bonding, so that the thermal interface material 106A diffuses and bonds to the surface of the heat sink 108 away from the chip 104. After the heat sink 108F is provided on the thermal interface material 106A, it can also be provided by hot pressing process 800 (shown in Figure 4 The thermal interface material 106A is melted and filled to fill the contact gap between the heat sinks 108 and 108F.

[0072] In some embodiments, Figure 10 The packaging structure 300 is similar to Figure 5 The packaging structure 100 differs in that the heat sink 108 is a heat sink fin. Compared to a heat sink metal cover, the heat sink fin has a larger heat dissipation area, which can more quickly conduct the heat generated by the chip 104 during operation, achieving a better heat dissipation effect.

[0073] In some embodiments, Figure 11 The packaging structure 400 is similar to Figure 5 The packaging structure 100 differs in that multiple wafers 104 are disposed on the substrate 102, while a single thermal interface material 106 corresponds to multiple wafers 104. By covering all wafers 104 with a single thermal interface material 106, the process is simplified. It should be noted that although in Figure 11 Only two chips 104 are shown in the illustration, but this disclosure is not limited thereto. In other embodiments, various numbers of chips 104 may be provided on the substrate 102, such as three, four or more chips 104, depending on actual needs.

[0074] In some embodiments, Figure 12 The packaging structure of 500 is similar to Figure 11 The packaging structure 400 differs in that the thermal interface material 106 comprises multiple separate parts, each part corresponding to a different chip 104, rather than... Figure 11Multiple wafers 104 are addressed by using a single thermal interface material 106. By mapping multiple portions of the thermal interface material 106 to each wafer 104, a suitable thermal interface material 106 can be configured according to the differences in each wafer 104 (e.g., material properties or operating temperature of the wafer 104). Furthermore, since multiple wafers 104 are not addressed by a single thermal interface material 106, the amount of thermal interface material 106 used can be reduced, thereby lowering production costs.

[0075] In some embodiments, Figure 13 The packaging structure of 600 is similar to Figure 12 The packaging structure 500 differs in that the metal layer 1080 and the outermost metal layer 1082 of the heat sink 108 each include multiple separate parts, and the multiple parts of the metal layer 1080 correspond one-to-one with each chip 104, and the multiple parts of the outermost metal layer 1082 also correspond one-to-one with each chip 104. This allows for the setting of corresponding metal layers 1080 and outermost metal layers 1082 according to the differences in each chip 104 (e.g., material properties or chip 104 operating temperature). Furthermore, since multiple chips 104 are not represented by a single thermal interface material 106, the amount of thermal interface material 106 used can be saved, thereby reducing production costs. Although in Figure 13 The diagram shows multiple portions of the metal layer 1080 and multiple portions of the outermost metal layer 1082 of the heat sink 108, each corresponding one-to-one with a chip 104. However, this disclosure is not limited thereto, and the heat sink 108 may also include a single outermost metal layer 1082 (e.g., Figure 5 , Figures 9-12 The outermost metal layer 1082) and a metal layer 1080 having multiple parts separated from each other (e.g., Figure 13 The heat sink 108 may consist of a single metal layer 1080, and multiple portions of the metal layer 1080 correspond one-to-one with each wafer 104. Furthermore, in some embodiments, the heat sink 108 may also comprise a single metal layer 1080 (e.g., Figure 5 , Figures 9-12 Metal layer 1080) and outermost metal layer 1082 (e.g., having multiple portions separated from each other) Figure 13 The outermost metal layer 1082, and multiple portions of the outermost metal layer 1082 correspond one-to-one with each wafer 104.

[0076] Although Figures 11 to 13 The heat sink 108 is shown as a heat dissipation metal cover, but this disclosure is not limited to this; the heat sink 108 may also be a heat dissipation fin. Furthermore, another heat sink 108F may be mounted on top of the heat sink 108 (e.g., Figure 9 As shown in the figure, the 108F heat sink can be a heat dissipation fin to further increase the heat dissipation area and achieve a better heat dissipation effect.

[0077] In some embodiments, depending on the thickness of the outermost metal layers 1042, 1082, the outermost metal layers 1042, 1082 may be partially or completely integrated into the thermal interface material 106. This is because after packaging, the thermal interface material 106 reacts with the outermost metal layers 1042, 1082 at the junction of the thermal interface material 106 and the outermost metal layers 1042, 1082 due to heat generated during wafer operation. Therefore, when the thickness of the outermost metal layers 1042, 1082 is thin (e.g., gold with a thickness less than 0.1 μm), the outermost metal layers 1042, 1082 may be completely integrated into the thermal interface material 106. However, when the thickness of the outermost metal layers 1042, 1082 is thicker, since only a portion of the outermost metal layers 1042, 1082 is integrated into the thermal interface material 106, the remaining portion of the outermost metal layers 1042, 1082 that is not integrated into the thermal interface material 106 can still be observed.

[0078] The following describes some experimental and comparative examples of packaging structures of this disclosure to illustrate more specifically the effects that can be achieved by bonding the metal layer and the thermal interface material in the embodiments of this disclosure.

[0079] Comparative Example 1: Placing the thermal interface material directly on the wafer

[0080] Comparative Example 1 was prepared by first providing a wafer 104 having a metal layer 1040 (material is aluminum / titanium / nickel-vanadium) and an outermost metal layer 1042 (material is gold), and then directly bonding a 100 mm wafer to the wafer without using any organic adhesive. 2 Comparative Example 1 was prepared by placing a 10mm × 10mm thermal interface material 106 (made of 100 wt% indium) on the outermost metal layer 1042. Since no pressure was applied to the thermal interface material, the pressure applied is shown as 0.0 gf / mm in Table 1 below. 2 (gf / mm 2 ).

[0081] Experimental Examples 1-7: Setting thermal interface materials on wafers via indentation bonding

[0082] The fabrication method of Examples 1-7 is as follows: First, a wafer 104 with a metal layer 1040 (material is aluminum / titanium / nickel-vanadium) and an outermost metal layer 1042 (material is gold) is provided. Without using any organic adhesive, a 100 mm wafer is bonded together by indentation. 2A 10mm × 10mm thermal interface material 106 (made of 100wt% indium) is disposed on the outermost metal layer 1042 as a bonding step. Specifically, in an environment with a temperature of 18 to 20°C, the thermal interface material 106 is subjected to two-point pressure by an indenter 700, causing the thermal interface material 106 at the pressure point to diffusely bond with the outermost metal layer 1042 of the wafer 104, thereby preparing Experimental Examples 1-7. In Experimental Examples 1-7, the applied force at each point in the two-point pressure step is 1.0 gf / mm. 2 (gf / mm 2 ), 1.6 gf / mm 2 (gf / mm 2 ), 2.5 gf / mm 2 (gf / mm 2 ), 3.3 gf / mm 2 (gf / mm 2 ), 4.3 gf / mm 2 (gf / mm 2 ), 5.0 gf / mm 2 (gf / mm 2 ) and 5.8 gf / mm 2 (gf / mm 2 ).

[0083] [Connectivity Test]

[0084] After completing the preparation of Comparative Example 1 and Experimental Examples 1-7, the wafers 104 that had undergone the bonding step with the thermal interface material 106 in Comparative Example 1 and Experimental Examples 1-7 were respectively attached to the turntable of a spin tool. The turntable was then rotated at a set speed for 20 seconds, and it was observed whether the thermal interface material 106 on the wafer 104 had fallen off. The experimental results of the bonding test are shown in Table 1. In Table 1, "bonded" indicates that the thermal interface material 106 remained bonded to the wafer 104 after rotation, and "fallen off" indicates that the thermal interface material 106 fell off the wafer 104 after rotation.

[0085] [Table 1]

[0086]

[0087] According to the experimental results in Table 1, in Comparative Example 1, since the thermal interface material 106 was not fixed to the wafer 104 by indentation bonding, the thermal interface material 106 fell off the wafer 104 at a rotation speed of 10 rpm. In contrast, in Experiments 1-4, as the applied force at each point during two-point pressure increased (from 1.0 gf / mm²), the thermal interface material 106 fell off the wafer 104. 2 (gf / mm 2 Up to 3.3 gf / mm 2 (gf / mm2 The better the bonding between the thermal interface material 106 and the wafer 104, the better the adhesion. Furthermore, in Experiments 5-7, as the applied force at each point during two-point pressure increases to 4.3 gf / mm², the bonding becomes even stronger. 2 (gf / mm 2 Even at a high-speed rotation of 2,000 rpm, the thermal interface material 106 remains firmly bonded to the wafer 104. This confirms that fixing the thermal interface material 106 through indentation bonding can indeed achieve the effect of positioning the thermal interface material 106.

[0088] In summary, this disclosure provides a packaging structure that eliminates the need for an organic adhesive between the wafer and the heat sink. Before bonding the wafer and heat sink, the thermal interface material is fixed to the wafer or heat sink via indentation, achieving temporary positioning of the thermal interface material and preventing it from slipping before bonding. Since this disclosure eliminates the need for an organic adhesive to fix the thermal interface material, the cost of obtaining and applying the adhesive is saved, resulting in better heat dissipation. Furthermore, this disclosure avoids the risk of porosity caused by solid residues in the organic adhesive at the bonding interface, further improving the reliability and heat dissipation performance of the packaging structure.

[0089] The components of several embodiments are summarized above to facilitate a better understanding of the views expressed in the embodiments of this utility model by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this utility model, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this utility model.

Claims

1. A packaging structure, characterized in that, include: One substrate; A wafer is disposed on the substrate and has a back surface of crystal away from the substrate; A heat sink is disposed above the substrate, wherein the heat sink has a surface facing the back surface of the crystal. as well as A thermal interface material is disposed between the wafer and the heat sink, and there is no organic adhesive between the wafer and the heat sink.

2. The packaging structure as described in claim 1, characterized in that, The wafer includes a metal layer on the back surface of the wafer, the metal layer having a thickness of 0.001 to 10 micrometers.

3. The packaging structure as described in claim 2, characterized in that, The wafer also includes an outermost metal layer adjacent to the thermal interface material, the outermost metal layer having a thickness of 0.001 to 10 micrometers.

4. The packaging structure as described in claim 3, characterized in that, The outermost metal layer of the wafer is used to at least partially incorporate the thermal interface material.

5. The packaging structure as described in claim 1, characterized in that, The heat sink includes a metal layer on the surface, the metal layer having a thickness of 0.001 to 10 micrometers.

6. The packaging structure as described in claim 5, characterized in that, The chip is multiple, and the metal layer of the heat sink includes multiple separate portions corresponding to the chip.

7. The packaging structure as described in claim 5, characterized in that, The heat sink also includes an outermost metal layer adjacent to the thermal interface material, the outermost metal layer having a thickness of 0.001 to 10 micrometers.

8. The packaging structure as described in claim 7, characterized in that, The chip is multiple, and the outermost metal layer of the heat sink includes multiple separate portions corresponding to the chip.

9. The packaging structure as described in claim 7, characterized in that, The outermost metal layer of the heat sink is used to at least partially incorporate the thermal interface material.

10. The packaging structure as described in claim 1, characterized in that, The wafer is multiple, and the thermal interface material comprises multiple separate portions corresponding to the wafer.

11. The packaging structure as described in claim 1, characterized in that, The thermal interface material is pure indium and has a melting point of 150°C to 160°C.

12. The packaging structure as described in claim 1, characterized in that, The thermal interface material has a coverage of more than 90% on the wafer.

13. The packaging structure as described in claim 1, characterized in that, The radiator is a heat dissipation metal cover and / or heat dissipation fins.

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