Wafer sacrificial layer release tool

Abstract

The utility model discloses a wafer sacrificial layer release tool comprising a wafer used for manufacturing an electronic component; the wafer further comprises a supporting layer and an etching layer, the etching layer is arranged on the upper layer of the supporting layer, the etching layer is used for etching the chip release groove, and the supporting layer is a supporting tool; the etching layer is provided with a plurality of etching areas which are arranged in an array mode, each etching area is matched with a chip release groove, the chip release grooves are used for containing chips to be processed, and a groove position interval is arranged between every two adjacent chip release grooves. The diversity of tool manufacturing is optimized, and the efficiency of tool manufacturing is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, specifically a wafer sacrificial layer release tool. Background Technology

[0002] Uncooled infrared detectors for infrared imaging technology are widely used in military and civilian fields. Sacrificial layer release, a crucial process, still suffers from incomplete or unclean release, affecting the imaging and other performance characteristics of the finished product. Existing release methods include: one is direct contact, where the chip is placed directly on the heating platform of a plasma release device. Since this device operates in a vacuum environment, it requires alternating vacuuming, devastating, and ventilating processes. During this process, the chip's position is not constrained, leading to positional changes and affecting the later differentiation of different chip numbers. Another method uses a high-temperature resistant quartz disk, which is an indirect contact method. This disk has uniformly sized slots to limit chip positional changes during release. However, the added release fixture can cause uneven heat transfer, resulting in residual adhesive on the sacrificial layer. Therefore, a new wafer sacrificial layer release fixture is needed. Summary of the Invention

[0003] This application provides a method for etching uniformly sized slots on a silicon wafer using a through-silicon via (TSV) etching process, with the depth of the slots greater than the thickness of the chip. The chip is then placed inside the slot, and a release fixture is used to place the chip.

[0004] This application provides a wafer sacrificial layer release tooling, including a wafer, for fabricating electronic components;

[0005] The wafer also includes a support layer and an etching layer. The etching layer is disposed on the upper layer of the support layer and is used to etch chip release grooves. The support layer is a support tooling.

[0006] The etched layer has several etched regions arranged in an array, each of which is adapted to the chip release slot.

[0007] Several chip release slots are provided for placing chips to be processed, and a slot interval is provided between two adjacent chip release slots.

[0008] Optionally, the surface area of ​​the chip release groove is adapted to the surface area of ​​the chip, and the depth of the chip release groove is greater than the thickness of the chip.

[0009] Optionally, the chip release slots are arranged in a ring array on the wafer.

[0010] Optionally, the chip release slots are arranged in a rectangular array on the wafer.

[0011] Optionally, the chip release slots arranged in a ring array have a plurality of chip release slots on the side of a concentric circle, and the vertical projection of the slot spacing between adjacent chip release slots forms the same sector shape.

[0012] Optionally, the slot spacing between the chip release slots arranged in a rectangular array is equidistant.

[0013] Optionally, the wafer has a thickness of 2 mm, and the etched layer has a thickness of 1 mm ± 50 μm.

[0014] Optionally, the wafer is a bare silicon wafer.

[0015] The beneficial effects of this application are as follows:

[0016] The improved chip release slot in this application is formed by laser etching on the etching layer of the wafer, which improves the stability of the chip release slot. The chip release slot can be arranged in a ring or matrix array, providing a variety of chip placement schemes. The chip placement slot formed by laser etching can be arbitrarily designed according to the shape of the chip, making the chip and its placement slot diverse, realizing the diversity and efficiency of tooling manufacturing. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the wafer structure of the release slot of the ring array chip;

[0018] Figure 2 This is a schematic diagram of the wafer structure of the release slot of a rectangular array chip;

[0019] Figure 3 This is a schematic diagram of the cross-sectional structure of a wafer;

[0020] In the diagram: 1. Wafer; 11. Support layer; 12. Etched layer; 2. Chip release groove; 3. Groove spacing. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This application provides a wafer sacrificial layer release tooling, including a wafer 1, for fabricating electronic components;

[0023] The wafer 1 further includes a support layer 11 and an etching layer 12. The etching layer 12 is disposed on the upper layer of the support layer 11. The etching layer 12 is used to etch the chip release groove 2. The support layer 11 is a support fixture. The wafer 1 is a bare silicon wafer.

[0024] It should be noted that the etched layer 12 and the support layer 11 are an integral wafer 1. The etched layer 12 is etched with a pre-designed etching scheme by laser etching technology. The depth and cross-sectional dimensions of the laser etching are matched with the chip to be processed, so that the chip can be placed inside the slot after laser etching.

[0025] In the laser etching operation, a photoresist layer is first coated on the outer surface of the insulating dielectric layer of the bare silicon wafer 1. The thickness of the photoresist layer is greater than or equal to the thickness of the support layer 11, approximately 1 mm. Through exposure and development, the shape of the chip release groove 2 is exposed. Then, the patterned opening portion is formed by laser etching of the insulating dielectric layer, and the opening portion is etched along the opening on the silicon substrate. Finally, the coated photoresist layer is removed, and the insulating dielectric layer on the chip surface is etched again in the same direction. At this time, the chip release groove 2 is etched.

[0026] The surface area of ​​the chip release groove 2 is adapted to the surface area of ​​the chip, and the depth of the chip release groove 2 is greater than the thickness of the chip. Being greater than the thickness of the chip can prevent the chip from falling out after being placed inside. Adapting to the surface area of ​​the chip can keep the chip stable during the processing.

[0027] The chip release slots 2 are arranged in a ring array on the wafer 1.

[0028] The chip release slots 2 arranged in a ring array have a plurality of chip release slots 2 on the side of a concentric circle, and the vertical projection of the slot spacing 3 between adjacent chip release slots 2 is the same sector shape.

[0029] The chip release slots 2 are arranged in a rectangular array on the wafer 1.

[0030] The slot spacing 3 between the chip release slots 2 arranged in a rectangular array is equidistant.

[0031] It is worth noting that the chip release slots 2 can be arranged in a ring array or a rectangular array. When arranged in a ring array, a ring of chip release slots 2 is set on the outer diameter of a concentric circle. At this time, the sector projection area formed between two adjacent chip release slots 2 is the same, and the distance between the chip release slots 2 set on the same diameter extension line of different concentric circles is the same.

[0032] The etched layer 12 has several etched regions arranged in an array, each of which is adapted to the chip release groove 2.

[0033] Several chip release slots 2 are provided for placing chips to be processed, and a slot interval 3 is provided between two adjacent chip release slots 2.

[0034] The wafer 1 has a thickness of 2 mm, and the etched layer 12 has a thickness of 1 mm ± 50 μm.

[0035] The above description is merely a few embodiments of this application and is not intended to limit this application in any way. Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any changes or modifications made by those skilled in the art without departing from the scope of the technical solution of this application using the disclosed technical content are equivalent to equivalent implementation cases and fall within the scope of the technical solution.

Claims

1. A wafer sacrificial layer release tooling, characterized in that, Includes wafers (1), used to fabricate electronic components; The wafer (1) further includes a support layer (11) and an etching layer (12). The etching layer (12) is disposed on the upper layer of the support layer (11). The etching layer (12) is used to etch the chip release groove (2). The support layer (11) is a support tooling. The etching layer (12) is provided with a plurality of etching regions arranged in an array, and each etching region is adapted to the chip release groove (2); Several chip release slots (2) are provided for placing chips to be processed, and a slot interval (3) is provided between two adjacent chip release slots (2).

2. The wafer sacrificial layer release fixture according to claim 1, characterized in that, The surface area of ​​the chip release groove (2) is adapted to the surface area of ​​the chip, and the depth of the chip release groove (2) is greater than the thickness of the chip.

3. The wafer sacrificial layer release fixture according to claim 1, characterized in that, The chip release slots (2) are arranged in a ring array on the wafer (1).

4. The wafer sacrificial layer release fixture according to claim 1, characterized in that, The chip release slots (2) are arranged in a rectangular array on the wafer (1).

5. The wafer sacrificial layer release fixture according to claim 3, characterized in that, The chip release slots (2) arranged in a ring array have a number of chip release slots (2) on the side of a concentric circle, and the vertical projection of the slot spacing (3) between adjacent chip release slots (2) is the same sector.

6. The wafer sacrificial layer release fixture according to claim 4, characterized in that, The slot spacing (3) between the chip release slots (2) arranged in a rectangular array is equidistant.

7. The wafer sacrificial layer release fixture according to claim 1, characterized in that, The wafer (1) has a thickness of 2 mm, and the etched layer (12) has a thickness of 1 mm ± 50 μm.

8. The wafer sacrificial layer release fixture according to claim 1, characterized in that, The wafer (1) is a bare silicon wafer.

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