Integrated circuit

Abstract

The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate and an interconnection structure. The interconnect structure is disposed on the semiconductor substrate. The interconnection structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and a first conductive feature. The composite dielectric layer includes an adhesive layer and a diamond layer disposed on the adhesive layer. The first conductive feature is embedded in the composite dielectric layer.

Description

Technical Field

[0001] This utility model relates to an integrated circuit. More specifically, this utility model relates to an integrated circuit with a heat dissipation structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have yielded generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (the number of interconnects in a chip area) has generally increased, while geometry (the smallest component or line that can be manufactured using a process) has decreased. This miniaturization process typically benefits production efficiency and reduces associated costs. Utility Model Content

[0003] An integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and a first conductive feature. The composite dielectric layer includes an adhesive layer and a diamond layer disposed on the adhesive layer. The first conductive feature is embedded in the composite dielectric layer.

[0004] An integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a dielectric layer, an adhesive layer, a heat dissipation layer, a first conductive pattern, a first via, a second conductive pattern, and a second via. The adhesive layer and the heat dissipation layer are alternately stacked on the dielectric layer. The first conductive pattern and the first via are embedded in the dielectric layer. The second conductive pattern and the second via are embedded in the adhesive layer and the heat dissipation layer. The first conductive pattern, the first via, the second conductive pattern, and the second via are electrically connected to each other. Attached Figure Description

[0005] The best understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0006] Figures 1A to 1Q This is a schematic cross-sectional view of the manufacturing process of an integrated circuit according to some embodiments of the present disclosure.

[0007] Figures 2A to 2CThis is a schematic cross-sectional view of an intermediate stage in the manufacturing process of an integrated circuit according to some alternative embodiments of this disclosure.

[0008] Figure 3 This is a schematic cross-sectional view of an integrated circuit according to some alternative embodiments of the present disclosure. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are illustrated below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0011] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods including intermediate verification of known good dies to improve yield and reduce costs.

[0012] Figures 1A to 1Q This is a schematic cross-sectional view of the manufacturing process of integrated circuit 10 according to some embodiments of this disclosure. (Refer to...) Figure 1A A semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 is made of the following materials: elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenide, or gallium indium phosphide. The semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0013] like Figure 1A As shown, a plurality of transistors 200 are formed on a semiconductor substrate 100. In some embodiments, each transistor 200 includes a source / drain region 202 and a gate 204. In some embodiments, each transistor 200 further includes a channel region (not shown) below the gate 204. In some embodiments, the channel region is also located between the source / drain regions 202 to serve as a path for electrons to travel when the transistor 200 is turned on.

[0014] In some embodiments, the semiconductor substrate 100 includes various doped regions, depending on circuit requirements (e.g., a p-type or n-type semiconductor substrate). In some embodiments, the doped regions are doped using p-type or n-type dopants. For example, p-type dopants (e.g., boron or BF2), n-type dopants (e.g., phosphorus or arsenic), and / or combinations thereof can be used to dope the doped regions. In some embodiments, these doped regions serve as the source / drain regions of the transistor 200. Depending on the type of dopant in the doped regions, the transistor 200 may be referred to as an n-type transistor or a p-type transistor.

[0015] In some embodiments, gate 204 comprises copper, titanium, tantalum, tungsten, aluminum, zirconium, hafnium, cobalt, titanium aluminum, tantalum aluminum, tungsten aluminum, zirconium aluminum, hafnium aluminum, titanium nitride, other suitable metallic materials, or combinations thereof. In some embodiments, gate 204 further comprises a material for fine-tuning the corresponding work function. For example, gate 204 may also comprise a p-type work function material (e.g., Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or combinations thereof) or an n-type work function material (e.g., Ag, TaCN, Mn, or combinations thereof).

[0016] like Figure 1AAs shown, the source / drain region 202 is embedded in the semiconductor substrate 100, and the gate 204 is located above the semiconductor substrate 100. However, this disclosure is not limited thereto. In some alternative embodiments, both the source / drain region 202 and the gate 204 are located above the semiconductor substrate 100. In some embodiments, the transistors 200 may be separated by shallow trench isolation (STI, not shown) between two adjacent transistors 200. In some embodiments, the transistors 200 are formed using a suitable front-end-of-line (FEOL) process.

[0017] Reference Figure 1B A signal transmission structure 300 is formed on a semiconductor substrate 100 and a transistor 200. In some embodiments, the signal transmission structure 300 includes a plurality of dielectric layers 310 and a plurality of conductive features 320. In some embodiments, the dielectric layers 310 are stacked on top of each other. For example, adjacent dielectric layers 310 are in physical contact with each other. In some embodiments, the material of the dielectric layers 310 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layers 310 may be formed of oxides or nitrides such as silicon oxide, silicon nitride, hafnium oxide, hafnium zirconium oxide, or similar materials. In some embodiments, different dielectric layers 310 are formed of the same material. However, this disclosure is not limited thereto. In some alternative embodiments, different dielectric layers 310 may be formed of different materials. The dielectric layer 310 can be formed by suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or similar techniques. In some embodiments, the number of dielectric layers 310 is four or more.

[0018] In some embodiments, the conductive feature 320 includes a plurality of conductive structures 322 and a plurality of conductive patterns 324. For example... Figure 1BAs shown, conductive feature 320 is embedded in dielectric layer 310. That is, conductive structure 322 and conductive pattern 324 are embedded in dielectric layer 310. For example, dielectric layer 310 laterally encapsulates conductive structure 322 and conductive pattern 324. In some embodiments, conductive pattern 324 extends horizontally. Meanwhile, conductive structure 322 extends vertically to connect conductive patterns 324 located at different horizontal heights. In other words, conductive patterns 324 are electrically connected to each other through conductive structure 322. In some embodiments, bottom conductive structure 322 is connected to transistor 200. For example, bottom conductive structure 322 is connected to source / drain region 202 and gate 204 of transistor 200. In other words, bottom conductive structure 322 establishes an electrical connection between transistor 200 and conductive pattern 324. That is, conductive feature 320 is electrically connected to transistor 200. In some embodiments, conductive structure 322 may be referred to as a "via". In some alternative embodiments, the bottom conductive structure 322 may be referred to as the “contact structure” of transistor 200.

[0019] In some embodiments, the materials of the conductive pattern 324 and the conductive structure 322 include aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive pattern 324 and the conductive structure 322 can be formed by electroplating, deposition, and / or photolithography and etching. In some embodiments, the conductive pattern 324 and the underlying conductive structure 322 are formed separately. However, this disclosure is not limited thereto. In some alternative embodiments, the conductive pattern 324 and the underlying conductive structure 322 can be formed simultaneously. Figure 1B As shown, the conductive structure 322 and the underlying conductive pattern 324 are embedded in the same dielectric layer 310. In other words, the top surface of each conductive structure 322 is coplanar with the top surface of the corresponding dielectric layer 310. Meanwhile, the top surface of each conductive pattern 324 is located at a lower horizontal height than the top surface of the corresponding dielectric layer 310. That is, the top surface of the conductive pattern 324 is covered by the dielectric layer 310.

[0020] Reference Figure 1B as well as Figure 1C The top dielectric layer 310 is planarized until the top conductive pattern 324 is exposed. In other words, after the planarization process, the top surface T of the top conductive pattern 324 is exposed. 324 With the top surface T of the top dielectric layer 310 310 Coplanar. In some embodiments, the planarization process makes the top surface T of the topmost conductive pattern 324 coplanar. 324 Surface roughness and the top surface T of the top dielectric layer 310 310The surface roughness is reduced to less than 1 nm. In some embodiments, the planarization process includes mechanical grinding, chemical mechanical polishing (CMP), etc.

[0021] Reference Figure 1D A carrier substrate C is provided. In some embodiments, the carrier substrate C is made of the following materials: elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenide, or gallium indium phosphide. The carrier substrate C may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, the material of the carrier substrate C includes silicon, silicon nitride, sapphire, SrTiO3, MgO, etc.

[0022] In some embodiments, a buffer layer BUF is formed on a carrier substrate C. In some embodiments, the material of the buffer layer BUF includes iridium or the like. The buffer layer BUF can be formed on the carrier substrate C by electron beam evaporation, magnetron sputtering, metal-organic CVD, atomic layer deposition (ALD), pulsed laser deposition, or the like. In some embodiments, the process temperature for forming the buffer layer BUF is 850°C or higher.

[0023] After forming a buffer layer BUF on a carrier plate C, a sacrificial diamond material layer SDM is grown on the buffer layer BUF and the carrier plate C. In some embodiments, the sacrificial diamond material layer SDM is formed on the buffer layer BUF and the carrier plate C via CVD, microwave plasma chemical vapor deposition (MPCVD), or the like. In some embodiments, the process temperature for growing the sacrificial diamond material layer SDM is 700°C or higher. In some embodiments, the sacrificial diamond material layer SDM can be considered as heteroepitaxially grown on the buffer layer BUF and the carrier plate C. In some embodiments, the buffer layer BUF can effectively improve the quality of the sacrificial diamond material layer SDM formed thereon. For example, compared to the case without a buffer layer, carbon atoms can enter the surface of the buffer layer BUF at a higher molar fraction (e.g., 10%) during the growth of the sacrificial diamond material layer SDM. Therefore, more carbon source can be provided to form a high density of diamond nucleation sites on the surface of the buffer layer BUF, thereby significantly improving the epitaxial growth of the sacrificial diamond material layer SDM.

[0024] Reference Figure 1D as well as Figure 1E The sacrificial diamond material layer SDM is patterned to form a sacrificial diamond layer SD with microneedles MN thereon. In some embodiments, the patterning process includes photolithography and etching processes. The etching process includes dry etching processes. For example, the sacrificial diamond material layer SDM can be patterned by reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, neutral beam etching (NBE), etc. In some embodiments, oxygen can be used as the etching gas during the dry etching process. In some embodiments, the microneedles MN are arranged in an array. Although Figure 1E The illustration shows each microneedle MN having upright sidewalls, but this disclosure is not limited thereto. In some alternative embodiments, each microneedle MN may have sloping sidewalls and a sharp tip.

[0025] Reference Figure 1FA diamond layer 414a is grown on microneedles MN. For example, the microneedles MN can serve as a seed layer for the epitaxial growth of the diamond layer 414a. In some embodiments, the diamond layer 414a is grown on the microneedles MN via CVD, MPCVD, or the like. Similar to sacrificial diamond material layer SDM, the process temperature for growing the diamond layer 414a is 700°C or higher. Figure 1F As shown, the microneedle MN is sandwiched between the sacrificial diamond layer SD and the diamond layer 414a.

[0026] Reference Figure 1G An adhesive layer 412a is formed on the diamond layer 414a. In some embodiments, the material of the adhesive layer 412a includes a metal oxide or a metal nitride. For example, the material of the adhesive layer 412a includes aluminum oxide or aluminum nitride. However, this disclosure is not limited thereto. In some alternative embodiments, other materials with adhesive properties may also be used as the material of the adhesive layer 412a. In some embodiments, the adhesive layer 412a is formed by a suitable manufacturing technique such as spin coating, CVD, PECVD, etc. In some embodiments, after the adhesive layer 412a is formed on the diamond layer 414a, the adhesive layer 412a is subjected to a planarization process to reduce its surface roughness. In some embodiments, the thickness of the adhesive layer 412a is 30 nm or less. For example, the thickness of the adhesive layer 412a can be in the range of about 1 nm to about 30 nm. In some embodiments, since both the adhesive layer 412a and the diamond layer 414a are made of dielectric material, the adhesive layer 412a and the diamond layer 414a can be collectively referred to as the composite dielectric layer 410a. That is, the composite dielectric layer 410a is grown on the carrier C, the buffer layer BUF, the sacrificial diamond layer SD, and the microneedle MN.

[0027] Reference Figure 1H ,Will Figure 1C The structure shown is Figure 1G The structural combinations shown. For example, [the following is a list of structural combinations]. Figure 1G The structure shown is flipped upside down and placed on Figure 1C The structure shown is as follows. That is, the diamond layer 414a, microneedles MN, sacrificial diamond layer SD, buffer layer BUF, and carrier plate C are attached to the signal transmission structure 300 via the adhesive layer 412a. For example... Figure 1H As shown, the adhesive layer 412a and the top surface T of the top dielectric layer 310 310 And the top surface T of the topmost conductive pattern 324 324 Physical contact. As described above, the top surface T of the topmost conductive pattern 324 324 The surface roughness is similar to the top surface T of the top dielectric layer 310. 310The surface roughness is less than 1 nm. Therefore, the adhesive layer 412a is attached to a substantially flat surface. In some embodiments, the material of the dielectric layer 310 is different from the material of the composite dielectric layer 410a. That is, the material of the dielectric layer 310 is different from the material of the adhesive layer 412a and the material of the diamond layer 414a. Therefore, there is an interface between the composite dielectric layer 410a and the topmost dielectric layer 310. That is, there is an interface between the adhesive layer 412a and the topmost dielectric layer 310.

[0028] Reference Figure 1H as well as Figure 1I Stress is applied to the microneedle MN, the sacrificial diamond layer SD, the buffer layer BUF, and the carrier plate C. The applied stress causes the microneedle MN to fracture, subsequently splitting it into a first part MN1 and a second part MN2. For example... Figure 1I As shown, the first portion MN1 of the microneedle MN is attached to the sacrificial diamond layer SD, while the second portion MN2 of the microneedle MN is attached to the diamond layer 414a. In some embodiments, the breakage of the microneedle MN allows the composite dielectric layer 410a to separate from the sacrificial diamond layer SD, the buffer layer BUF, and the carrier plate C. In other words, the first portion MN1 of the microneedle MN, the sacrificial diamond layer SD, the buffer layer BUF, and the carrier plate C separate from the second portion MN2 of the microneedle MN, the diamond layer 414a, and the adhesive layer 412a.

[0029] Reference Figure 1I as well as Figure 1J The microneedles MN remaining on the diamond layer 414a are removed. That is, the second portion MN2 of the microneedles MN is removed. In some embodiments, the second portion MN2 of the microneedles MN is removed by etching, planarization, or a combination thereof. After the second portion MN2 of the microneedles MN is removed, the diamond layer 414a has a substantially flat top surface.

[0030] Through execution Figures 1D to 1JThe steps shown allow for the easy growth of the composite dielectric layer 410a and its transfer onto the signal transmission structure 300. In some embodiments, the signal transmission structure 300 and the composite dielectric layer 410a are considered to be formed during a back-end-of-line (BEOL) process. Traditionally, the thermal budget (process temperature window) of the BEOL process is low. However, as mentioned above, the process temperature for forming the composite dielectric layer 410a is high (700°C or higher for the diamond layer 414a and 850°C or higher for the buffer layer BUF). Therefore, within the thermal budget constraints of the BEOL process, it is difficult to form the diamond layer 414a by simply depositing diamond material. That is, a high-temperature process is required to grow the diamond layer 414a; however, the high growth temperature of the diamond layer 414a exceeds the temperature limits of the BEOL process and is incompatible with it. Instead, as Figures 1D to 1J As shown, by first growing a diamond layer 414a on a separate carrier C and then transferring the diamond layer 414a onto the signal transmission structure 300, the diamond layer 414a can be integrated into the subsequently formed integrated circuit 10 while being compatible with the thermal budget of BEOL.

[0031] It is worth noting that, Figures 1D to 1J The growth and transfer of the composite dielectric layer 410a shown are merely illustrative and this disclosure is not limited thereto. In some alternative embodiments, the composite dielectric layer 410a can be grown and transferred onto the signal transmission structure 300 using other processes. For example, the following will be combined with Figures 2A to 2C Another process is described for growing and transferring a composite dielectric layer 410a onto a signal transmission structure 300.

[0032] Figures 2A to 2C This is a schematic cross-sectional view of an intermediate stage in the manufacturing process of an integrated circuit 10 according to some alternative embodiments of this disclosure. (Refer to...) Figure 2A Provide carrier board C. Figure 2A Carrier plate C in Figure 1D The carrier plate C is similar to that in the previous example, so its detailed description is omitted here. In some embodiments, a buffer layer BUF is formed on the carrier plate C. In some embodiments, Figure 2A The buffer layer BUF in Figure 1D The buffer layer BUF in the middle is similar, so its detailed description is omitted here.

[0033] After forming a buffer layer BUF on a carrier plate C, a diamond layer 414a is grown on the buffer layer BUF and the carrier plate C. In some embodiments, the diamond layer 414a is formed on the buffer layer BUF and the carrier plate C by CVD, MPCVD, or the like. In some embodiments, the process temperature for growing the diamond layer 414a is 700°C or higher. In some embodiments, the diamond layer 414a can be considered as heteroepitaxial growth on the buffer layer BUF and the carrier plate C. In some embodiments, the buffer layer BUF can effectively improve the quality of the diamond layer 414a formed thereon. For example, compared to the case without a buffer layer, during the growth of the diamond layer 414a, carbon atoms can enter the surface of the buffer layer BUF at a higher molar fraction (e.g., 10%). Therefore, more carbon source can be provided to form a high density of diamond nucleation sites on the surface of the buffer layer BUF, thereby significantly improving the epitaxial growth of the diamond layer 414a.

[0034] Reference Figure 2B An adhesion layer 412a is formed on the diamond layer 414a. In some embodiments, Figure 2B The adhesive layer 412a in the middle and Figure 1G Similar to the adhesive layer 412a, its detailed description is omitted here. In some embodiments, after the adhesive layer 412a is formed on the diamond layer 414a, the adhesive layer 412a is subjected to a planarization process to reduce its surface roughness. In some embodiments, since both the adhesive layer 412a and the diamond layer 414a are made of dielectric material, the adhesive layer 412a and the diamond layer 414a can be collectively referred to as the composite dielectric layer 410a. That is, the composite dielectric layer 410a is grown on the carrier C and the buffer layer BUF.

[0035] Reference Figure 2C ,Will Figure 1C The structure shown is Figure 2B The structural combinations shown. For example, [the following is a list of structural combinations]. Figure 2B The structure shown is flipped upside down and placed on Figure 1C The structure shown is such that the diamond layer 414a, the buffer layer BUF, and the carrier plate C are attached to the signal transmission structure 300 via the adhesive layer 412a. Figure 2C As shown, the adhesive layer 412a and the top surface T of the top dielectric layer 310 310 And the top surface T of the topmost conductive pattern 324 324 Physical contact. As described above, the top surface T of the topmost conductive pattern 324 324 The surface roughness is similar to the top surface T of the top dielectric layer 310. 310The surface roughness is less than 1 nm. Therefore, the adhesive layer 412a is attached to a substantially flat surface. In some embodiments, the material of the dielectric layer 310 is different from the material of the composite dielectric layer 410a. That is, the material of the dielectric layer 310 is different from the material of the adhesive layer 412a and the material of the diamond layer 414a. Therefore, there is an interface between the composite dielectric layer 410a and the topmost dielectric layer 310. That is, there is an interface between the adhesive layer 412a and the topmost dielectric layer 310.

[0036] After attaching the diamond layer 414a to the signal transmission structure 300 via the adhesive layer 312a, the buffer layer BUF and the carrier plate C are removed to obtain the desired result. Figure 1J The structure is shown. In some embodiments, the buffer layer BUF and the carrier plate C are removed by etching, planarization, or a combination thereof. After removing the buffer layer BUF and the carrier plate C, the diamond layer 414a has a substantially flat top surface.

[0037] Through execution Figures 2A to 2C The steps shown allow for the easy growth of the composite dielectric layer 410a and its transfer onto the signal transmission structure 300. In some embodiments, the signal transmission structure 300 and the composite dielectric layer 410a are considered to be formed during a BEOL process. Traditionally, the thermal budget (i.e., process temperature window) of the BEOL process is low. However, as mentioned above, the process temperature for forming the composite dielectric layer 410a is high (700°C or higher for the diamond layer 414a and 850°C or higher for the buffer layer BUF). Therefore, within the thermal budget constraints of the BEOL process, it is difficult to form the diamond layer 414a by simply depositing diamond material. That is, a high-temperature process is required to grow the diamond layer 414a; however, the high growth temperature of the diamond layer 414a exceeds the temperature limits of the BEOL process and is incompatible with it. Instead, as Figures 2A to 2C As shown, by first growing a diamond layer 414a on a separate carrier C and then transferring the diamond layer 414a onto the signal transmission structure 300, the diamond layer 414a can be integrated into the subsequently formed integrated circuit 10 while being compatible with the thermal budget of BEOL.

[0038] Reference Figure 1J as well as Figure 1KThe adhesive layer 412a and the diamond layer 414a are patterned to form a plurality of openings OP1 in the adhesive layer 412a and the diamond layer 414a. That is, the openings OP1 are formed in the composite dielectric layer 410a. In some embodiments, the openings OP1 penetrate the composite dielectric layer 410a. For example, the openings OP1 penetrate the adhesive layer 412a and the diamond layer 414a to partially expose the underlying conductive pattern 324. That is, the openings OP1 partially expose the topmost conductive pattern 324. In some embodiments, the patterning process of the adhesive layer 412a and the diamond layer 414a includes a photolithography process and an etching process. The etching process includes a dry etching process. For example, the adhesive layer 412a and the diamond layer 414a can be patterned by RIE, ICP etching, ECR etching, NBE, etc. In some embodiments, oxygen can be used as the etching gas during the dry etching process.

[0039] Reference Figure 1L Conductive material (not shown) is deposited in the opening OP1 to form a plurality of vias 422. For example, the conductive material is conformally formed on the composite dielectric layer 410a. In some embodiments, the conductive material also fills the opening OP1. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, the conductive material is deposited into the opening OP1 by means of PVD, ion beam deposition (IBD), CVD, ALD, molecular beam epitaxy (MBE), electro-chemical plating (ECP), electroless deposition (ELD), etc. Then, the conductive material is planarized until the diamond layer 414a is exposed to form vias 422 in the opening OP1. In some embodiments, the planarization process includes mechanical polishing, CMP, etc. After the planarization process, the top surface T of the via 422 is planarized. 422 With the top surface T of diamond layer 414a 414a Coplanar. In other words, the composite dielectric layer 410a laterally encloses the via 422 and exposes the top surface T of the via 422. 422 In some embodiments, the planarization process flattens the top surface T of the via 422. 422 Surface roughness and the top surface T of diamond layer 414a 414a The surface roughness is reduced to less than 1 nm.

[0040] Reference Figure 1MA composite dielectric layer 410b is formed on the composite dielectric layer 410a and the via 422. In some embodiments, the composite dielectric layer 410b includes an adhesive layer 412b and a diamond layer 414b disposed on the adhesive layer 412b. Figure 1M The adhesive layer 412b and the diamond layer 414b in the middle are respectively with Figure 1G The adhesive layer 412a and diamond layer 414a are similar, so their detailed description is omitted here. In some embodiments, they can be achieved through similar means. Figures 1D to 1J The steps shown or Figures 2A to 2C The steps shown are used to grow and transfer the composite dielectric layer 410b onto the composite dielectric layer 410a and the via 422.

[0041] Reference Figure 1M as well as Figure 1N The adhesive layer 412b and the diamond layer 414b are patterned to form a plurality of openings OP2 in the adhesive layer 412b and the diamond layer 414b. That is, the openings OP2 are formed in the composite dielectric layer 410b. In some embodiments, the openings OP2 penetrate the composite dielectric layer 410b. For example, the openings OP2 penetrate the adhesive layer 412b and the diamond layer 414b to expose the underlying via 422. In some embodiments, the openings OP2 also partially expose the underlying composite dielectric layer 410a. In some embodiments, the patterning process of the adhesive layer 412b and the diamond layer 414b includes a photolithography process and an etching process. The etching process includes a dry etching process. For example, the adhesive layer 412b and the diamond layer 414b can be patterned by RIE, ICP etching, ECR etching, NBE, etc. In some embodiments, oxygen can be used as the etching gas during the dry etching process.

[0042] Reference Figure 10 Conductive material (not shown) is deposited in the opening OP2 to form multiple conductive patterns 424. For example, the conductive material is conformally formed on the composite dielectric layer 410b. In some embodiments, the conductive material also fills the opening OP2. In some embodiments, the conductive material includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. In some embodiments, the conductive material is deposited into the opening OP2 via PVD, IBD, CVD, ALD, MBE, ECP, ELD, etc. Subsequently, the conductive material is planarized until the diamond layer 414b is exposed to form conductive patterns 424 in the opening OP2. In some embodiments, the planarization process includes mechanical polishing, CMP, etc. After the planarization process, the top surface T of the conductive pattern 424 is... 424 Top surface T of diamond layer 414b 414b Coplanar. In other words, the composite dielectric layer 410b laterally encapsulates the conductive pattern 424 and exposes the top surface T of the conductive pattern 424. 424In some embodiments, the planarization process flattens the top surface T of the conductive pattern 424. 424 Surface roughness and the top surface T of diamond layer 414b 414b The surface roughness is reduced to less than 1 nm.

[0043] like Figure 10 As shown, each conductive pattern 424 passes through a composite dielectric layer (i.e., composite dielectric layer 410b), while each via 422 passes through another composite dielectric layer (i.e., composite dielectric layer 410a). For example, each conductive pattern 424 passes through an adhesive layer (i.e., adhesive layer 412b) and a diamond layer (i.e., diamond layer 414b), while each via 422 passes through another adhesive layer (i.e., adhesive layer 412a) and another diamond layer (i.e., diamond layer 414a).

[0044] Reference Figure 1P ,Will Figures 1J to 1O The steps shown are repeated multiple times to form a heat dissipation structure 400 on the signal transmission structure 300. In some embodiments, the heat dissipation structure 400 includes a plurality of composite dielectric layers 410a, 410b, 410c, 410d, 410e and a plurality of conductive features 420. In some embodiments, the composite dielectric layers 410a, 410b, 410c, 410d, 410e are stacked on top of each other. For example, adjacent composite dielectric layers 410a, 410b, 410c, 410d, 410e are in physical contact with each other. In some embodiments, composite dielectric layer 410c includes an adhesive layer 412c and a diamond layer 414c disposed on the adhesive layer 412c, composite dielectric layer 410d includes an adhesive layer 412d and a diamond layer 414d disposed on the adhesive layer 412d, and composite dielectric layer 410e includes an adhesive layer 412e and a diamond layer 414e disposed on the adhesive layer 412e. Figure 1P The adhesive layers 412c, 412d, 412e and the diamond layers 414c, 414d, 414e are respectively with Figure 1G The adhesive layer 412a and the diamond layer 414a are similar, so a detailed description of them is omitted here. Figure 1P As shown, adhesive layers 412a, 412b, 412c, 412d, 412e and diamond layers 414a, 414b, 414c, 414d, 414e are alternately stacked on top of dielectric layer 310.

[0045] In some embodiments, the conductive feature 420 includes a via 422 and a conductive pattern 424. For example... Figure 1P As shown, conductive feature 420 is embedded in composite dielectric layers 410a, 410b, 410c, 410d, and 410e. For example... Figure 1PAs shown, vias 422 are embedded in composite dielectric layers 410a, 410c, and 410e. On the other hand, conductive patterns 424 are embedded in composite dielectric layers 410b and 410d. For example, vias 422 are embedded in adhesive layers 412a, 412c, and 412e and diamond layers 414a, 414c, and 414e, while conductive patterns 424 are embedded in adhesive layers 412b and 412d and diamond layers 414b and 414d. In some embodiments, conductive patterns 424 extend horizontally. Simultaneously, vias 422 extend vertically to connect conductive patterns 424 located at different horizontal heights. In other words, conductive patterns 424 are electrically connected to each other through vias 422. In some embodiments, vias 422 and conductive patterns 424 penetrate different composite dielectric layers 410a, 410b, 410c, 410d, and 410e. For example, via 422 penetrates the corresponding composite dielectric layers 410a, 410c, and 410e, while conductive pattern 424 penetrates the corresponding composite dielectric layers 410b and 410d. Figure 1P As shown, the top surface of each diamond layer 414a, 414b, 414c, 414d, 414e is coplanar with the top surface of the corresponding conductive feature 420. Meanwhile, the top surface of each adhesive layer 412a, 412b, 412c, 412d, 412e is located at a lower horizontal height than the top surface of the corresponding conductive feature 420.

[0046] In some embodiments, since the diamond layers 414a, 414b, 414c, 414d, and 414e are made of diamond and grown at a process temperature of 700°C or higher, the thermal conductivity of the diamond layers 414a, 414b, 414c, 414d, and 414e is high. For example, the thermal conductivity of the diamond layers 414a, 414b, 414c, 414d, and 414e is 600 W / (m·K) or higher. Accordingly, the heat generated during the subsequent operation of the integrated circuit 10 can be sufficiently dissipated by the diamond layers 414a, 414b, 414c, 414d, and 414e. Therefore, in some embodiments, the diamond layers 414a, 414b, 414c, 414d, and 414e can be referred to as heat dissipation layers. By introducing these heat dissipation layers (i.e., diamond layers 414a, 414b, 414c, 414d, 414e), the performance and lifespan of the subsequently formed integrated circuit 10 can be significantly improved.

[0047] In some embodiments, the heat dissipation structure 400 is in physical contact with the signal transmission structure 300. For example, the topmost dielectric layer 310 of the signal transmission structure 300 is in physical contact with the bottommost adhesive layer (i.e., adhesive layer 412a) of the heat dissipation structure 400. Simultaneously, the bottommost conductive feature 420 (i.e., the bottommost via 422) of the heat dissipation structure 400 is in physical contact with the topmost conductive feature 320 (i.e., the topmost conductive pattern 324) of the signal transmission structure 300. In other words, the conductive feature 420 of the heat dissipation structure 400 is electrically connected to the conductive feature 320 of the signal transmission structure 300. For example, the conductive structure 322, the conductive pattern 324, the via 422, and the conductive pattern 424 are electrically connected to each other. In some embodiments, the conductive feature 420 is electrically connected to the transistor 200 through the conductive feature 320.

[0048] Since the conductive feature 420 of the heat dissipation structure 400 is electrically connected to the conductive feature 320 of the signal transmission structure 300, the heat dissipation structure 400 also has the function of signal transmission in addition to heat dissipation.

[0049] In some embodiments, the signal transmission structure 300 and the heat dissipation structure 400 are collectively referred to as the interconnect structure INT. That is, the interconnect structure INT is disposed on the semiconductor substrate 100. For example... Figure 1P As shown, transistor 200 is partially embedded in the interconnect structure INT. For example, the gate 204 of transistor 200 is embedded in the signal transmission structure 300 of the interconnect structure INT.

[0050] It is worth noting that, Figure 1P The number of composite dielectric layers 410a, 410b, 410c, 410d, 410e, vias 422, and conductive patterns 424 shown are for illustrative purposes only, and this disclosure is not limited thereto. In some alternative embodiments, depending on the circuit design, fewer or more layers of composite dielectric layers 410a, 410b, 410c, 410d, 410e, vias 422, and conductive patterns 424 may be formed.

[0051] Reference Figure 1Q Multiple under-bump metallurgy (UBM) patterns 500 are formed on the heat dissipation structure 400. For example, the UBM patterns 500 are formed on the composite dielectric layer 410e and the topmost via 422. In some embodiments, the UBM patterns 500 are in physical contact with the topmost via 422 to achieve electrical connection with the interconnect structure INT. In some embodiments, the UBM patterns 500 are formed through sputtering, PVD, electroplating, or other processes. In some embodiments, the UBM patterns 500 are made of aluminum, titanium, copper, tungsten, and / or their alloys.

[0052] After the UBM pattern 500 is formed on the heat dissipation structure 400, a plurality of conductive terminals 600 are disposed on the UBM pattern 500. In some embodiments, the conductive terminals 600 are attached to the UBM pattern 500 via flux. In some embodiments, the conductive terminals 600 are, for example, solder balls, ball grid array (BGA) balls, or controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 600 are made of a low resistivity conductive material, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof.

[0053] Subsequently, the heat dissipation structure 400, signal transmission structure 300, and semiconductor substrate 100 are subjected to a monomerization process to obtain multiple integrated circuits 10. In some embodiments, the monomerization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monomerization process includes laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof.

[0054] Figure 3 This is a schematic cross-sectional view of an integrated circuit 20 according to some alternative embodiments of this disclosure. Please refer to... Figure 3 , Figure 3 Integrated circuit 20 and Figure 1Q The integrated circuit 10 is similar to that in the example, and therefore similar components are represented by the same reference numerals, and their detailed descriptions are omitted here. Figure 3 Integrated circuit 20 and Figure 1Q The difference in integrated circuit 10 is that, Figure 3 The heat dissipation structure 400 in the integrated circuit 20 includes only one composite dielectric layer 410. Furthermore, the conductive feature 420 in the heat dissipation structure 400 includes only vias 422. In some embodiments, the composite dielectric layer 410 includes an adhesive layer 412 and a diamond layer 414 disposed on the adhesive layer 412. Figure 3 The adhesive layer 412 and the diamond layer 414 in the middle are respectively with Figure 1G The adhesive layer 412a and diamond layer 414a are similar, so their detailed description is omitted here. Meanwhile, Figure 3 The through hole 422 and Figure 1L Similar to the via 422 in the example, its detailed description is omitted here. In some embodiments, it is possible to pass through a similar... Figures 1D to 1J The steps shown or Figures 2A to 2CThe steps shown transfer the composite dielectric layer 410 onto the signal transmission structure 300. Therefore, by first growing the diamond layer 414 on a separate substrate and then transferring it onto the signal transmission structure 300, the diamond layer 414 can be integrated into the integrated circuit 20 while remaining compatible with the thermal budget of BEOL. Furthermore, by introducing a heat dissipation layer (i.e., the diamond layer 414), the performance and lifespan of the integrated circuit 20 can be significantly improved.

[0055] According to some embodiments of this disclosure, an integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and a first conductive feature. The composite dielectric layer includes an adhesive layer and a diamond layer disposed on the adhesive layer. The first conductive feature is embedded in the composite dielectric layer.

[0056] According to some embodiments disclosed herein, the signal transmission structure includes a dielectric layer and a second conductive feature. The material of the dielectric layer is different from the material of the composite dielectric layer, and the second conductive feature is embedded in the dielectric layer.

[0057] According to some embodiments of this disclosure, the integrated circuit further includes a transistor disposed on the semiconductor substrate, and the first conductive feature is electrically connected to the transistor via the second conductive feature.

[0058] According to some embodiments disclosed herein, the bottommost first conductive feature is in physical contact with the topmost second conductive feature.

[0059] According to some embodiments disclosed herein, the topmost dielectric layer is in physical contact with the bottommost adhesive layer.

[0060] According to some embodiments disclosed herein, the number of dielectric layers is four or more.

[0061] According to some embodiments of this disclosure, the top surface of each diamond layer is coplanar with the top surface of the corresponding first conductive feature.

[0062] According to some embodiments of this disclosure, the first conductive feature includes a via, and the via extends vertically through the composite dielectric layer.

[0063] According to some alternative embodiments of this disclosure, an integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a dielectric layer, an adhesive layer, a heat dissipation layer, a first conductive pattern, a first via, a second conductive pattern, and a second via. The adhesive layer and the heat dissipation layer are alternately stacked on the dielectric layer. The first conductive pattern and the first via are embedded in the dielectric layer. The second conductive pattern and the second via are embedded in the adhesive layer and the heat dissipation layer. The first conductive pattern, the first via, the second conductive pattern, and the second via are electrically connected to each other.

[0064] According to some alternative embodiments disclosed herein, the number of dielectric layers is four or more.

[0065] According to some alternative embodiments disclosed herein, the material of the dielectric layer is different from the material of the adhesive layer and the material of the heat dissipation layer.

[0066] According to some alternative embodiments disclosed herein, the material of the heat dissipation layer includes diamond.

[0067] According to some alternative embodiments of this disclosure, each of the second conductive patterns passes through one of the adhesive layers and one of the heat dissipation layers, and each of the second vias passes through another of the adhesive layers and another of the heat dissipation layers.

[0068] According to some embodiments of this disclosure, a method for manufacturing an integrated circuit includes at least the following steps: Providing a semiconductor substrate. Forming an interconnect structure on the semiconductor substrate. The interconnect structure is formed through at least the following steps: Forming a signal transmission structure on the semiconductor substrate. Forming a heat dissipation structure on the signal transmission structure. The heat dissipation structure is formed through at least the following steps: Growing a composite dielectric layer on a carrier substrate. The composite dielectric layer includes a diamond layer and an adhesion layer disposed on the diamond layer. Transferring the composite dielectric layer onto the signal transmission structure. Forming a first conductive feature in the composite dielectric layer.

[0069] According to some embodiments of this disclosure, growing the composite dielectric layer and transferring the composite dielectric layer includes at least the following steps: Growing a sacrificial diamond material layer on the substrate. Patterning the sacrificial diamond material layer to form a sacrificial diamond layer with microneedles thereon. Growing the diamond layer on the microneedles. Forming the adhesive layer on the diamond layer. Attaching the diamond layer, the microneedles, the sacrificial diamond layer, and the substrate to the signal transmission structure through the adhesive layer. Breaking off the microneedles to separate portions of the microneedles, the sacrificial diamond layer, and the substrate from the diamond layer. Removing any remaining microneedles from the diamond layer.

[0070] According to some embodiments of this disclosure, growing the composite dielectric layer and transferring the composite dielectric layer includes at least the following steps: Growing the diamond layer on the carrier substrate. Forming the adhesive layer on the diamond layer. Attaching the diamond layer and the carrier substrate to the signal transmission structure via the adhesive layer. Removing the carrier substrate.

[0071] According to some embodiments of this disclosure, forming the first conductive feature in the composite dielectric layer includes at least the following steps: patterning the diamond layer and the adhesive layer to form openings in the diamond layer and the adhesive layer; and depositing a conductive material in the openings to form the first conductive feature.

[0072] According to some embodiments of this disclosure, the top surface of the first conductive feature is formed to be coplanar with the top surface of the diamond layer.

[0073] According to some embodiments of this disclosure, forming the signal transmission structure includes at least the following steps: forming a dielectric layer on the semiconductor substrate; forming a second conductive feature in the dielectric layer, wherein the first conductive feature is electrically connected to the second conductive feature.

[0074] According to some embodiments disclosed herein, the number of dielectric layers is four or more.

[0075] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, characterized in that, include: Semiconductor substrate; as well as An interconnect structure, disposed on the semiconductor substrate, includes: Signal transmission structure; and A heat dissipation structure, disposed on the signal transmission structure, includes: The composite dielectric layer includes an adhesive layer and a diamond layer disposed on the adhesive layer; and The first conductive feature is embedded in the composite dielectric layer.

2. The integrated circuit according to claim 1, characterized in that, The signal transmission structure includes: Dielectric layer; and The second conductive feature is embedded in the dielectric layer.

3. The integrated circuit according to claim 2, characterized in that, It also includes a transistor disposed on the semiconductor substrate, wherein the first conductive feature is electrically connected to the transistor through the second conductive feature.

4. The integrated circuit according to claim 2, characterized in that, The bottom first conductive feature is in physical contact with the top second conductive feature.

5. The integrated circuit according to claim 2, characterized in that, The top dielectric layer and the bottom adhesive layer are in physical contact.

6. The integrated circuit according to claim 1, characterized in that, The top surface of each diamond layer is coplanar with the top surface of the corresponding first conductive feature.

7. The integrated circuit according to claim 1, characterized in that, The first conductive feature includes: A via extends vertically through the composite dielectric layer.

8. An integrated circuit, characterized in that, include: Semiconductor substrate; as well as Interconnect structures, disposed on the semiconductor substrate, include: Dielectric layer; An adhesive layer and a heat dissipation layer are alternately stacked on the dielectric layer; A first conductive pattern and a first via are embedded in the dielectric layer; and The second conductive pattern and the second through hole are embedded in the adhesive layer and the heat dissipation layer, wherein the first conductive pattern, the first through hole, the second conductive pattern and the second through hole are electrically connected to each other.

9. The integrated circuit according to claim 8, characterized in that, The number of dielectric layers is four or more.

10. The integrated circuit according to claim 8, characterized in that, Each of the second conductive patterns passes through one of the adhesive layers and one of the heat dissipation layers, and each of the second vias passes through another of the adhesive layers and another of the heat dissipation layers.

Images