Intelligent power module

Abstract

According to the intelligent power module provided by the utility model, the low-voltage pins are all arranged on the first side of the packaging body, and the high-voltage pins and the power pins are all arranged on the second side of the packaging body, so that the isolation of the high-voltage pins and the low-voltage pins is realized, the interference of the high-voltage pins on the low-voltage pins is avoided, and meanwhile, the reliability of the power module is improved. By arranging the independent direct-current bus cathode pin, the direct-current bus cathode pin can be externally connected with a current induction resistor and a related protection circuit thereof, so that overcurrent protection can be respectively and independently performed on the three-phase low side.

Description

Technical Field

[0001] This utility model relates to the field of electronic device technology, and in particular to an intelligent power module. Background Technology

[0002] Intelligent power modules are advanced power switching devices that are increasingly widely used in the field of power electronics. Based on traditional power modules, intelligent power modules integrate logic, control, detection, and protection circuits, featuring high integration, high system reliability, simplified peripheral application circuits, and ease of use.

[0003] Because intelligent power modules integrate power devices and drive circuits together, they require high-voltage power supplies and low-voltage logic power supplies and logic signals when used. However, low-voltage power supplies are easily interfered with by high-voltage power supplies, causing problems such as high-voltage breakdown and false triggering. Utility Model Content

[0004] The main purpose of this invention is to propose an intelligent power module that aims to solve the problem that low-voltage power supplies are easily interfered with by high-voltage power supplies in the prior art.

[0005] To achieve the above objectives, this utility model provides an intelligent power module, characterized in that it comprises:

[0006] The package has a first side and a second side that are opposite to each other;

[0007] A lead frame is disposed inside the package;

[0008] A plurality of power chips and a plurality of high-voltage drive chips, arranged according to a predetermined electrical connection relationship, are disposed on the first lead frame;

[0009] Several pins, including low-voltage pins and high-voltage pins of the high-voltage drive chip, and power pins of the power chip, wherein the power pins of the power chip include a DC bus negative pin;

[0010] in:

[0011] The high-voltage pin and power pin are located on the first side of the package, and the low-voltage pin is located on the second side of the package.

[0012] Optionally, the lead frame includes a first lead frame having a base island for mounting the power chip, and the first lead frame leads the power terminal of the power chip to a power pin on a first side of the package.

[0013] Optionally, the lead frame includes a second lead frame having a base island for mounting the high-voltage driver chip, and the second lead frame leads the low-voltage terminal of the high-voltage driver chip to a low-voltage pin on the second side of the package.

[0014] Optionally, the lead frame includes a third lead frame, the third lead frame including a first lead frame disposed on a first side of the package, the third lead frame leading the high voltage terminal of the high voltage driver chip to a high voltage pin on a second side of the package.

[0015] Optionally, the first lead frame is disposed on the first side of the package, and the second lead frame is disposed on the second side of the package.

[0016] Optionally, the power chip includes a high-side power chip and a low-side power chip. The number of high-side power chips is three, including a high-side U-phase power chip, a high-side V-phase power chip, and a high-side W-phase power chip; the number of low-side power chips is three, including a low-side U-phase power chip, a low-side V-phase power chip, and a low-side W-phase power chip; wherein:

[0017] The high-side U-phase power chip is arranged adjacent to the low-side U-phase power chip, the high-side V-phase power chip is arranged adjacent to the low-side V-phase power chip, and the high-side W-phase power chip is arranged adjacent to the low-side W-phase power chip.

[0018] Optionally, the number of high-voltage drive chips is three, including a high-voltage U-phase drive chip, a high-voltage V-phase drive chip, and a high-voltage W-phase drive chip; each high-voltage drive chip includes a low-side drive ground terminal, and each low-side power chip includes a source terminal; wherein:

[0019] The low-side driving ground terminal of the high-voltage U-phase driver chip is connected to the source terminal of the low-side U-phase power chip, the low-side driving ground terminal of the high-voltage V-phase driver chip is connected to the source terminal of the low-side V-phase power chip, and the low-side driving ground terminal of the high-voltage W-phase driver chip is connected to the source terminal of the low-side W-phase power chip.

[0020] Optionally, the lead frame includes a first lead frame disposed on a first side of the package, the distance between the first lead frame and the heat dissipation surface of the package is a first distance, the distance between the pin and the heat dissipation surface of the package is a second distance, and the first distance is less than the second distance.

[0021] Optionally, the lead frame includes a second lead frame disposed on the second side of the package, the distance between the second lead frame and the heat dissipation surface of the package is a third distance, the third distance is less than the second distance and greater than the first distance.

[0022] Optionally, the distance between the inner pin corresponding to the high-voltage pin and the heat dissipation surface of the package is a fourth distance, which is consistent with the second distance.

[0023] This utility model proposes an intelligent power module, comprising: a package having a first side and a second side opposite to each other; a lead frame disposed inside the package; a plurality of power chips and a plurality of high-voltage drive chips arranged according to a predetermined electrical connection relationship, disposed on the first lead frame; and a plurality of pins, including low-voltage pins and high-voltage pins of the high-voltage drive chips, and power pins of the power chips, wherein the power pins of the power chips include a DC bus negative pin; wherein the high-voltage pins and power pins are disposed on the first side of the package, and the low-voltage pins are disposed on the second side of the package. Optionally, the lead frame includes a first lead frame having a base island for mounting the power chips, and the first lead frame leads the power terminals of the power chips to the power pins on the first side of the package. By placing all the low-voltage pins on the first side of the package and all the high-voltage and power pins on the second side of the package, the high and low voltage pins are isolated in position, avoiding interference between the high-voltage pins and the low-voltage pins. At the same time, by setting an independent DC bus negative pin, a current sensing resistor and its related protection circuit can be connected to the DC bus negative pin, enabling independent overcurrent protection for the three-phase low side. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0027] Figure 1 This is a front view of the internal structure of the first embodiment of the intelligent power module of this utility model;

[0028] Figure 2 This is a pin diagram of the intelligent power module of this utility model;

[0029] Figure 3 This is a side view of the internal structure of the intelligent power module of this utility model;

[0030] Figure 4 This is a side view of the internal structure of a smart power module in the prior art;

[0031] Figure 5 Side view of the internal structure of the heat dissipation substrate of the intelligent power module of this utility model;

[0032] Figure 6 This is a side view of the ceramic substrate of the intelligent power module of this utility model;

[0033] Figure 7 This is a front view of the ceramic substrate of the intelligent power module of this utility model;

[0034] Figure 8 This is a front view of the internal structure of the intelligent power module of this utility model;

[0035] Figure 9 A side view of the internal structure of the heat dissipation substrate (metal substrate) of the intelligent power module of this utility model.

[0036] Explanation of icon numbers:

[0037] label name label name 1 Package Q1 High-side U-phase power chip 21 First lead frame Q2 Low-side U-phase power chip 22 Second lead frame Q3 High-side V-phase power chip 3 power chip Q4 Low-side V-phase power chip 4 High voltage driver chip Q5 High-side W-phase power chip 5 bond wire Q6 Low-side W-phase power chip 6 Heat sink D3 High voltage W-phase driver chip 61 Ceramic substrate D1 High voltage U-phase driver chip 62 thermally conductive metal layer D2 High voltage V-phase driver chip 63 metal substrate 23 Internal pins 64 insulating adhesive 7 tin solder Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The following disclosure provides numerous different embodiments or examples for implementing various structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0040] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention. To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0041] This utility model provides an intelligent power module, referring to... Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the intelligent power module of this utility model, including:

[0042] Package 1 has a first side and a second side opposite to each other;

[0043] A lead frame is disposed inside the package;

[0044] A plurality of power chips and a plurality of high-voltage drive chips, arranged according to a predetermined electrical connection relationship, are disposed on the first lead frame;

[0045] Several pins, including low-voltage pins and high-voltage pins of the high-voltage drive chip, and power pins of the power chip, wherein the power pins of the power chip include a DC bus negative pin;

[0046] in:

[0047] The high-voltage pin and power pin are located on the first side of the package, and the low-voltage pin is located on the second side of the package.

[0048] Package 1 is injection molded and encapsulates the chip, internal leads, lead frame, etc. together, serving to protect the chip, internal leads, lead frame, etc. inside the package. The material can be set according to actual needs, such as a molding compound made of epoxy resin.

[0049] The lead frame serves as the chip carrier within the intelligent power module. It is used to achieve electrical connections between the circuit leads inside the intelligent power module and the external pins of the intelligent power module using bonding materials, thus forming an electrical circuit. The bonding materials used in the lead frame can be selected based on actual needs, such as gold wire or copper wire.

[0050] It is understandable that the intelligent power module integrates power chip 3 and high-voltage driver chip 4. Therefore, when the intelligent power module is used, it is necessary to set high-voltage power supply and low-voltage logic power supply, logic signals, etc. However, the low-voltage power supply is easily interfered with by the high-voltage power supply, causing problems such as high-voltage breakdown and false triggering. In order to solve this problem, in this embodiment, the pins are divided and set separately based on high and low voltage. Specifically, all low-voltage pins are set on the first side of the package 1, while all high-voltage pins and power pins are set on the second side of the package 1, thereby achieving isolation between the high and low voltage pins and avoiding interference between the high-voltage pins and the low-voltage pins.

[0051] See Figure 2 ,based on Figure 2 The pin configurations in this embodiment are described below:

[0052] Among them, pins 1 to 16 are low-voltage pins, specifically including the low-voltage logic power supply pin VCC, the low-voltage power ground pin COM, the low-voltage signal pins HIN / LIN, and other low-voltage pins. U, V, and W respectively indicate the pins corresponding to U, V, and W. For example, LINu is the low-voltage signal pin of phase U. The same applies to the following, and will not be repeated.

[0053] Pins 18, 22, and 25 are high-voltage pins. Pin 18 is the U-phase high-voltage pin VBu; pin 22 is the V-phase high-voltage pin VBv; and pin 25 is the W-phase high-voltage pin VBw.

[0054] The remaining pins are power pins. Specifically, pin 17 is the positive pin of the DC bus; pin 19 is the U-phase output terminal; pin 23 is the V-phase output terminal; pin 24 is a dummy pin used to connect internally to the P terminal and disconnect externally; pin 26 is the W-phase output terminal. In this embodiment, three additional negative pins of the DC bus, 20, 21, and 27, are also provided. Specifically, pin 20 is the negative pin of the U-phase DC bus, Nu; pin 21 is the negative pin of the V-phase DC bus, Nv; and pin 27 is the negative pin of the W-phase DC bus, Nw.

[0055] In this embodiment, by setting an independent DC bus negative pin, a current sensing resistor and its related protection circuit can be connected to the DC bus negative pin, so that overcurrent protection can be provided independently for the three-phase low side.

[0056] Further details will follow. Figure 1 The lead frame includes a first lead frame 21, which has a base island for mounting the power chip 3. The first lead frame 21 leads the power terminal of the power chip 3 to the power pin on the first side of the package 1.

[0057] The first lead frame 21 includes multiple base islands, each base island corresponding to a power chip 3. Specifically, the power chip 3 can be soldered to the corresponding base island of the first lead frame 21 using appropriate soldering equipment. The specific type of solder can be set according to actual needs and can be, but is not limited to, tin solder or silver paste.

[0058] The electrical connection between the power terminal of the power chip 3 and the electrode of the first lead frame 21 is made by bonding wire 5. The material of the bonding wire 5 can be set according to actual needs, such as gold wire or copper wire; the first lead frame 21 leads the power terminal to the corresponding power pin.

[0059] Furthermore, the lead frame includes a second lead frame 22, which has a base island for mounting the high voltage driving chip 4, and the second lead frame 22 leads the low voltage terminal of the high voltage driving chip 4 to the low voltage pin on the second side of the package 1.

[0060] The second lead frame 22 includes multiple base islands, each base island corresponding to a high-voltage driving chip 4. Specifically, the high-voltage driving chip 4 can be bonded to the corresponding base island of the second lead frame 22 by chip adhesive. The specific type of chip adhesive can be set according to actual needs, and can be, but is not limited to, conductive silver paste or non-conductive paste.

[0061] The electrical connection between the low-voltage end of the high-voltage driver chip 4 and the electrode of the second lead frame 22 is made by bonding wire 5. The material of the bonding wire 5 can be set according to actual needs, such as gold wire or copper wire; the second lead frame 22 leads the low-voltage end to the corresponding low-voltage pin.

[0062] Furthermore, the lead frame includes a third lead frame disposed on the second side of the package body, the third lead frame leading the high voltage terminal of the high voltage driver chip 4 to the high voltage pin on the second side of the package body 1.

[0063] The third lead frame has an inner pin 23 for the high voltage pin. One end of the third lead frame is bonded to the high voltage terminal of the high voltage driver chip 4 using a bonding wire 5, and the other end is led out to the corresponding high voltage pin.

[0064] Specifically, in the setting of the inner pin 23, the third lead frame corresponding to the inner pin 23 is set between the high-side power chip 3 and the low-side power chip of the corresponding phase; for example, the inner pin 23 corresponding to the U-phase high voltage pin is set between the high-side U-phase power chip Q1 and the low-side U-phase power chip Q2; the inner pin 23 corresponding to the V-phase high voltage pin is set between the high-side V-phase power chip Q3 and the low-side V-phase power chip Q4; the inner pin 23 corresponding to the W-phase high voltage pin is set between the high-side W-phase power chip Q5 and the low-side W-phase power chip Q6.

[0065] Furthermore, the first lead frame 21 is disposed on the first side of the package 1, and the second lead frame 22 is disposed on the second side of the package 1.

[0066] It is understandable that, in order to facilitate connection with high voltage pins, low voltage pins, and power pins, the first lead frame 21 can be placed on the first side of the package body 1, while the second lead frame 22 can be placed on the second side of the package body 1.

[0067] Further, the power chip 3 includes a high-side power chip 3 and a low-side power chip 3. The number of high-side power chips 3 is 3, including a high-side U-phase power chip Q1, a high-side V-phase power chip Q3, and a high-side W-phase power chip Q5; the number of low-side power chips is 3, including a low-side U-phase power chip Q2, a low-side V-phase power chip Q4, and a low-side W-phase power chip Q6; wherein:

[0068] The high-side U-phase power chip Q1 and the low-side U-phase power chip Q2 are arranged adjacent to each other, the high-side V-phase power chip Q3 and the low-side V-phase power chip Q4 are arranged adjacent to each other, and the high-side W-phase power chip Q5 and the low-side W-phase power chip Q6 are arranged adjacent to each other.

[0069] In this embodiment, a three-phase full-bridge circuit is constructed by setting a high-side U-phase power chip Q1, a high-side V-phase power chip Q3, a high-side W-phase power chip Q5, a low-side U-phase power chip Q2, a low-side V-phase power chip Q4, and a low-side W-phase power chip Q6, with one high-power side chip and one low-power side chip corresponding to each phase.

[0070] It is understandable that the connection relationship between the high-side power chip 3 and the low-side power chip of the same phase is relative. For example, the high-side power chip 3 and the low-side power chip need to be connected to the high-voltage drive chip 4 of the corresponding phase, as well as the relevant external circuits of the corresponding phase. Therefore, in order to facilitate the circuit setup, the high-side and low-side power chips of the same phase are arranged adjacently in this embodiment. Figure 4 In the middle, from left to right, the low-side W-phase power chip Q6, the high-side W-phase power chip Q5, the low-side V-phase power chip Q4, the high-side V-phase power chip Q3, the low-side U-phase power chip Q2, and the high-side U-phase power chip Q1 are respectively set.

[0071] To further facilitate circuit layout, when configuring the pins on the second side of package 1, the high-voltage pins can be positioned adjacent to the output pins of the corresponding phase, such as... Figure 3In the diagram, pin 18 is the U-phase high-voltage pin, pin 19 is the U-phase output terminal, and pins 18 and 19 are arranged adjacent to each other; pin 22 is the V-phase high-voltage pin, pin 23 is the V-phase output terminal, and pins 22 and 23 are arranged adjacent to each other; pin 25 is the W-phase high-voltage pin, pin 26 is the W-phase output terminal, and pins 25 and 26 are arranged adjacent to each other.

[0072] Furthermore, the number of high-voltage drive chips 4 is three, including a high-voltage U-phase drive chip D1, a high-voltage V-phase drive chip D2, and a high-voltage W-phase drive chip D3; each high-voltage drive chip 4 includes a low-side drive ground terminal, and each low-side power chip includes a source terminal; wherein:

[0073] The low-side driving ground terminal of the high-voltage U-phase drive chip D1 is connected to the source terminal of the low-side U-phase power chip Q2, the low-side driving ground terminal of the high-voltage V-phase drive chip D2 is connected to the source terminal of the low-side V-phase power chip Q4, and the low-side driving ground terminal of the high-voltage W-phase drive chip D3 is connected to the source terminal of the low-side W-phase power chip Q6.

[0074] The high-voltage driver chip 4 is used to drive the power chips 3 of the corresponding phases; specifically, the high-voltage U-phase driver chip D1 drives the high-side U-phase power chip Q1 and the low-side U-phase power chip Q2; the high-voltage V-phase driver chip D2 drives the high-side V-phase power chip Q3 and the low-side V-phase power chip Q4; and the high-voltage W-phase driver chip D3 drives the high-side W-phase power chip Q5 and the low-side W-phase power chip Q6.

[0075] When the ESD (Electrostatic Protection) capability of the COM-DC bus negative pin is poor, it can easily lead to ESD breakdown of the gate of the low-side power chip. Therefore, in order to improve the ESD capability, in this embodiment, a high-voltage driver chip 4 with an independent low-side drive ground terminal is selected, and the source of the corresponding phase low-side power chip is connected to the low-side drive ground terminal of the high-voltage driver chip 4, thereby increasing the ESD release circuit. This avoids the ESD voltage between COM-Nu, Nv, and Nw from directly acting on the gate of the low-side power chip, thus preventing the gate-source breakdown problem of the low-side power chip.

[0076] Further, see Figure 3 The lead frame includes a first lead frame 21 disposed on the first side of the package 1. The distance between the first lead frame 21 and the heat dissipation surface of the package 1 is a first distance, and the distance between the pin and the heat dissipation surface of the package 1 is a second distance. The first distance is less than the second distance.

[0077] The first lead frame 21 serves as the carrier for the power chip 3; the first lead frame 21 establishes an electrical connection between the circuit lead-out terminals of the power chip 3 and the power pins of the intelligent power module.

[0078] It is understandable that power chip 3 is the main heat source within the intelligent power module; see [link / reference] Figure 4 In existing technologies, to facilitate wiring setup, the lead frame and the pins of the intelligent power module are usually placed on the same plane. In this case, the lead frame is far from the heat dissipation surface of the package 1. Therefore, the power chip 3 mounted on the lead frame is also far from the heat dissipation surface of the package 1, resulting in poor heat dissipation. Figure 4 The right side of the middle package 1 is the heat dissipation surface.

[0079] To improve the heat dissipation of the power chip 3, in this embodiment, the distance between the first lead frame 21 and the heat dissipation surface of the package 1 is reduced. Since the relative position of the pin and the heat dissipation surface of the package 1 remains unchanged, the distance between the first lead frame 21 and the heat dissipation surface of the package 1 is smaller than the distance between the pin and the heat dissipation surface of the package 1, that is, the first distance is smaller than the second distance. This allows the power chip 3, which is mounted on the first lead frame 21, to be closer to the heat dissipation surface of the package 1, enabling the power chip 3 to dissipate heat faster and thus improving the heat dissipation capability of the intelligent power module.

[0080] The specific setting of the distance between the first lead frame 21 and the heat dissipation surface of the package 1 can be set according to actual needs. For example, a step can be set to increase the height of the first lead frame 21 in the thickness direction, thereby setting the distance between the first lead frame 21 and the heat dissipation surface of the package 1. The specific value of the first distance between the first lead frame 21 and the heat dissipation surface of the package 1 can be set according to the needs of the smart power module in actual application, such as 0.55mm.

[0081] In this embodiment, by reducing the distance between the first lead frame 21 and the heat dissipation surface, the power chip 3 disposed on the first lead frame 21 can be closer to the heat dissipation surface of the package 1. As the main heat-generating device in the smart power module, the reduction in the distance between the power chip 3 and the heat dissipation surface enables the power chip 3 to dissipate heat faster, thereby improving the heat dissipation capacity of the smart power module and preventing the smart power module from overheating.

[0082] Furthermore, the lead frame includes a second lead frame 22 disposed on the second side of the package 1, and the distance between the second lead frame 22 and the heat dissipation surface of the package 1 is a third distance, which is less than the second distance and greater than the first distance.

[0083] The second lead frame 22 serves as the carrier for the high-voltage driver chip 4; the second lead frame 22 establishes an electrical connection between the circuit lead-out terminals of the high-voltage driver chip 4 and the high-voltage pins and low-voltage pins of the intelligent power module.

[0084] The high-voltage driver chip 4 is used to drive the power chip 3.

[0085] In the prior art, the first lead frame 21 and the second lead frame 22 of the intelligent power module are disposed on the same plane as the pins of the intelligent power module, that is, the distance between the first lead frame 21, the second lead frame 22 and the pins of the intelligent power module and the heat dissipation surface of the package 1 is the same. After reducing the distance between the first lead frame 21 and the heat dissipation surface of the package 1 to a first distance, the second lead frame 22 and the pins of the intelligent power module are still on the same plane. At this time, the distance between the second lead frame 22 and the first lead frame 21 is the difference between the first distance and the second distance. It is understandable that the power chip 3 disposed on the first lead frame 21 needs to be connected to the high-voltage drive chip 4 disposed on the second lead frame 22. When the height difference between the first lead frame 21 and the second lead frame 22 is large, it will cause the arc of the connection line between the high-voltage drive chip 4 and the power chip 3 to be too high and the line length to be too long. Excessive length hinders manufacturing; furthermore, if the distance between the second lead frame 22 and the heat dissipation surface of the package 1 is simultaneously reduced to the first distance, the high-voltage driver chip 4 on the second lead frame 22 and the low-voltage pin will also suffer from excessively high arc and excessively long line length. To address this issue, in this embodiment, the distance between the second lead frame 22 and the heat dissipation surface of the package 1 is reduced to a third distance, which is between the first and second distances. Specifically, the distance between the second lead frame 22 and the heat dissipation surface of the package 1 is less than the distance between the pin and the heat dissipation surface of the package 1, but greater than the distance between the first lead frame 21 and the heat dissipation surface of the package 1. In other words, the height of the second lead frame 22 is between the first lead frame 21 and the pin, thus avoiding excessively high arc and excessively long line length between the second lead frame 22 and the first lead frame 21, and between the second lead frame 22 and the pin. The specific third distance between the second lead frame 22 and the heat dissipation surface of the package 1 can be set based on actual needs, such as setting it to the average of the first and second distances.

[0086] In this embodiment, by setting the third distance between the second lead frame 22 and the heat dissipation surface to be between the first distance and the second distance, it is possible to avoid excessively high arcs and excessively long lines between the second lead frame 22 and the first lead frame 21, and between the second lead frame 22 and the pin.

[0087] Furthermore, the distance between the inner pin 23 corresponding to the high-voltage pin and the heat dissipation surface of the package 1 is a fourth distance, which is consistent with the second distance.

[0088] Understandably, after reducing the distance between the first lead frame 21 and the heat dissipation surface of the package 1 to a first distance, and reducing the distance between the second lead frame 22 and the heat dissipation surface of the package 1 to a third distance, the distance between the pin and the heat dissipation surface of the package 1 remains the second distance. However, the high-voltage pin is located on the first side of the package 1, while the high-voltage driver chip 4, which needs to be connected to the inner pin 23 of the high-voltage pin, is located on the second side of the package 1. Therefore, when the height of the second lead frame 22 where the high-voltage driver chip 4 is located increases, the distance between the inner pin of the high-voltage pin... The connection line between the inner pin 23 and the high-voltage driver chip 4 has an excessively high arc and excessively long length, which is inconvenient for manufacturing. Therefore, in order to solve this problem, in this embodiment, the distance between the inner pin 23 of the high-voltage pin and the heat dissipation surface of the package 1 is reduced to be consistent with the first lead frame 21. That is, the distance between the inner pin 23 of the high-voltage pin and the heat dissipation surface of the package 1 is equal to the distance between the first lead frame 21 and the heat dissipation surface of the package 1; that is, the fourth distance is equal to the first distance, thereby avoiding the excessively high arc and excessively long length of the connection line between the high-voltage driver chip 4 and the inner pin 23 of the high-voltage pin.

[0089] Meanwhile, the inner pin 23 of the high-voltage pin has the same height as the first lead frame 21, which also facilitates product packaging.

[0090] In this embodiment, by setting the fourth distance between the inner pin 23 of the high voltage pin and the heat dissipation surface to be consistent with the first distance, it is possible to avoid the line arc between the high voltage driver chip 4 and the inner pin 23 of the high voltage pin being too high and the line length being too long.

[0091] To further improve the heat dissipation of the intelligent power module, see [link / reference]. Figure 5 In this embodiment, a heat dissipation substrate 6 may also be provided, which is disposed on the heat dissipation surface of the package 1 relative to the first lead frame 21;

[0092] The heat dissipation substrate 6 can improve the speed of heat dissipation. Therefore, in this embodiment, by setting the heat dissipation substrate 6 relative to the first lead frame 21, the heat dissipation substrate 6 can accelerate the heat dissipation of the power chip 3 on the first lead frame 21, thereby further improving the heat dissipation capability of the smart power module. It can be understood that the side of the heat dissipation substrate 6 facing away from the first lead frame 21 is exposed to the environment and directly serves as the heat dissipation surface of the smart power module.

[0093] Understandably, the heat dissipation substrate 6 needs to be made of a material with high thermal conductivity, which can be, but is not limited to, ceramic or metal.

[0094] Further, see Figure 5 The heat dissipation substrate 6 is a ceramic substrate 61, which is soldered to the base island of the first lead frame 21 by solder 7.

[0095] It is understandable that the heat generated by the power chip 3 needs to be transferred to the heat dissipation surface of the package 1 for heat dissipation. Therefore, the heat generated by the power chip 3 needs to reach the external environment through the base island, solder, and heat dissipation substrate 6. Therefore, the solder between the heat dissipation substrate 6 and the first lead frame 21 will also affect the heat dissipation of the power chip 3. The heat dissipation substrate 6 is soldered onto the first lead frame 21. In terms of soldering alone, the specific soldering material can be selected based on actual needs. In this embodiment, in order to further improve the heat dissipation of the power chip 3, tin solder 7 is selected as the soldering material. Tin solder 7 has good thermal conductivity. Therefore, the heat dissipation substrate 6 is soldered onto the base island by tin solder 7, which can improve the heat dissipation capacity. In other embodiments, materials with excellent thermal conductivity, such as silver paste, can also be used for soldering.

[0096] Further, see Figure 6 The heat dissipation substrate 6 is a ceramic substrate 61. A thermally conductive metal layer 62 is provided on the side of the ceramic substrate 61 near the first lead frame. The thermally conductive metal layer 62 is soldered to the base island of the first lead frame 21 by solder 7.

[0097] To further improve heat dissipation, in this embodiment, a thermally conductive metal layer 62 is further provided on one side of the heat dissipation substrate 6; the thermally conductive metal layer 62 is in contact with the base island; the thermally conductive metal layer 62 can accelerate the transfer of heat from the base island to the heat dissipation substrate 6 for heat dissipation, thereby improving the heat dissipation capability of the power chip 3. The thermally conductive metal layer 62 can be made of a material with good thermal conductivity, such as tungsten or molybdenum copper.

[0098] It is understandable that the thermally conductive metal layer 62 is in contact with the base island. Therefore, the thermally conductive metal layer 62 needs to be soldered to the base island. For the same reason as in the previous embodiment, solder 7 is used to solder the thermally conductive metal layer 62.

[0099] Further, see Figure 6 , Figure 7 and Figure 8 The thermally conductive metal layer 62 is aligned with the projection of the first lead frame 21 onto the ceramic substrate.

[0100] It is understood that the thermally conductive metal layer 62 is in direct contact with the first lead frame 21. In order to improve the thermal conductivity and reduce the material of the thermally conductive metal layer 62, in this embodiment, the projections of the thermally conductive metal layer 62 and the first lead frame 21 on the ceramic substrate are set to be consistent. It is understood that the first lead frame 21, the thermally conductive metal layer 62, and the heat dissipation substrate 6 are stacked. When the projections of the thermally conductive metal layer 62 and the first lead frame 21 on the ceramic substrate are consistent, the thermally conductive metal layer 62 can be completely attached to the first lead frame 21, thereby maximizing the area of ​​heat transfer from the base island to the ceramic substrate, thereby improving the heat dissipation efficiency.

[0101] Furthermore, the outer surface of the thermally conductive metal layer 62 is plated with a welding metal layer.

[0102] It is understood that the thermally conductive metal layer 62 is made of a material with good thermal conductivity. However, a metal with good thermal conductivity does not necessarily have good solderability. Therefore, in this embodiment, a soldering metal layer is plated on the outer surface of the thermally conductive metal layer 62 so that the thermally conductive metal layer 62 has both good thermal conductivity and solderability. It is understood that the soldering metal layer is made of a material with good solderability, such as nickel, silver, or gold.

[0103] Further, see Figure 9 The heat dissipation substrate 6 is a ceramic substrate 61 or a metal substrate 63, and the metal substrate 63 is bonded to the base island of the first lead frame 21 by insulating adhesive 64.

[0104] It is understandable that when the heat dissipation substrate 6 is metal, if the metal substrate 63 is soldered to the base island by solder, a short circuit will occur between the base islands. Therefore, in this embodiment, when the heat dissipation substrate 6 is a metal substrate 63, the metal substrate 63 and the base island of the first lead frame 21 are bonded together by insulating adhesive 64 to prevent a short circuit between the base islands.

[0105] In the overall manufacturing of the intelligent power module, the power chip 3 is soldered to the corresponding base island of the first lead frame 21 using appropriate soldering equipment, and the high-voltage driver chip 4 is bonded to the corresponding base island of the second lead frame 22 using chip bonding adhesive using chip mounting equipment. The electrical connection between the power chip 3 and the electrodes of the first lead frame 21 is achieved using bonding wires 5, and the connection between the driver chip electrodes and the electrodes of the second lead frame 22, and between the driver chip electrodes and the electrodes of the power chip 3, is also achieved using bonding wires 5. After the intelligent power module completes the bonding process, it is molded using encapsulating adhesive, followed by electroplating, and finally, the individual products are separated through a lead cutting and forming process.

[0106] In this utility model, the terms "first", "second", "third", "fourth" and "fifth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0107] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0108] Although embodiments of the present invention have been shown and described above, the scope of protection of the present invention is not limited thereto. It is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, and substitutions to the above embodiments within the scope of the present invention, and such changes, modifications, and substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.

Claims

1. A smart power module, characterized in that, include: The package has a first side and a second side that are opposite to each other; A lead frame is disposed inside the package; A number of power chips and a number of high-voltage drive chips, arranged according to a predetermined electrical connection relationship, are disposed on the first lead frame. Several pins, including low-voltage pins and high-voltage pins of the high-voltage drive chip, and power pins of the power chip, wherein the power pins of the power chip include a DC bus negative pin; in: The high-voltage pin and power pin are located on the first side of the package, and the low-voltage pin is located on the second side of the package.

2. The intelligent power module as described in claim 1, characterized in that, The lead frame includes a first lead frame having a base island for mounting the power chip, and the first lead frame leads the power terminal of the power chip to a power pin on a first side of the package.

3. The intelligent power module as described in claim 2, characterized in that, The lead frame includes a second lead frame having a base island for mounting the high-voltage driver chip, and the second lead frame leads the low-voltage terminal of the high-voltage driver chip to a low-voltage pin on the second side of the package.

4. The intelligent power module as described in claim 3, characterized in that, The lead frame includes a third lead frame disposed on the second side of the package, the third lead frame leading the high voltage terminal of the high voltage driver chip to the high voltage pin on the second side of the package.

5. The intelligent power module as described in claim 4, characterized in that, The first lead frame is disposed on the first side of the package, and the second lead frame is disposed on the second side of the package.

6. The intelligent power module as described in claim 1, characterized in that, The power chip includes a high-side power chip and a low-side power chip. The number of high-side power chips is three, including a high-side U-phase power chip, a high-side V-phase power chip, and a high-side W-phase power chip. The number of low-side power chips is also three, including a low-side U-phase power chip, a low-side V-phase power chip, and a low-side W-phase power chip. Wherein: The high-side U-phase power chip is arranged adjacent to the low-side U-phase power chip, the high-side V-phase power chip is arranged adjacent to the low-side V-phase power chip, and the high-side W-phase power chip is arranged adjacent to the low-side W-phase power chip.

7. The intelligent power module as described in claim 6, characterized in that, The number of high-voltage drive chips is three, including a high-voltage U-phase drive chip, a high-voltage V-phase drive chip, and a high-voltage W-phase drive chip; each high-voltage drive chip includes a low-side drive ground terminal, and each low-side power chip includes a source terminal; wherein: The low-side driving ground terminal of the high-voltage U-phase driver chip is connected to the source terminal of the low-side U-phase power chip, the low-side driving ground terminal of the high-voltage V-phase driver chip is connected to the source terminal of the low-side V-phase power chip, and the low-side driving ground terminal of the high-voltage W-phase driver chip is connected to the source terminal of the low-side W-phase power chip.

8. The intelligent power module as described in claim 1, characterized in that, The lead frame includes a first lead frame disposed on a first side of the package, the distance between the first lead frame and the heat dissipation surface of the package is a first distance, the distance between the pin and the heat dissipation surface of the package is a second distance, and the first distance is less than the second distance.

9. The intelligent power module as described in claim 8, characterized in that, The lead frame includes a second lead frame disposed on the second side of the package body. The distance between the second lead frame and the heat dissipation surface of the package body is a third distance, which is less than the second distance and greater than the first distance.

10. The intelligent power module as described in claim 9, characterized in that, The distance between the inner pin corresponding to the high-voltage pin and the heat dissipation surface of the package is the fourth distance, which is consistent with the second distance.

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