Enabling circuit and power supply circuit

Abstract

The utility model provides an enabling circuit and a power supply circuit, and belongs to the technical field of power supplies. The enabling circuit comprises a transistor, a first voltage dividing unit and a second voltage dividing unit, and the on-off between the voltage input end of the first voltage dividing unit and the voltage input end of the second voltage dividing unit is controlled by utilizing the on-off of the transistor, so that the voltage dividing parameter of the second voltage dividing unit can be reasonably set; and when the first voltage drops to the first threshold value, the value of the enable signal VEN output by the voltage division output end of the second voltage division unit is lowered to be smaller than the second threshold value, so that the power supply chip cannot continue to work, and the phenomenon of output overshoot occurring when the power supply chip is shut down is effectively avoided or reduced.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to an enable circuit and a power supply circuit. Background Technology

[0002] MCUs, FPGAs, and other load chips require low-voltage power supply chips to provide low-power DC power. In developing this application, the inventors discovered at least the following problems in the prior art: Typically, the voltage difference between the input and output voltages of a low-voltage power supply chip is relatively large, and the output load is usually small. Furthermore, the internal sensitivity of the low-voltage power supply chip is insufficient. At the moment of system shutdown or power failure, the low-voltage power supply chip will experience an output surge, which may exceed the load chip's tolerance range, easily causing damage to the load chip. Utility Model Content

[0003] To effectively solve the technical problems existing in the prior art, this application provides an enable circuit and a power supply circuit that can effectively reduce power-off output overshoot.

[0004] According to a first aspect of the embodiments of this application, an enabling circuit is provided, including a transistor, a first voltage divider unit, and a second voltage divider unit;

[0005] The current input terminal of the transistor is connected to the voltage input terminal of the first voltage divider unit, the control terminal of the transistor is connected to the voltage divider output terminal of the first voltage divider unit, and the current output terminal of the transistor is connected to the voltage input terminal of the second voltage divider unit.

[0006] The voltage input terminal of the first voltage divider unit is used to receive the first voltage, and the voltage output terminal of the second voltage divider unit is used to output an enable signal to the enable terminal of the power chip.

[0007] Optionally, the transistor is a PMOS transistor, the current input terminal of the transistor is the source terminal of the PMOS transistor, the control terminal of the transistor is the gate terminal of the PMOS transistor, and the current output terminal of the transistor is the drain terminal of the PMOS transistor.

[0008] Optionally, the first voltage divider unit includes a first resistor and a second resistor. The first end of the first resistor is the voltage input terminal of the first voltage divider unit, the second end of the first resistor is the voltage divider output terminal of the first voltage divider unit, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded.

[0009] Optionally, the second voltage divider unit includes a third resistor and a fourth resistor. The first end of the third resistor is the voltage input terminal of the second voltage divider unit, the second end of the third resistor is the voltage divider output terminal of the second voltage divider unit, the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is grounded.

[0010] Optionally, the enabling circuit further includes a first capacitor, the first terminal of which is connected to the voltage input terminal of the first voltage divider unit, and the second terminal of which is grounded.

[0011] According to a second aspect of the embodiments of this application, a power supply circuit is provided, including a power supply chip and an enable circuit as described in any of the preceding claims;

[0012] The enabling circuit is connected to the enabling terminal of the power chip and is used to output an enabling signal to the enabling terminal of the power chip.

[0013] Optionally, the power supply circuit further includes a second capacitor, the first end of which is connected to the voltage input terminal of the power chip, and the second end of which is grounded.

[0014] The power chip has a voltage input terminal for receiving a second voltage, which is then converted into a supply voltage. The supply voltage is output to the load via the power chip's voltage output terminal to supply power to the load.

[0015] Optionally, the power supply circuit further includes a third capacitor, the first end of which is connected to the feedback terminal of the power chip, and the second end of which is grounded.

[0016] Optionally, the power supply circuit further includes at least one fourth capacitor, the first end of which is connected to the voltage output terminal of the power chip, and the second end of which is grounded.

[0017] Optionally, the power supply chip is a low-dropout linear regulator chip.

[0018] As can be seen from the above, the technical solution provided in this application has at least the following beneficial effects:

[0019] The enabling circuit provided in this application uses the switching on and off of a transistor to control the connection and disconnection between the voltage input terminals of the first voltage divider unit and the second voltage divider unit. By appropriately setting the voltage division parameters of the second voltage divider unit, when the first voltage drops to a first threshold, the value of the enabling signal VEN output from the voltage divider unit is pulled down to below a second threshold, thus preventing the power supply chip from continuing to operate and effectively avoiding or reducing output overshoot when the power supply chip is powered off. The power supply circuit and the enabling circuit provided in this application achieve the same beneficial effects. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 This is a schematic diagram of a low-voltage power supply circuit with fixed output.

[0022] Figure 2 for Figure 1 The waveform diagram of the low-voltage power supply circuit shown is as follows;

[0023] Figure 3 This application provides schematic diagrams of the enabling circuit structure in some embodiments;

[0024] Figure 4 This is a schematic diagram of the power supply circuit provided in some embodiments of this application;

[0025] Figure 5 for Figure 4 The waveform diagram of the power supply circuit shown is shown. Detailed Implementation

[0026] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the ways in which this application may be implemented. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] In the description of this application, unless otherwise stated, "a plurality of" means two or more. Furthermore, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] Please see Figure 1 The diagram shows a schematic of a low-voltage power supply circuit, which includes a low-voltage power supply chip U1 and corresponding peripheral circuitry. The low-voltage power supply chip U1 has an input pin IN1, a ground pin GND1, an enable pin EN1, an output pin OUT1, and feedback pins BP1 / FB1. The peripheral circuitry corresponding to the low-voltage power supply chip U1 includes a pull-up resistor R11 and a decoupling ceramic capacitor C13, one end of which is connected to the enable pin EN1. The other end of the pull-up resistor R11 is connected to the voltage input terminal to receive the input voltage IN1, and the other end of the decoupling ceramic capacitor C13 is grounded. When the input voltage is received at the input pin IN1, the decoupling ceramic capacitor C13 pulls up the voltage of the enable pin EN1, causing the low-voltage power supply chip U1 to enter the operating state. The peripheral circuitry corresponding to the low-voltage power supply chip U1 also includes an input capacitor connected between the input pin IN1 and the ground pin GND1, with the ground pin GND1 grounded. The input capacitor connected to the input pin IN1 may include, but is not limited to, capacitors C11 and C12. In addition, the peripheral circuit of the low-voltage power chip U1 also includes a ceramic capacitor C14 connected to the feedback pin BP1 / FB1 and at least one output capacitor connected to the output pin OUT1. The at least one output capacitor includes ceramic capacitors C15, C16, C17 and decoupling ceramic capacitor C18.

[0030] The low-voltage power supply chip U1 is typically a low-dropout linear regulator chip, with an input voltage VI N1 generally of 5V or 3.3V and an output voltage of 1.2V. However, the inventors of this application discovered during their research that, for example... Figure 1 The low-voltage power supply shown has a fixed low output voltage, which will cause an output voltage overshoot at the moment of power-off. Specifically... Figure 2 As shown, it is Figure 1The waveform diagram of the low-voltage power supply circuit shown illustrates that when the input voltage VI N1 is 5V and the output voltage is a fixed 1.2V, the large voltage difference between the input and output terminals of the low-voltage power supply chip leads to output voltage overshoot during light-load shutdown due to the slow internal feedback speed of the low-voltage power supply chip U1. This can easily cause damage to the load. Therefore, this application provides an enable circuit and a power supply circuit to avoid or reduce output voltage overshoot during shutdown, thereby protecting the load.

[0031] Please see Figure 3 The diagram shows a schematic of an enable circuit applied to a power supply circuit according to some embodiments of this application. In some embodiments, the enable circuit provided in this application is used to provide an enable signal to the enable terminal of the power supply chip. The enable circuit includes a transistor Q, a first voltage divider unit, and a second voltage divider unit. The current input terminal of transistor Q is connected to the voltage input terminal of the first voltage divider unit, the control terminal of transistor Q is connected to the voltage divider output terminal of the first voltage divider unit, and the current output terminal of transistor Q is connected to the voltage input terminal of the second voltage divider unit. The voltage input terminal of the first voltage divider unit is used to receive a first voltage V1, and the voltage divider output terminal of the second voltage divider unit is used to output an enable signal VEN to the enable terminal of the power supply chip.

[0032] The enable circuit provided in this application uses the switching on and off of transistors to control the switching between the voltage input terminals of the first voltage divider unit and the second voltage divider unit. By reasonably setting the voltage division parameters of the second voltage divider unit, when the first voltage drops to the first threshold, the value of the enable signal VEN output by the voltage divider output terminal of the second voltage divider unit is pulled down to less than the second threshold, thereby preventing the power chip from continuing to work and effectively avoiding or reducing the output overshoot phenomenon that occurs when the power chip is turned off.

[0033] Please continue reading. Figure 1 As shown, in some embodiments, transistor Q is a PMOS transistor. The current input terminal of transistor Q is the source terminal of the PMOS transistor, the control terminal of transistor Q is the gate terminal of the PMOS transistor, and the current output terminal of transistor Q is the drain terminal of the PMOS transistor. Using a PMOS transistor to control the switching between the voltage input terminals of the first and second voltage divider units allows for better placement of the power supply circuit on the PCB due to the smaller package size of the PMOS transistor.

[0034] Please continue reading. Figure 3As shown, in some embodiments, the first voltage divider unit is a first resistor voltage divider, which includes a first resistor R21 and a second resistor R22. The first end of the first resistor R21 is the voltage input terminal of the first voltage divider unit, and the second end of the first resistor R21 is the voltage divider output terminal of the first voltage divider unit. The first end of the second resistor R22 is connected to the second end of the first resistor R21, and the second end of the second resistor R22 is grounded. The first resistor voltage divider divides the first voltage V1 of the input enable circuit and outputs the divided voltage to the control terminal of transistor Q. By reasonably setting the resistance values ​​of the first resistor R21 and the second resistor R22, transistor Q can be controlled to be in the conducting state until the first voltage V1 drops to a third threshold value, where the third threshold value is less than the first threshold value.

[0035] Continue reading Figure 3 As shown, in some embodiments, to facilitate adjustment of the voltage division parameters of the second voltage divider unit, the second voltage divider unit is a second resistive voltage divider, which includes a third resistor R23 and a fourth resistor R24. The first terminal of the third resistor R23 is the voltage input terminal of the second voltage divider unit, and the second terminal of the third resistor R23 is the voltage output terminal of the second voltage divider unit. The first terminal of the fourth resistor R24 ​​is connected to the second terminal of the third resistor R23, and the second terminal of the fourth resistor R24 ​​is grounded. The voltage division parameters of the second voltage divider unit include the resistance values ​​of the third resistor R23 and the fourth resistor R24. By reasonably setting the resistance values ​​of the third resistor R23 and the fourth resistor R24, when the first voltage V1 drops to a first threshold, the enable signal VEN is pulled down to less than a second threshold, so as to control the power chip to stop output during the power-down period of the first voltage V1, effectively avoiding the phenomenon of output voltage overshoot.

[0036] In some embodiments, transistor Q is a PMOS transistor with a Zener diode between its source and drain. The cathode of the Zener diode is connected to the drain terminal of the PMOS transistor, and the anode is connected to the source terminal of the PMOS transistor. PMOS transistors with Zener diodes have higher stability.

[0037] Please continue reading. Figure 3 As shown, in some embodiments, the enabling circuit provided in this application further includes a first capacitor C21 connected to the voltage input terminal of the first voltage divider unit. Specifically, the first terminal of the first capacitor C21 is connected to the voltage input terminal of the first voltage divider unit to receive the first voltage VI, and the second terminal of the first capacitor C21 is grounded. The first capacitor C21 is used to support the first voltage to improve the stability of the enabling circuit.

[0038] Please see Figure 4The diagram shows a schematic of a power supply circuit provided according to some embodiments of this application. In some embodiments, the power supply circuit provided by this application includes a power chip U2 and an enable circuit provided according to any embodiment of this application. The enable circuit is used to output an enable signal VEN to the enable terminal EN2 of the power chip U2, that is, the voltage divider output terminal of the second voltage divider unit is connected to the enable terminal EN2 of the power chip U2. The enable circuit provided in the embodiments of this application can output an enable signal VEN that can control the power chip U2 to stop outputting when the load powered by the power supply circuit is turned off, so as to avoid or reduce the phenomenon of output voltage overshoot of the power chip U2 during the power-off period, thereby effectively realizing the power-off protection of the load. Specifically, as shown below... Figure 5 As shown, it is Figure 4 The waveform diagram of the power supply circuit shown clearly indicates that during the power-off period of the first voltage V1, the enable signal VEN is pulled low enough to no longer enable the power chip U2 to operate, and the power chip U2 stops outputting voltage. Therefore, the output of the power chip U2 will also drop after the first voltage V1 is lost, and will not exhibit the same behavior as before. Figure 2 The overshoot phenomenon shown can effectively prevent the load from being damaged due to power failure.

[0039] Please continue reading. Figure 4 As shown, in some embodiments, the power supply circuit provided in this application further includes a second capacitor C22. The first terminal of the second capacitor C22 is connected to the voltage input terminal IN2 of the power chip U2, and the second terminal of the second capacitor C22 is grounded. The second capacitor C22 is used to provide a stable input voltage, i.e., a second voltage V2, for the power chip U2.

[0040] The voltage input terminal IN2 of the power chip U2 is used to receive the second voltage V2. The power chip U2 converts the second voltage V2 into a supply voltage VOUT2. The supply voltage VOUT2 is output to the load via the voltage output terminal OUT2 of the power chip U2 to power the load. Specifically, the power chip U2 is a low dropout linear regulator chip, i.e., an LDO chip, used to output a fixed supply voltage to the load. The load powered by the power circuit provided in this embodiment can be a chip such as an MCU or an FPGA.

[0041] Continue reading Figure 4As shown, in some embodiments, the power supply circuit further includes a third capacitor C23, which is connected to the feedback terminal BP2 / FB2 of the power chip U2. The third capacitor can be a ceramic capacitor. Further, the power supply circuit also includes at least one fourth capacitor, with its first terminal connected to the voltage output terminal OUT2 of the power chip, and its second terminal grounded. The fourth capacitor may include, but is not limited to, capacitors C24, C25, C26, and C27. Specifically, capacitors C24, C25, and C26 are ceramic capacitors with the same capacitance value, and capacitor C27 is a decoupling ceramic capacitor with a capacitance value greater than that of capacitors C24, C25, and C26. The placement of the fourth capacitor at the voltage output terminal OUT2 of the power chip U2 helps improve the stability of the power supply circuit's power supply to the load.

[0042] according to Figure 2 The waveform diagram shows that when the 5V voltage VI N1 input to the input pin IN1 of the low-voltage power chip U1 drops to 1.96V, the 1.2V voltage output by the low-voltage power chip U1 experiences an overshoot. Therefore, in the enable circuit and power supply circuit provided in this embodiment, the first threshold can be set to 1.96V. By reasonably setting the voltage division parameters of the second voltage divider unit, when the first voltage V1 drops to near the time point corresponding to 1.96V, the enable signal VEN output by the voltage divider output terminal of the second voltage divider unit follows the drop of the first voltage V1 and is pulled down to less than the second threshold, thereby causing the power chip U2 to stop working, that is, achieving the purpose of the power chip U2 not working and not outputting voltage at this time, and the phenomenon of its output voltage overshoot naturally disappears.

[0043] In the power supply circuit provided in some embodiments of this application, the drain terminal of the PMOS transistor and the enable terminal EN2 of the power chip U2 are divided by two resistors. By reasonably setting the parameters of these two resistors, such as setting the resistance of the third resistor R23 to 10K and the resistance of the fourth resistor R24 ​​to 6.49K, when the source voltage (first voltage V1) of the PMOS transistor drops from 5V to 1.96V, the voltage of the enable signal VEN input to the enable terminal EN2 of the power chip U2 drops to about 0.3V. When the voltage of the enable terminal EN2 of the power chip U2 is lower than 0.3V, the power chip U2 stops working and will not output voltage, effectively eliminating the source of overshoot.

[0044] In some embodiments, the power supply circuit provided in this application is used to power the core module of the MCU, the core module having a power supply range of 1.0V to 1.2V. The power chip U2 specifically uses a fixed output 1.2V LDO chip with a maximum output current of 300mA and an input of 3.3V. The value of the enable signal is controlled by adding a PMOS transistor to the enable circuit connected to the enable terminal EN2. The source terminal of the PMOS transistor receives a first voltage V1 of 5V, and the drain terminal is connected to a 10K third resistor, which is connected to the enable terminal EN2 via the third resistor R23. The enable terminal is also connected to a 6.49K fourth resistor R24 ​​pulled down to ground. A 1K first resistor R21 is connected between the gate and source of the PMOS transistor, and the gate terminal of the PMOS transistor is connected to a 470R second resistor R22 pulled down to ground. Upon power-on, a threshold voltage drop of 3.4V is formed between the gate and source of the PMOS transistor, allowing it to enter saturation conduction. The first 5V voltage, V1, then conducts to the enable terminal EN2, generating a 1.96V voltage drop across EN2. Since the maximum enable voltage of EN2 is 1.5V, the power supply chip U2 operates normally, outputting 1.2V to power the MCU. Upon power-off, when the first 5V voltage, V1, drops to 1.96V, the voltage drop across the enable terminal EN2 falls below 0.3V. The power supply chip U2 stops operating, outputting no voltage, and the output overshoot disappears.

[0045] In other embodiments, the power supply circuit provided in this application is used to power the signal processing chip. When power-off occurs, if the first voltage V1 drops to 2.5V, the 1.2V output of the power chip U2 will overshoot. Then, the third resistor between the drain terminal of the PMOS transistor and the enable terminal EN2 will be adjusted to 11K and the fourth resistor R24 ​​will be adjusted to 1.5K. At this time, the voltage at the enable terminal EN2 will be 0.3V. When the first voltage V1 drops further, the voltage at the enable terminal EN2 will be lower than 0.3V, which is lower than the minimum enable operating voltage. Then, the power chip U2 will not work and will not output voltage, thus preventing overshoot.

[0046] In some embodiments, the power supply circuit provided in this application can also serve as a primary power supply for a low-power board, converting a 24V input voltage into a 5V output voltage. Specifically, the power supply circuit topology is a BUCK-type structure, meaning the power chip U2 is a step-down power chip. When power-off occurs, if the first voltage V1 drops to 3.5V, the 5V output voltage of the power chip U2 will overshoot. Therefore, the third resistor will be adjusted to 11K and the fourth resistor to 1K. At this time, the voltage at the enable terminal EN2 will be 0.292V. When the first voltage V1 continues to drop below 3.5V, the voltage at the enable terminal EN2 will be below 0.3V, which is below the minimum enable operating voltage. Therefore, the power chip U2 will not operate and will not output voltage, thus preventing output overshoot.

[0047] As can be seen from the above, the power supply circuit provided in this application embodiment has at least the following beneficial effects:

[0048] 1. The operating state of the power supply chip U2 is controlled by a PMOS transistor, resulting in low cost;

[0049] 2. The power chip U2 can be turned on or off by using a resistor voltage divider to adjust the power chip U2 according to the power-off overshoot time of different power chips, which is convenient for adjustment;

[0050] 3. The smaller package size of the PMOS transistor allows the PMOS transistor and its surrounding components to be placed closer to the power chip U2, making the PCB layout of the power circuit more flexible.

[0051] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An enabling circuit, characterized in that, Includes transistors, a first voltage divider unit, and a second voltage divider unit; The current input terminal of the transistor is connected to the voltage input terminal of the first voltage divider unit, the control terminal of the transistor is connected to the voltage divider output terminal of the first voltage divider unit, and the current output terminal of the transistor is connected to the voltage input terminal of the second voltage divider unit. The voltage input terminal of the first voltage divider unit is used to receive the first voltage, and the voltage output terminal of the second voltage divider unit is used to output an enable signal to the enable terminal of the power chip.

2. The enabling circuit according to claim 1, characterized in that, The transistor is a PMOS transistor, the current input terminal of the transistor is the source terminal of the PMOS transistor, the control terminal of the transistor is the gate terminal of the PMOS transistor, and the current output terminal of the transistor is the drain terminal of the PMOS transistor.

3. The enabling circuit according to claim 1, characterized in that, The first voltage divider unit includes a first resistor and a second resistor. The first end of the first resistor is the voltage input terminal of the first voltage divider unit, and the second end of the first resistor is the voltage output terminal of the first voltage divider unit. The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded.

4. The enabling circuit according to claim 1, characterized in that, The second voltage divider unit includes a third resistor and a fourth resistor. The first end of the third resistor is the voltage input terminal of the second voltage divider unit, the second end of the third resistor is the voltage divider output terminal of the second voltage divider unit, the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is grounded.

5. The enabling circuit according to any one of claims 1 to 4, characterized in that, It also includes a first capacitor, the first end of which is connected to the voltage input terminal of the first voltage divider unit, and the second end of which is grounded.

6. A power supply circuit, characterized in that, Includes a power supply chip and an enable circuit as described in any one of claims 1 to 5; The enabling circuit is connected to the enabling terminal of the power chip and is used to output an enabling signal to the enabling terminal of the power chip.

7. The power supply circuit according to claim 6, characterized in that, It also includes a second capacitor, the first end of which is connected to the voltage input terminal of the power chip, and the second end of which is grounded; The power chip has a voltage input terminal for receiving a second voltage, which is then converted into a supply voltage. The supply voltage is output to the load via the power chip's voltage output terminal to supply power to the load.

8. The power supply circuit according to claim 6, characterized in that, It also includes a third capacitor, the first end of which is connected to the feedback terminal of the power chip, and the second end of which is grounded.

9. The power supply circuit according to any one of claims 6 to 8, characterized in that, It also includes at least one fourth capacitor, the first end of which is connected to the voltage output terminal of the power chip, and the second end of which is grounded.

10. The power supply circuit according to any one of claims 6 to 8, characterized in that, The power supply chip is a low-dropout linear regulator chip.

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