Impact current suppression circuit meeting DO-160G standard

Abstract

The utility model provides the impulse current suppression circuit which meets the DO-160G standard. The resistor R1 and the resistor R2 are sequentially connected in series between the positive input end and the negative input end of the direct-current voltage source, and the resistor R1, the capacitor C1 and the diode V2 are connected in parallel. The source electrode of the MOS tube V1 is connected with the positive input end of the direct-current voltage source, the grid electrode is connected with the negative input end and the negative output end of the direct-current voltage source, and the drain electrode is connected with the positive output end of the direct-current voltage source. The diode V3 is connected with the resistor R2 in parallel, the negative electrode end of the diode V3 is connected with the positive electrode end of the diode V2, and the positive electrode end of the diode V3 and the negative electrode input end and the negative electrode output end of the direct-current voltage source are in common ground. According to the utility model, an impact current test condition 1 in a DO-160G standard can be met, an impact current test condition 2 can also be met, the impact current at the starting moment of equipment can be reduced, possible interference to adjacent circuits can be reduced, the pressure of an aircraft power supply system can be reduced, and the safety of the equipment can be effectively improved.

Description

Technical Field

[0001] This utility model belongs to the field of inrush current suppression technology, specifically relating to an inrush current suppression circuit that meets the DO-160G standard. Background Technology

[0002] Electronic products typically have filters and DC / DC converters installed at their input terminals. These devices usually contain a large number of capacitors. When the external power is turned on, these capacitors require a large current to charge to a steady state. The current spike generated at startup is the inrush current. Excessively high current spikes can interfere with adjacent circuits, triggering overcurrent protection and causing the upstream fuse to blow.

[0003] The requirements for inrush current are clearly defined in the Environmental Conditions and Test Procedures for Airborne Equipment of Civil Aircraft (DO-160G). The inrush current test requirements in DO-160G are as follows (under 28V power supply conditions):

[0004] Test conditions 1: a) Keep the power supply to the test device off for at least 5 minutes; b) Provide the test device with a 28V DC power supply, and the power rise time should be less than 300μs.

[0005] Test conditions 2: a) Reduce the input voltage of the device under test to 1.4V for 200ms; b) Apply a 28V voltage to the device under test.

[0006] The pass / fail criterion is: the peak value of the generated inrush current should be less than: a) 9 times the maximum steady-state load current in the first 3.0ms; b) 4 times the maximum steady-state load current from 3.0ms to 500ms; c) 2 times the maximum steady-state load current from 500ms to 2s, and then normal.

[0007] Most existing inrush current suppression circuits can meet test condition 1, but not test condition 2. For example, such as Figure 2 In the circuit shown, to reduce power consumption, the resistance value of R2 is chosen to be as large as possible. At the same time, when the external input power is off, the discharge of capacitor C1 needs to pass through resistor R2. Therefore, when the power is off, the discharge of capacitor C1 has a delay and the discharge process is relatively long. If the voltage across capacitor C1 is not discharged to the complete pinch-off voltage between the gate and source of the MOSFET during the 200ms power-off process, then when the external power is restarted and a 28V voltage is applied, the MOSFET will not operate in the variable resistance region, the suppression circuit will not be effective, and the inrush current suppression effect cannot be achieved. Utility Model Content

[0008] The purpose of this invention is to solve the problem that the existing surge current suppression circuits cannot meet the surge current test condition 2 in the DO-160G standard and thus cannot achieve the surge current suppression effect, and to provide a surge current suppression circuit that meets the DO-160G standard.

[0009] To achieve the above objectives, the technical solution provided by this utility model is as follows:

[0010] An inrush current suppression circuit that meets the DO-160G standard includes resistors R1 and R2, capacitor C1, P-channel MOSFET V1, and diodes V2 and V3.

[0011] Resistors R1 and R2 are connected in series between the positive and negative input terminals of the DC voltage source, and resistor R1, capacitor C1, and diode V2 are connected in parallel.

[0012] The source of MOSFET V1 is connected to the positive input terminal of a DC voltage source, the gate is connected to the negative input and negative output terminals of the DC voltage source, and the drain is connected to the positive output terminal of the DC voltage source.

[0013] Diode V3 is connected in parallel with resistor R2, and the negative terminal of diode V3 is connected to the positive terminal of diode V2. The positive terminal of diode V3, as well as the negative input and negative output terminals of the DC voltage source, share a common ground.

[0014] Furthermore, MOSFET V1 can be replaced with an N-channel MOSFET.

[0015] Furthermore, diode V2 is a Zener diode.

[0016] The advantages of this utility model are:

[0017] 1. The inrush current suppression circuit of this invention, which meets the DO-160G standard, incorporates a diode V3 that enables rapid discharge of capacitor C1 when the external input power is interrupted. In addition to meeting inrush current test condition 1 of the DO-160G standard, under inrush current test condition 2, when the power is interrupted, capacitor C1 can rapidly discharge through diode V3, allowing the voltage across capacitor C1 to reach the complete pinch-off voltage between the gate and source of the MOSFET within 200ms. This allows the MOSFET to quickly pinch off, and the circuit can function again after power is restored, meeting test condition 2 of the DO-160G standard. Therefore, this invention enables the equipment to meet the inrush current requirements of the DO-160G standard for civil aircraft environmental testing, reduces the inrush current at startup, reduces potential interference to adjacent circuits, reduces the pressure on the aircraft power supply system, and effectively improves equipment safety.

[0018] 2. The circuit uses a P-channel MOSFET. Compared to an N-channel MOSFET, an N-MOSFET needs to be connected in series with the negative power supply line. If the case ground of the product filter is connected to the 28V ground, when the product is powered on, there will be a path between the external power supply ground point and the case ground. This will cause the delay circuit where the MOSFET is located to be bypassed. This will cause the suppression circuit to be short-circuited by the case ground, and the suppression circuit will not be effective. This situation will not occur when using a P-channel MOSFET. Attached Figure Description

[0019] The above and / or other features and advantages of the present invention will become more readily understood from the following description with reference to the accompanying drawings, which are not drawn to scale and some features are enlarged or reduced to show details of specific parts.

[0020] Figure 1 This is a circuit diagram of the inrush current suppression circuit that meets the DO-160G standard of this utility model;

[0021] Figure 2 These are the test results without a suppression circuit;

[0022] Figure 3 The test results are for the case with a suppression circuit under impulse current test condition 1 in the DO-160G standard.

[0023] Figure 4 The results are from the test under impulse current test condition 2 in the DO-160G standard, with a suppression circuit. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and exemplary embodiments thereof. It should be noted that the following detailed description of the present invention is for illustrative purposes only and is not intended to limit the scope of the invention.

[0025] This invention provides an inrush current suppression circuit that meets the DO-160G standard. The circuit uses a MOSFET as its core and consists of the MOSFET and peripheral circuitry. It can be used in devices equipped with filters and DC / DC converters. Upon power-on, the circuit enables the device to start up slowly, allowing the capacitive load within the device to charge gradually, thus meeting the requirements of inrush current test conditions 1 and 2 in the DO-160G standard for civil aircraft environmental testing. This circuit requires no external drive circuitry; the product starts automatically upon power-on, with virtually no additional power consumption. Parameter settings can be flexibly adjusted according to different product designs, making it highly adaptable and inexpensive.

[0026] Reference Figure 1The surge current suppression circuit that meets the DO-160G standard, as an exemplary embodiment of this utility model, includes resistors R1 and R2, capacitor C1, MOSFET V1, and diodes V2 and V3.

[0027] Resistors R1 and R2 are connected in series between the positive and negative input terminals of the DC voltage source. Resistor R1, capacitor C1, and diode V2 are connected in parallel. Together, they form a delay circuit. When selecting the parameters for the voltage divider circuit composed of resistors R1 and R2, a resistor with a relatively large resistance value can be chosen to ensure that the gate voltage of the MOSFET reaches the turn-on state within the full operating voltage range of the product. Diode V2 can be a Zener diode; the Zener diode prevents overvoltage of the MOSFET gate voltage and protects the circuit. It can be selected to have a voltage higher than the normal operating voltage but lower than Ugsmax.

[0028] When selecting the parameters of the delay circuit composed of R2 and C1, the values ​​of C1 and R2 are adjusted using the following formula to adjust the time for the suppression circuit to fully start:

[0029] t=R2C1×ln[U C / (U C -U GS(th) )]

[0030] In the formula, U C and U GS(th) U represents the voltage across capacitor C1 and the gate threshold voltage, respectively. GS(th) Take the minimum value; C1 and R2 represent the capacitance value of C1 and the resistance value of R2, respectively. The values ​​of R1, R2, and C1 should be considered comprehensively when selecting them. When selecting the V2 Zener diode, the clamping voltage should be less than the maximum withstand voltage between the gate and source terminals of the MOSFET.

[0031] In this invention, when selecting the type and parameters of the MOSFET, it is necessary to consider that the MOSFET's UdsMAX must be greater than the input voltage Vin, and similarly, IdsMAX must be greater than the maximum operating current Iin. Furthermore, the smaller Rds(on) is, the lower the circuit loss during operation. When using a P-MOSFET, it needs to be connected in series to the positive power supply line. When using an N-MOSFET, it is connected in series to the negative power supply line. Reference materials show that the on-resistance of an N-MOSFET is generally smaller than that of a P-MOSFET. When using an N-MOSFET on the negative power supply line, it is necessary to ensure that there are no other loops besides the one where the N-MOSFET is located. If there is a path between the primary ground and the case ground, and the primary ground at the power supply terminal is also connected to the case ground, the delay circuit containing the N-MOSFET is bypassed. If the primary ground at the rear is insulated from the case ground, a switch can be used on the negative line.

[0032] Therefore, a P-channel MOSFET is preferably selected for V1. In this case, the source of MOSFET V1 is connected to the positive input terminal of the DC voltage source, the gate is connected to the negative input and negative output terminals of the DC voltage source, and the drain is connected to the positive output terminal of the DC voltage source. However, an N-channel MOSFET can also be used as an alternative. But when using an N-MOSFET, it needs to be connected in series on the negative power supply line. If the case ground at the front end of the product's filter is connected to the 28V ground, when the product is powered on, there will be a path between the external power supply ground point and the case ground, causing the delay circuit containing the MOSFET to bypass. This will cause the suppression circuit to be short-circuited by the case ground, rendering the suppression circuit ineffective. This situation does not occur with a P-channel MOSFET. In practical applications, the appropriate MOSFET can be selected based on the circuit requirements.

[0033] Diode V3 is connected in parallel with resistor R2, and the negative terminal of diode V3 is connected to the positive terminal of diode V2. The positive terminal of diode V3, as well as the negative input and negative output terminals of the DC voltage source, share a common ground. The function of diode V3 is to allow capacitor C1 to discharge quickly when the power is off. V3 is optional; its installation is selected based on the actual capacitor discharge time to meet the requirements of DO-160G test condition 2.

[0034] The working principle of the circuit provided by this utility model is as follows: When the external power supply is suddenly turned on, the voltage between the gate and source of the MOSFET is slowly increased by the delay circuit composed of R1, R2, and C1. Since the MOSFET itself is characterized by the voltage between Ugs controlling the current between Ids, the drain current Ids increases almost linearly with the increase of the gate voltage Ugs. By controlling the change in the Ugs voltage, the current flowing through the drain is controlled. The settling time of the MOSFET gate input voltage allows the field-effect transistor to operate in the variable resistance region for a period of time, thereby reducing the path impedance and controlling the charging current of the input filter capacitor, thus suppressing the inrush current.

[0035] This inrush current suppression circuit, in addition to meeting inrush current test condition 1 of the DO-160G standard, also meets inrush current test condition 2 of the DO-160G standard. When the power is off, capacitor C1 can discharge rapidly through diode V3, allowing the voltage across capacitor C1 to reach the complete pinch-off voltage between the gate and source of the MOSFET within 200ms. This allows the MOSFET to quickly pinch off, and the circuit can function again after power is restored, meeting test condition 2 of the DO-160G standard. Therefore, this invention enables the equipment to meet the inrush current requirements of the DO-160G standard for civil aircraft environmental testing, reduces the inrush current at startup, reduces potential interference to adjacent circuits, reduces the pressure on the aircraft power supply system, and effectively improves the safety of the equipment.

[0036] The following section provides a further explanation of the inrush current suppression circuit that meets the DO-160G standard provided by this invention, using examples.

[0037] In this example, the current clamp is set to 100mV / A. When the current clamp outputs 100mV, it means that the detected current is 1A, and the maximum steady-state load current is known to be approximately 0.35A.

[0038] Reference Figure 2 The blue line represents the external input / output voltage, and the yellow line represents the inrush current at startup. Without any suppression circuit, the startup current exceeds the measurement range of the oscilloscope.

[0039] Reference Figure 3 and Figure 4 After adding the surge current suppression circuit of this utility model to the front end of the device, the blue line represents the external input voltage, and the yellow line represents the surge current at startup. The test is conducted according to the DO-160G test method: Under test condition 1, the surge current peak appears about 125ms after the external power supply starts, and the peak surge current is about 0.7A, which meets the requirement of being less than 4 times the maximum steady-state load current within 3.0ms to 500ms, and less than 9 times the steady-state load current within 3ms, less than 2 times the maximum steady-state load current within 500ms to 2s, and the steady-state current has recovered after more than 2s; Under test condition 2, the surge current peak appears about 124ms after the external power supply restarts, and the peak surge current is about 0.5A, which meets the requirement of being less than 4 times the maximum steady-state load current within 3.0ms to 500ms, and less than 9 times the steady-state load current within 3ms, less than 2 times the maximum steady-state load current within 500ms to 2s, and the steady-state current has recovered after more than 2s.

[0040] As can be seen from the results of this example, the surge current suppression circuit provided by this utility model can not only meet the surge current test condition 1 in the DO-160G standard, but also the surge current test condition 2 in the DO-160G standard, thus verifying the effectiveness of the circuit provided by this utility model.

[0041] Finally, it should be noted that the features mentioned and / or shown in the above description of exemplary embodiments of the present invention can be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. These combined or substituted technical solutions should also be considered as included within the protection scope of the present invention.

Claims

1. An inrush current suppression circuit that meets the DO-160G standard, characterized in that: This includes resistors R1 and R2, capacitor C1, P-channel MOSFET V1, and diodes V2 and V3; The resistors R1 and R2 are connected in series between the positive and negative input terminals of the DC voltage source, and the resistor R1, capacitor C1, and diode V2 are connected in parallel. The source of the MOS transistor V1 is connected to the positive input terminal of the DC voltage source, the gate is connected to the negative input terminal and the negative output terminal of the DC voltage source, and the drain is connected to the positive output terminal of the DC voltage source. The diode V3 is connected in parallel with the resistor R2, and the negative terminal of the diode V3 is connected to the positive terminal of the diode V2. The positive terminal of the diode V3, the negative input terminal and the negative output terminal of the DC voltage source are grounded together.

2. The surge current suppression circuit conforming to the DO-160G standard according to claim 1, characterized in that: The MOSFET V1 can be replaced with an N-channel MOSFET.

3. The surge current suppression circuit conforming to the DO-160G standard according to claim 1, characterized in that: The diode V2 is a Zener diode.

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