Driving circuit of field effect transistor and power supply driving circuit

Abstract

The utility model provides a field effect transistor driving circuit and a power supply driving circuit, and relates to the technical field of circuit design. The drive circuit of the field effect transistor comprises a PWM signal input circuit, a voltage division bias circuit and a first field effect transistor, the semiconductor layer of the first field effect transistor comprises gallium nitride; the input end of the PWM signal input circuit is electrically connected with a PWM signal end, and the output end of the PWM signal input circuit is electrically connected with the input end of the voltage division biasing circuit; the output end of the voltage division biasing circuit is electrically connected with the grid electrode of the first field effect transistor, and the voltage division biasing circuit is used for converting the voltage amplitude of the PWM signal into the turn-on voltage of the first field effect transistor so that the first field effect transistor can be turned on. The voltage division biasing circuit outputs appropriate voltage to drive the first field effect transistor, the problems that in the prior art, a special IC chip needs to be used for driving a gallium nitride field effect transistor, cost is high, and the size is large are solved, and the size and price of a product are effectively reduced.

Description

Technical Field

[0001] This application relates to the technical field of circuit design, and more specifically, to a driving circuit and a power supply driving circuit for a field-effect transistor. Background Technology

[0002] Gallium nitride (GaN) field-effect transistors are a type of field-effect transistor based on gallium nitride and aluminum gallium nitride. Due to the excellent heat dissipation, high breakdown electric field, and high saturation velocity of gallium nitride, GaN field-effect transistors have promising applications in high-power, high-frequency energy conversion and high-frequency microwave communication.

[0003] Currently, mainstream gallium nitride field-effect transistors require dedicated IC chips to drive them. However, dedicated IC chips are expensive and have limited selection, resulting in high product costs. Utility Model Content

[0004] This application addresses the shortcomings of existing methods by proposing a driving circuit and a power supply driving circuit for a field-effect transistor (FET), thereby solving the technical problem that related technologies require dedicated IC chips to drive the FET, resulting in high costs.

[0005] In a first aspect, this application provides a driving circuit for a field-effect transistor, comprising:

[0006] The circuit includes a PWM signal input circuit, a voltage divider bias circuit, and a first field-effect transistor; the semiconductor layer of the first field-effect transistor includes gallium nitride.

[0007] The PWM signal input circuit has its input terminal electrically connected to the PWM signal terminal and its output terminal electrically connected to the input terminal of the voltage divider bias circuit.

[0008] The output terminal of the voltage divider bias circuit is electrically connected to the gate of the first field-effect transistor, and is used to convert the voltage amplitude of the PWM signal into the turn-on voltage of the first field-effect transistor, so that the first field-effect transistor is turned on.

[0009] In one possible implementation, the PWM signal input circuit includes a ferrite bead, the first end of which serves as the input terminal of the PWM signal input circuit and is electrically connected to the PWM signal terminal.

[0010] In one possible implementation, the PWM signal input circuit further includes: an adjustment module, which includes a first diode, a first resistor, and a second resistor;

[0011] The negative terminal of the first diode and the first end of the second resistor together serve as the input terminal of the adjustment module, and are electrically connected to the second end of the magnetic bead;

[0012] The second end of the first resistor and the second end of the second resistor together serve as the output terminal of the adjustment module, and are electrically connected to the input terminal of the voltage divider bias circuit.

[0013] In one possible implementation, the voltage divider bias circuit specifically includes: a third resistor and a fourth resistor;

[0014] The first end of the third resistor serves as the input terminal of the voltage divider bias circuit and is electrically connected to the PWM signal terminal through the PWM signal input circuit; the second end of the third resistor and the first end of the fourth resistor together serve as the output terminal of the voltage divider bias circuit and are electrically connected to the gate of the first field-effect transistor; the source of the first field-effect transistor is grounded.

[0015] The second terminal of the fourth resistor is grounded.

[0016] In one possible implementation, the driving circuit further includes: a boost module, the boost module including a first capacitor;

[0017] The first terminal of the first capacitor serves as the input terminal of the boost module and is electrically connected to the output terminal of the PWM signal input circuit.

[0018] The second terminal of the first capacitor serves as the output terminal of the boost module and is electrically connected to the gate of the first field-effect transistor.

[0019] In one possible implementation, the driving circuit further includes: a voltage regulator module, the voltage regulator module including a first Zener diode;

[0020] The negative terminal of the first Zener diode serves as the input terminal of the voltage regulator module and is electrically connected to the gate of the first field-effect transistor.

[0021] The positive terminal of the first Zener diode is grounded as the output terminal of the voltage regulator module.

[0022] In one possible implementation, the driving circuit further includes: a first inductor and a second capacitor;

[0023] Wherein, the first end of the first inductor and the first end of the second capacitor are electrically connected to the VIN+ terminal, and the second end of the first inductor is electrically connected to the drain of the first field-effect transistor.

[0024] The second terminal of the second capacitor is grounded.

[0025] Secondly, this application provides a power supply drive circuit, comprising: a defogging film control circuit, an EMI filter circuit, a transformer circuit, a VCC power supply circuit, an output rectifier filter circuit, a signal feedback circuit, and an over-temperature protection circuit. The defogging film control circuit is electrically connected to the EMI filter circuit, the transformer circuit is electrically connected to the output rectifier filter circuit, the VCC power supply circuit is electrically connected to the transformer circuit, and the output rectifier filter circuit is electrically connected to the signal feedback circuit. The power supply drive circuit further comprises: a PFC boost circuit, a PWM pulse width modulation circuit, and a rectifier filter circuit.

[0026] The PFC boost circuit includes a driving circuit for a field-effect transistor as described in any one of the first aspects, and the PFC boost circuit is electrically connected to the power supply driving circuit; the PWM pulse width modulation circuit is electrically connected to the power supply driving circuit; and the power supply driving circuit is electrically connected to the rectifier filter circuit.

[0027] In one possible implementation, the PFC boost circuit is electrically connected to the power supply drive circuit; the PWM pulse width modulation circuit is electrically connected to the power supply drive circuit; and the power supply drive circuit is electrically connected to the rectifier filter circuit; comprising:

[0028] The rectifier filter circuit, the PFC boost circuit, and the PWM pulse width modulation circuit are electrically connected in sequence. The PWM pulse width modulation circuit, the VCC power supply circuit, and the transformer circuit are electrically connected in pairs. The signal feedback circuit and the PWM pulse width modulation circuit are connected by optocoupler.

[0029] In one possible implementation, the PWM pulse width modulation circuit includes: a PWM pulse width modulation chip;

[0030] The PWM pulse width modulation chip includes a PG pin, which is used to output a PWM signal to the driving circuit.

[0031] The beneficial technical effects of the technical solution provided in this application include:

[0032] This application provides a driving circuit and a power supply driving circuit for a field-effect transistor. This application uses a voltage divider bias circuit to output a suitable voltage to drive the gallium nitride field-effect transistor, which solves the problems of high cost and large size caused by the need to use a dedicated IC chip to drive the gallium nitride field-effect transistor in the prior art, and effectively reduces the size and price of the product.

[0033] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0034] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0035] Figure 1 A circuit diagram of a field-effect transistor driving circuit provided in this application;

[0036] Figure 2 A circuit diagram of a power supply drive circuit provided in this application;

[0037] Figure 3 A circuit diagram of an EMI filter circuit provided in this application;

[0038] Figure 4 A circuit diagram of a rectifier filter circuit provided in this application;

[0039] Figure 5 A circuit diagram of a PFC boost circuit provided in this application;

[0040] Figure 6 A circuit diagram of a PWM pulse width modulation circuit provided in this application;

[0041] Figure 7 A circuit diagram of a transformer circuit provided in this application;

[0042] Figure 8 A circuit diagram of an output rectifier and filter circuit provided in this application;

[0043] Figure 9 A circuit diagram of a signal feedback circuit provided in this application;

[0044] Figure 10 A circuit diagram of a VCC power supply circuit provided in this application;

[0045] Figure 11 An over-temperature protection circuit is provided in this application;

[0046] Figure 12 A circuit diagram of a defogging film control circuit provided in this application;

[0047] Figure label:

[0048] 1-EMI filter circuit; 2-rectifier filter circuit; 3-PFC boost circuit; 4-PWM pulse width modulation circuit; 5-transformer circuit; 6-output rectifier filter circuit; 7-signal feedback circuit; 8-VCC power supply circuit; 9-over-temperature protection circuit; 10-demisting film control circuit.

[0049] 110 - PWM signal input circuit; 120 - Voltage divider bias circuit;

[0050] 111-Regulation module; 112-Boost module; 113-Voltage stabilizing module. Detailed Implementation

[0051] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0052] Those skilled in the art will understand that, unless specifically stated otherwise, the terms “comprising” and “the” used herein may also include plural forms. It should be further understood that the term “comprising” as used in the specification of this application means the presence of features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. It should be understood that when we say an element is “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein means at least one of the items defined by the term; for example, “A and / or B” may be implemented as “A”, or as “B”, or as “A and B”.

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0054] Research has revealed that mainstream gallium nitride field-effect transistors currently require dedicated IC chips to drive them. However, dedicated IC chips are expensive and have limited selection options, resulting in high product costs.

[0055] The field-effect transistor driving circuit and power supply driving circuit provided in this application are intended to solve the above-mentioned technical problems in related technologies.

[0056] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0057] Figure 1 A circuit diagram of a field-effect transistor driving circuit provided in this application is shown below. Figure 1As shown, it includes: a PWM signal input circuit 110, a voltage divider bias circuit 120, and a first field-effect transistor Q1 connected in sequence; wherein, the PWM signal input circuit 110 receives the PWM signal output by the PWM pulse width modulation circuit 4 and inputs the PWM signal to the voltage divider bias circuit 120; the voltage divider bias circuit 120 is used to adjust the voltage amplitude of the PWM signal and control the gate-source voltage of the first field-effect transistor Q1 to be greater than the turn-on voltage, so that the first field-effect transistor Q1 is in the turn-on state.

[0058] Its working principle is that this application uses a voltage divider bias circuit 120 to output a suitable voltage to drive the field-effect transistor, solving the problem in the prior art that a dedicated IC chip is required to drive gallium nitride field-effect transistors. Furthermore, in this application, the voltage divider bias circuit 120 uses a smaller, cheaper power device, effectively reducing the product's size and price, and improving its cost-effectiveness. It should be noted that in this application, the type of the first field-effect transistor Q1 includes, but is not limited to, gallium nitride field-effect transistors, and can be selected according to actual needs.

[0059] In some optional embodiments, the PWM signal input circuit 110 includes a ferrite bead B1, with a first end of the ferrite bead B1 disposed at the input end of the PWM signal input circuit 110, and the ferrite bead B1 is used to reduce the radiation of the received PWM signal.

[0060] In some optional embodiments, the PWM signal input circuit 110 further includes: an adjustment module 111, which includes a first diode D11, a first resistor R63, and a second resistor R26; wherein the cathode of the first diode D11 and the first terminal of the second resistor R26 are respectively the input terminals of the adjustment module 111; the second terminals of the first resistor R63 and the second terminal of the second resistor R26 are respectively the output terminals of the adjustment module 111; the input terminal of the adjustment module 111 is connected to the second terminal of the ferrite bead B1 to receive the PWM signal input through the ferrite bead B1, and the adjustment module 111 is used to control the switching speed of the first field-effect transistor and reduce the EMI of the PWM signal.

[0061] In some optional embodiments, the driving circuit of the field-effect transistor further includes: a boost module 130, which includes a first capacitor C38; wherein, the first terminal of the first capacitor C38 is the input terminal of the boost module 130, and the second terminal of the first capacitor C38 is set as the output terminal of the boost module 130; the input terminal of the boost module 130 is connected to the output terminal of the adjustment module 111, and the output terminal of the boost module 130 is connected to the gate of the first field-effect transistor; since the waveform of the PWM signal is pulsed, the rise from the reference voltage to the peak voltage (i.e., the rising edge of the pulse) and the fall from the peak voltage to the reference voltage (i.e., the falling edge of the pulse) are different in speed, the first capacitor C38 can narrow the rising and falling edges of the pulse waveform, thereby increasing the voltage of the gate of the first field-effect transistor Q1.

[0062] In some optional embodiments, the driving circuit of the field-effect transistor further includes: a voltage regulator module 140, which includes a first Zener diode D19; wherein the cathode of the first Zener diode D19 is set as the input terminal of the voltage regulator module 140 and connected to the gate of the first field-effect transistor Q1; the anode of the first Zener diode D19 is set as the output terminal of the voltage regulator module 140; the input terminal of the voltage regulator module 140 is connected to the output terminal of the boost module 130, and the output terminal of the voltage regulator module 140 is grounded; the voltage regulator module 140 is used to control the driving voltage of the first field-effect transistor Q1 to not exceed the maximum gate voltage.

[0063] In some optional embodiments, the voltage divider bias circuit 120 includes a third resistor R27 and a fourth resistor R28. The voltage divider bias circuit 120 is used to adjust the gate voltage of the first field-effect transistor Q1 so that the gate-source voltage of the first field-effect transistor Q1 is greater than the turn-on voltage, thereby driving the first field-effect transistor Q1. The first terminal of the third resistor R27 is configured as the input terminal of the voltage divider bias circuit 120. The second terminal of the third resistor R27, the first terminal of the fourth resistor R28, and the gate of the first field-effect transistor Q1 are connected, and the source of the first field-effect transistor Q1 is grounded. The second terminal of the fourth resistor R28 is configured as the output terminal of the voltage divider bias circuit 120, and the output terminal is grounded. The third resistor R27 is connected in parallel with the first capacitor C38, and the fourth resistor R28 is connected in parallel with the first Zener diode D19.

[0064] In some optional embodiments, the driving circuit of the field-effect transistor further includes: a first inductor T1 and a second capacitor C26; wherein, the first terminal of the first inductor T1 and the first terminal of the second capacitor C26 are connected to the DC pulse voltage VIN+, and the second terminal of the first inductor T1 is connected to the drain of the first field-effect transistor Q1; the second terminal of the second capacitor C26 is grounded; the second capacitor is used to smooth and filter the DC pulse voltage VIN+ to obtain a DC voltage, which is used to power the driving circuit; the first inductor T1 is used to store the DC voltage and to power the driving circuit of the field-effect transistor when the DC pulse voltage drops.

[0065] like Figure 2-12 As shown, the power supply drive circuit includes: an EMI filter circuit 1, a rectifier filter circuit 2, a PFC boost circuit 3, a PWM pulse width modulation circuit 4, a transformer circuit 5, an output rectifier filter circuit 6, and a signal feedback circuit 7 connected in sequence. The PFC boost circuit 3 also includes a field-effect transistor drive circuit.

[0066] In some optional embodiments, the power supply drive circuit further includes: a VCC power supply circuit 8, an over-temperature protection circuit 9, and a demisting film control circuit 10; wherein, the VCC power supply circuit 8 is connected to the PWM pulse width modulation circuit 4 and is used to supply power to the PWM pulse width modulation circuit 4; the over-temperature protection circuit 9 is connected to the PWM pulse width modulation circuit 4 and is used to provide over-temperature protection for the PWM pulse width modulation circuit 4; and the demisting film control circuit 10 is connected to the EMI filter circuit 1.

[0067] In some optional embodiments, the PWM pulse width modulation circuit 4 includes: a PWM pulse width modulation chip U1; wherein the PWM pulse width modulation chip U1 includes a PGATE pin, which is used to output a PWM signal to the driving circuit of the field-effect transistor.

[0068] In this application, the EMI filter circuit 1, the rectifier filter circuit 2, the PFC boost circuit 3, the PWM pulse width modulation circuit 4, the transformer circuit 5, and the output rectifier filter circuit 6 are connected in sequence to form the PFC drive circuit. Based on the PFC drive circuit, a signal feedback module 7 is added to form a feedback loop. At the same time, the signal feedback circuit 7 detects the DC voltage output by the output rectifier filter circuit 6 and feeds the detection result back to the PWM pulse width modulation circuit 4 through the transmitter unit U3A of the optocoupler. The over-temperature protection circuit 9 is used to monitor the output voltage of the PWM pulse width modulation circuit 4 and provide over-temperature protection for the PWM pulse width modulation circuit 4.

[0069] Specifically, EMI filter circuit 1 is used to filter out high-frequency pulses from the external power grid that interfere with the power supply, and also reduces the electromagnetic interference emitted by the switching power supply itself. For example... Figure 3 As shown, the EMI filter circuit 1 includes: a fuse F1 connected in series, a capacitor C35 connected in parallel, a capacitor C4 connected in parallel, and a varistor VR1; common mode inductors LF1, LF2, and LF3 connected in series; resistors R1 and R12 connected in series, resistors R1 and R2 connected in parallel, and resistors R12 and R13 connected in parallel; wherein, the EMI filter circuit 1 also includes: AC output neutral line N1, AC input neutral line N, ground PE, and AC input live line L.

[0070] Specifically, the rectifier-filter circuit 2 is used to step down, rectify, and filter the AC power supply into a suitable DC voltage. For example... Figure 4As shown, the rectifier-filter circuit 2 includes: a rectifier DB1, capacitors C34, C7, and C8, a varistor VR2, a resistor R14, and an inductor L1; wherein, the first terminal of the rectifier DB1 is connected in series with the inductor L1 to output the positive terminal VIN+ of the DC pulse voltage; the second terminal of the rectifier DB1 is connected to the second output terminal of the EMI filter circuit 1; the third terminal of the rectifier DB1 is connected to the first output terminal of the EMI filter circuit 1; and the fourth terminal of the rectifier DB1 is connected to the negative terminal BUS- of the DC pulse voltage; the first terminal of capacitor C34 is connected to the PFC boost circuit 3; the second terminal of capacitor C34, the first terminal of varistor VR2, and the first terminal of capacitor C7 are connected to the first terminal of rectifier DB1; the second terminal of varistor VR2 and the second terminal of capacitor C7 are connected to the negative terminal BUS- of the DC pulse voltage; the first terminal of capacitor C8 is connected to the positive terminal VIN+ of the DC pulse voltage; and the second terminal of capacitor C8 is connected to the negative terminal BUS- of the DC pulse voltage; the resistor R14 is connected in parallel with the inductor L1.

[0071] Specifically, the PFC boost circuit 3 is used to perform power factor correction on the DC pulse voltage VIN+ output by the rectifier filter circuit 2, boosting it to output a stable and reliable DC voltage HV. For example... Figure 5 As shown, the PFC boost circuit 3, in addition to the MOSFET drive circuit, also includes: resistors R8~R10, resistors R23~R25, resistor R29, resistors R31~R33, resistor R35, resistors R54~R55, resistors R58~R59, a thermistor RT1, capacitors C5, C15, C17~C18, diodes D3~D4, diodes D6 and D12, and a ferrite bead FB; wherein, resistors R8, R24, and R25 are connected in series with capacitor C15, and capacitor C15 is connected in parallel with resistor R23; resistor R9 is connected in series with diode D3, and resistor R10 is connected in series with diode D4; the cathode of diode D3, the diode... The negative terminal of diode D4 and the first end of resistor R8 are connected; capacitor C5 is connected in series with resistor R11, and diode D12 is connected in series with ferrite bead FB; the positive terminal of diode D6 is connected to VIN+, the negative terminal of diode D6 is connected to the first end of capacitor C17, and the second end of capacitor C17 is grounded; the source of field-effect transistor Q1, resistor R54, and resistor R55 are connected in sequence; the first end of the thermistor is connected to ferrite bead FB, and the second end is connected to HV terminal; HV terminal, resistors R31, R32, and R33, and capacitor C18 are connected in sequence, and capacitor C18 is connected in parallel with resistor R30; resistors R35, R29, R58, and R59 are connected in parallel.

[0072] Specifically, the PWM pulse width modulation circuit 4 is used to control the input and output of the transformer circuit 5 based on the feedback signal collected from the feedback terminal. For example... Figure 6As shown, the PWM pulse width modulation circuit 4 includes a receiver U3B of an optocoupler. The receiver U3B of the optocoupler is connected to the transmitter U3A of the optocoupler in the signal feedback circuit 7. It is used to receive the optical signal sent by the transmitter U3A of the optocoupler and convert the optical signal into an electrical signal and send it to the pulse width modulation chip U1. This allows the pulse width modulation chip U1 to adjust the duty cycle of the PWM signal according to the received electrical signal, thereby ensuring the stability of the output voltage of the transformer T2.

[0073] Specifically, transformer circuit 5 is used to transform the DC voltage HV output from PFC boost circuit 3 into the operating voltage required by the load. For example... Figure 7 As shown, the transformer circuit 5 includes a first transformer T2, with a primary input and a secondary input, and a primary output and a secondary output. The primary input circuit of the first transformer T2 is connected to the PWM pulse width modulation circuit 4, and the secondary input circuit is connected to the VCC power supply circuit 8. The primary output circuit of the first transformer T2 is connected to the input of the output rectifier and filter circuit 6, and the secondary output circuit is connected to the VG1 and VG2 pins of the chip U2 in the output rectifier and filter circuit 6.

[0074] Specifically, the output rectifier filter circuit 6 uses a power MOSFET with extremely low resistance to replace the rectifier diode, thus greatly reducing rectifier losses, improving the efficiency of the DC / DC converter, and meeting the needs of low-voltage, high-current rectification. For example... Figure 8As shown, the output current filter circuit 6 includes a rectifier chip U2, capacitors C1~C3, capacitors C24, C37, and C41, resistors R3~R5, resistors R20, R22, and R48, LED1, diode D2, polarized capacitors C12~C14, and common-mode inductor LF4. The rectifier chip U2 includes pins 1~8: VG2, PGND, LL, VD2, VSS, VD1, VDD, and VG1. Pin VDD, the first terminal of capacitor C3, and the first terminal of resistor R7 are connected. The second terminal of capacitor C3 is connected to pin VSS and then grounded. Pins VG1 and VG2 output vg1 and vg2 respectively, and pins VD1 and VD2 output vd1 and vd2 respectively. The first terminal of capacitor C1 is connected to pin LL and the first terminal of resistor R5. The second terminal of capacitor C1, the second terminal of resistor R5, and pin PGND are grounded. The second terminal of resistor R7 is connected to... The first terminal of R20 is connected to: the first terminal of resistor R7, the first terminal of resistor R22, the first terminal of resistor R20, the positive terminals of polarized capacitors C12~C14, the first terminal of capacitor C41, the second terminal of resistor R6, the second terminal of resistor R48, the source of MOSFET Q5, and pin 7 of transformer T2 output are connected; the second terminal of resistor R22 is connected to the positive terminal of LED1; the negative terminal of LED1, the negative terminals of polarized capacitors C12~C14, the second terminal of resistor R20, and the first terminal of capacitor C37 are grounded; the first terminal of resistor R6 is connected to the second terminal of capacitor C2; the second terminal of resistor R3, the positive terminal of diode D2, and the first terminal of resistor R48 are connected to the gate of MOSFET Q5; the first terminal of resistor R3 and the negative terminal of capacitor C2 are connected to terminal Vg1; the second terminal of resistor R4, the first terminal of capacitor C2, the source of MOSFET Q5, and pin 6 of transformer T2 output are connected.

[0075] Specifically, the signal feedback circuit 7 is used to detect the signal output by the output rectifier and filter circuit 6, generate a feedback signal, and reliably transmit the feedback signal to the PWM pulse width modulation chip U1 through opto-isolation. For example... Figure 9As shown, the signal feedback circuit 7 includes an optocoupler transmitting unit U3A, resistors R21, R49~R50, R52, R56~R57, diode D10, capacitors C26~C27, and a reference voltage comparator U4. Resistor R21 is connected in series with the transmitting unit U3A of the optocoupler, and the transmitting unit U3A of the optocoupler is connected in parallel with resistor R52. Resistors R57 and R49 are connected in series, and the first terminal of the reference voltage comparator U4 is connected to the second terminal of resistor R49, the second terminal of resistor R56, and the second terminal of capacitor C26. Pin 2 of the reference voltage comparator U4 is connected to the first terminal of capacitor C27, and the second terminal of capacitor C27 is connected to the first terminal of resistor R56. Resistor R50 is connected in parallel between pins 1 and 3 of the reference voltage comparator U4, and pin 3 of the reference voltage comparator U4 is grounded.

[0076] In practical applications, an optical coupler (OC), also known as an opto-isolator or simply optocoupler, is a device that uses light as a medium to transmit electrical signals. It typically encapsulates a light emitter (infrared LED) and a light receiver (photosensitive semiconductor tube) within the same housing. When an electrical signal is applied to the emitting unit of the optocoupler, the light emitter emits light, and the receiving end receives this light, generating a photocurrent that flows out from the output terminal, thus achieving an "electrical-to-optical-to-electrical" conversion.

[0077] In this application, the reference voltage comparator U4 is used to detect the detection voltage V+ terminal output by the output rectifier filter circuit 6, and converts the electrical signal into an optical signal through the transmitting unit U3A of the optocoupler, and sends the optical signal to the receiving unit U3B of the optocoupler set in the PWM pulse width modulation circuit 4; the receiving unit U3B of the optocoupler then converts the received optical signal into an electrical signal, and feeds the electrical signal back to the PWM pulse width modulation chip U1, so that the PWM pulse width modulation chip U1 adjusts the duty cycle of the PWM signal to ensure the stability of the output voltage of the transformer T2.

[0078] Specifically, the VCC power supply circuit 8 and the secondary primary side of the transformer T2 input terminal form a loop to convert the DC voltage HV into the startup voltage VCC of the PWM pulse width modulation chip U1. For example... Figure 10As shown, the VCC power supply circuit 8 includes: diode D8, resistors R46~R47, polarized capacitors C25 and C33, capacitors C31 and C36, transistor Q4, Zener diode D1, and Schottky diode D15. The cathode of diode D8 is connected to the first terminal of resistor R46; the second terminal of resistor R46, the first terminal of resistor R47, and the anode of polarized capacitor C25 are connected to the collector of transistor Q4; the second terminal of resistor R47 and the cathode of Zener diode D1 are connected to the base of transistor Q4; the first terminal of capacitor C36 and the anode of Schottky diode D15 are connected to the emitter of transistor Q4; the anode of polarized capacitor C33 is connected to the cathode of Schottky diode D15; the cathode of polarized capacitor C25, the anode of Zener diode D1, the second terminal of capacitor C36, the cathode of polarized capacitor C33, and the first terminal of capacitor C31 are connected, and the second terminal of capacitor C31 is grounded.

[0079] Specifically, the over-temperature protection circuit 9 is connected to the VSEN pin of the pulse width modulation chip U1 to monitor the output voltage of the PWM pulse width modulation circuit 4 and provide temperature protection for the PWM pulse width modulation circuit 4. Figure 11 As shown, the over-temperature protection circuit 9 includes resistors R62 and R53, a varistor R61, and a diode D18; wherein, the positive terminal of the diode D18 is connected to the first terminal of the varistor R61 and the first terminal of R62, and the varistor R61 is connected in series with the resistor R53.

[0080] Specifically, the defogger control circuit 10 is used to control the heating process of the defogger film, thereby effectively removing fog or frost from the glass. For example... Figure 12 As shown, the defogging film control circuit 10 includes: a fuse F2, a silicon controlled rectifier (SCR) Q7, an AC output live wire L1, resistors R18 and R19, an optocoupler U5, a control switch for the defogging film ON / OFF, and a positive output terminal VOUT+. The first end of the fuse F2 is connected to the EMI filter circuit 1. The second end of the fuse F2, the first end of the SCR Q7, and the first end of the resistor R18 are connected. The second end of the SCR Q7 is connected to the AC output live wire L1. The third end of the SCR Q7 is connected to the first end of the receiving unit of the optocoupler U5. The second end of the resistor R18 is connected to the second end of the receiving unit of the optocoupler U5. The positive output terminal VOUT+ is connected to the first end of the transmitting unit of the optocoupler. The control switch for the defogging film ON / OFF is connected to the second end of the transmitting unit of the optocoupler U5.

[0081] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Moreover, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0082] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0083] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0084] The above are only some embodiments of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of this application.

Claims

1. A driving circuit for a field-effect transistor, characterized in that, include: The circuit includes a PWM signal input circuit, a voltage divider bias circuit, and a first field-effect transistor; the semiconductor layer of the first field-effect transistor includes gallium nitride. The PWM signal input circuit has its input terminal electrically connected to the PWM signal terminal and its output terminal electrically connected to the input terminal of the voltage divider bias circuit. The output terminal of the voltage divider bias circuit is electrically connected to the gate of the first field-effect transistor, and is used to convert the voltage amplitude of the PWM signal into the turn-on voltage of the first field-effect transistor, so that the first field-effect transistor is turned on.

2. The driving circuit for the field-effect transistor according to claim 1, characterized in that, The PWM signal input circuit includes a ferrite bead, the first end of which serves as the input terminal of the PWM signal input circuit and is electrically connected to the PWM signal terminal.

3. The driving circuit for the field-effect transistor according to claim 2, characterized in that, The PWM signal input circuit further includes an adjustment module, which includes a first diode, a first resistor, and a second resistor. The negative terminal of the first diode and the first end of the second resistor together serve as the input terminal of the adjustment module, and are electrically connected to the second end of the magnetic bead; The second end of the first resistor and the second end of the second resistor together serve as the output terminal of the adjustment module, and are electrically connected to the input terminal of the voltage divider bias circuit.

4. The driving circuit for the field-effect transistor according to claim 1, characterized in that, The voltage divider bias circuit specifically includes: a third resistor and a fourth resistor; The first end of the third resistor serves as the input terminal of the voltage divider bias circuit and is electrically connected to the PWM signal terminal through the PWM signal input circuit; the second end of the third resistor and the first end of the fourth resistor together serve as the output terminal of the voltage divider bias circuit and are electrically connected to the gate of the first field-effect transistor; the source of the first field-effect transistor is grounded. The second terminal of the fourth resistor is grounded.

5. The driving circuit for the field-effect transistor according to claim 4, characterized in that, The driving circuit further includes: a boost module, the boost module including a first capacitor; The first terminal of the first capacitor serves as the input terminal of the boost module and is electrically connected to the output terminal of the PWM signal input circuit. The second terminal of the first capacitor serves as the output terminal of the boost module and is electrically connected to the gate of the first field-effect transistor.

6. The driving circuit for the field-effect transistor according to claim 4, characterized in that, The driving circuit further includes: a voltage regulator module, the voltage regulator module including a first voltage regulator diode; The negative terminal of the first Zener diode serves as the input terminal of the voltage regulator module and is electrically connected to the gate of the first field-effect transistor. The positive terminal of the first Zener diode is grounded as the output terminal of the voltage regulator module.

7. The driving circuit for the field-effect transistor according to claim 6, characterized in that, The driving circuit further includes: a first inductor and a second capacitor; Wherein, the first end of the first inductor and the first end of the second capacitor are electrically connected to the VIN+ terminal, and the second end of the first inductor is electrically connected to the drain of the first field-effect transistor. The second terminal of the second capacitor is grounded.

8. A power supply drive circuit, comprising: The system comprises a demisting film control circuit, an EMI filter circuit, a transformer circuit, a VCC power supply circuit, an output rectifier filter circuit, a signal feedback circuit, and an over-temperature protection circuit. The demisting film control circuit is electrically connected to the EMI filter circuit. The transformer circuit and the output rectifier filter circuit are electrically connected. The VCC power supply circuit is electrically connected to the transformer circuit. The output rectifier filter circuit is electrically connected to the signal feedback circuit. The power supply drive circuit further includes a PFC boost circuit, a PWM pulse width modulation circuit, and a rectifier filter circuit. The PFC boost circuit includes a driving circuit for a field-effect transistor as described in any one of claims 1-7, and the PFC boost circuit is electrically connected to the power supply driving circuit; the PWM pulse width modulation circuit is electrically connected to the power supply driving circuit; and the power supply driving circuit is electrically connected to the rectifier filter circuit.

9. The power supply drive circuit according to claim 8, characterized in that, The PFC boost circuit is electrically connected to the power supply drive circuit; the PWM pulse width modulation circuit is electrically connected to the power supply drive circuit; the power supply drive circuit is electrically connected to the rectifier filter circuit; including: The rectifier filter circuit, the PFC boost circuit, and the PWM pulse width modulation circuit are electrically connected in sequence. The PWM pulse width modulation circuit, the VCC power supply circuit, and the transformer circuit are electrically connected in pairs. The signal feedback circuit and the PWM pulse width modulation circuit are connected by optocoupler.

10. The power supply drive circuit according to claim 9, characterized in that, The PWM pulse width modulation circuit includes: a PWM pulse width modulation chip; The PWM pulse width modulation chip includes a PG pin, which is used to output a PWM signal to the driving circuit.

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