Super-junction fast-recovery planar gate silicon carbide VDMOS

Abstract

The utility model provides a super-junction fast-recovery planar gate silicon carbide VDMOS. The super-junction fast-recovery planar gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to a silicon carbide substrate; the diffusion region is arranged in the drift layer and penetrates through the drift layer, the lower side surface of the diffusion region is connected to the upper side surface of the silicon carbide substrate, and an N-type source region is arranged on the diffusion region; the freewheeling region is arranged in the drift layer and penetrates through the drift layer, and the lower side surface of the freewheeling region is connected to the upper side surface of the silicon carbide substrate; the lower side surface of the gate dielectric layer is connected with the drift layer, the freewheeling region and the diffusion region; the gate metal layer is connected to the gate dielectric layer; the lower side surface of the source metal layer is connected with the drift layer, the diffusion region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate, a super junction structure constructed by a diffusion region and a current sharing region is constructed in the device, the voltage endurance capability of the device can be effectively improved under the conditions of fixed thickness and area, a Schottky diode is constructed, the reverse recovery time of the device can be effectively shortened, and fast recovery is realized.

Description

Technical Field

[0001] This utility model relates to a superjunction fast recovery planar gate silicon carbide VDMOS. Background Technology

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. For silicon carbide power VDMOS, the performance requirements vary across different applications, but generally include higher breakdown voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage surge reliability, and short-circuit reliability), and lower body diode conduction loss. Existing VDMOS devices still require further improvement in breakdown voltage and have a relatively long reverse recovery time, which urgently needs further enhancement. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a superjunction fast recovery planar gate silicon carbide VDMOS, which constructs a superjunction structure with diffusion region and current sharing region inside the device, which can effectively improve the voltage withstand capability of the device under fixed thickness and area conditions, and constructs a Schottky diode, which can effectively reduce the reverse recovery time of the device and achieve fast recovery.

[0004] In a first aspect, this utility model provides a superjunction fast recovery planar gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate,

[0006] A drift layer, the lower side of which is connected to the silicon carbide substrate;

[0007] A diffusion region is disposed within the drift layer and penetrates the drift layer. The lower side of the diffusion region is connected to the upper side of the silicon carbide substrate, and an N-type source region is disposed on the diffusion region.

[0008] A freewheeling region is provided within the drift layer and extends through the drift layer, and the lower side of the freewheeling region is connected to the upper side of the silicon carbide substrate.

[0009] A gate dielectric layer, wherein the lower side of the gate dielectric layer is respectively connected to the drift layer, the freewheeling region and the diffusion region;

[0010] A gate metal layer, the gate metal layer being connected to the gate dielectric layer;

[0011] A source metal layer, the lower side of which is connected to the drift layer, the diffusion region and the N-type source region;

[0012] And a drain metal layer connected to the silicon carbide substrate.

[0013] The advantages of this utility model are:

[0014] I. This utility model constructs a superjunction structure of the device by building a diffusion region and a freewheeling region in the drift layer, thereby changing the longitudinal withstand voltage of the device into a structure with both longitudinal and transverse withstand voltage, i.e., a superjunction structure, so as to improve the withstand voltage capability of devices with the same thickness and width.

[0015] 2. The direct Schottky contact between the source metal layer and the drift layer of this utility model can form a parasitic Schottky body diode, thereby improving the reverse recovery speed of the device, reducing the reverse recovery time, and improving the switching speed of the device.

[0016] Third, the diffusion region of the superjunction structure of the device completely surrounds the N-type source region, thus eliminating the need for additional well region processes, effectively reducing the complexity of the device fabrication process and lowering the device manufacturing cost. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This is a schematic diagram of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention.

[0019] Figure 2 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0020] Figure 3 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0021] Figure 4 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0022] Figure 5 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0023] Figure 6 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0024] Figure 7 This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0025] Figure 8This is a cross-sectional view of the process of a superjunction fast recovery planar gate silicon carbide VDMOS according to the present invention. Figure 7 . Detailed Implementation

[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0030] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0031] like Figure 1 As shown, this application embodiment provides a superjunction fast recovery planar gate silicon carbide VDMOS, comprising:

[0032] Silicon carbide substrate 1,

[0033] Drift layer 2, the lower side of which is connected to the silicon carbide substrate 1;

[0034] A diffusion region 3 is disposed within the drift layer 2 and penetrates the drift layer 2. The lower side of the diffusion region 3 is connected to the upper side of the silicon carbide substrate 1. An N-type source region 31 is provided on the diffusion region 3.

[0035] The continuous current region 4 is disposed within the drift layer 2 and penetrates the drift layer 2. The lower side of the continuous current region 4 is connected to the upper side of the silicon carbide substrate 1.

[0036] Gate dielectric layer 5, the lower side of which is connected to drift layer 2, freewheeling region 4 and diffusion region 3 respectively;

[0037] A gate metal layer 6 is connected to the gate dielectric layer 5;

[0038] Source metal layer 7, the lower side of which is connected to drift layer 2, diffusion region 3 and N-type source region 31;

[0039] And a drain metal layer 8, which is connected to the silicon carbide substrate 1.

[0040] In this embodiment, preferably, the doping concentration of the N-type source region 31 is greater than the doping concentration of the diffusion region 3, and the doping concentration of the diffusion region 3 is greater than the doping concentration of the drift layer 2.

[0041] In this embodiment, preferably, the total width of the diffusion region 3 is 40% of the width of the drift layer 2.

[0042] In this embodiment, preferably, the width of the continuous flow region 4 is 20% of the width of the drift layer 2.

[0043] In this embodiment, preferably, the distance between the inner side surface of the N-type source region 31 and the inner side surface of the diffusion region 3 is 20 nm.

[0044] In this embodiment, preferably, the distance between the inner side of the diffusion region 3 and the outer side of the continuous flow region 4 is 5% of the width of the drift layer 2.

[0045] like Figures 1 to 8 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0046] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 8, and epitaxially grow drift layer 2 on the upper side of silicon carbide substrate 1.

[0047] Step 2: Form a barrier layer 9 above the drift layer 2, etch the barrier layer 9 to form a via, and perform ion implantation into the drift layer 2 to form a diffusion region 3;

[0048] Step 3: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and perform ion implantation into the drift layer 2 to form the continuous flow region 4;

[0049] Step 4: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions into the diffusion region 3 to form an N-type source region 31;

[0050] Step 5: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form vias, and deposit the gate dielectric layer 5.

[0051] Step 6: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal, and form the gate metal layer 6.

[0052] Step 7: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal to form the source metal layer 8, remove the barrier layer 9, and complete the fabrication.

[0053] In another embodiment of this invention, the silicon carbide substrate 1, the drift layer 2, and the freewheeling region 4 are all N-type; the diffusion region 3 is P-type; and the doping concentration of the silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 1-5e17cm. -3 The doping concentration of P-type diffusion region 3 is 1-5e18cm. -3 The doping concentration of the N-type freewheeling region 4 is 1-2e18cm. -3 The gate dielectric layer 5 is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm. -3The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The P-type diffusion region 3 and the N-type freewheeling region 4 are designed to construct the superjunction structure in the device. Their concentration design is to achieve a trade-off between breakdown voltage and potential guidance from the drain to the source. The P-type diffusion region 3 also serves as the well region of the device. The doping concentration of the N-type source region 31 is to reduce the source contact resistance of the device and reduce the on-resistance of the device. In addition to forming the superjunction structure, the N-type freewheeling region 4 also provides a freewheeling channel when the device is turned on, thereby reducing the on-resistance of the device.

[0054] The thickness of the N-type silicon carbide substrate 1 is 1 μm, the thickness of the N-type drift layer 2 is 10-30 μm, and it is adjusted within the above range according to the different requirements of the device's withstand voltage characteristics. The total width of the P-type diffusion region 3 is 40% of the width of the drain metal layer 8, the width of the N-type freewheeling region 4 is 20% of the width of the drain metal layer 8, and the distance between the outer side of the N-type freewheeling region 4 and the inner side of the P-type diffusion region 3 is 5% of the width of the drain metal layer 8. This is to suppress the influence of the N-type freewheeling region 4 and the P-type diffusion region 3 on the device's gate structure. The width of the N-type source region 31 is 10% of the width of the drain metal layer 8, and the distance between the inner side of the N-type source region 31 and the inner side of the P-type diffusion region is 20 nm. This part of the region is distributed below the device gate. The thickness of the N-type source region 31 is 200 nm, the thickness of the source metal layer 7 is 200 nm, and the thickness of the gate metal layer 6 is 150 nm.

[0055] By constructing a P-type diffusion region 3 and an N-type freewheeling region 4 within the N-type drift layer 2, a superjunction structure of the device is constructed, thereby changing the longitudinal withstand voltage of the device to a structure with both longitudinal and lateral withstand voltage, i.e., a superjunction structure, to improve the withstand voltage capability of devices with the same thickness and width.

[0056] The direct Schottky contact between the source metal layer 7 and the N-type drift layer 2 of the device can form a parasitic Schottky body diode, thereby improving the reverse recovery speed, reducing the reverse recovery time, and improving the switching speed of the device.

[0057] The P-type diffusion region 3, which forms a superjunction structure, completely surrounds the N-type source region 31, thus eliminating the need for additional P-type well region processes. This effectively reduces the complexity of the device fabrication process and lowers the device manufacturing cost.

[0058] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A superjunction fast recovery planar gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the silicon carbide substrate; A diffusion region is disposed within the drift layer and penetrates the drift layer. The lower side of the diffusion region is connected to the upper side of the silicon carbide substrate, and an N-type source region is disposed on the diffusion region. A freewheeling region is provided within the drift layer and extends through the drift layer, and the lower side of the freewheeling region is connected to the upper side of the silicon carbide substrate. A gate dielectric layer, wherein the lower side of the gate dielectric layer is respectively connected to the drift layer, the freewheeling region and the diffusion region; A gate metal layer, the gate metal layer being connected to the gate dielectric layer; A source metal layer, the lower side of which is connected to the drift layer, the diffusion region and the N-type source region; And a drain metal layer connected to the silicon carbide substrate.

2. The superjunction fast recovery planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the N-type source region is greater than that of the diffusion region, and the doping concentration of the diffusion region is greater than that of the drift layer.

3. The superjunction fast recovery planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The total width of the diffusion region is 40% of the width of the drift layer.

4. The superjunction fast recovery planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the follow-through region is 20% of the width of the drift layer.

5. The superjunction fast recovery planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The distance between the inner side surface of the N-type source region and the inner side surface of the diffusion region is 20 nm.

6. The superjunction fast recovery planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The distance between the inner side of the diffusion zone and the outer side of the follow-through zone is 5% of the drift layer width.

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