Capacitance detection circuit

Abstract

The utility model relates to the technical field of capacitance detection, and discloses a capacitance detection circuit which comprises two capacitance detection units, and each capacitance detection unit comprises a capacitor CP, a switch S2, a waveform shaping unit and a T trigger. When in use, two same capacitance detection units are arranged, one capacitance detection unit is connected with a capacitor to be detected through a switch S1, T triggers of the two capacitance detection units respectively output a detection clock signal and a standard clock signal, and the detection clock signal and the standard clock signal are counted through two counters. Therefore, the detection of the capacitor to be detected can be realized according to the count values of the two counters. The circuit structures of the other two capacitance detection units are the same, and the influence of the external temperature change and the power supply voltage change on the two capacitance detection units is the same, that is, the count value changes of the two counters are the same, so that the detection accuracy of the to-be-detected capacitor is not influenced, and the anti-interference performance of the circuit is improved.

Description

Technical Field

[0001] This utility model relates to the field of capacitance detection technology, and specifically to a capacitance detection circuit. Background Technology

[0002] Most capacitive sensors detect signals by sensing changes in capacitance. For example, in existing airflow sensors, the capacitance changes when airflow is present. Additionally, many chips connect to external sensors via an oscillator-like structure; when the oscillator frequency changes beyond a certain range, the external capacitance is interpreted as changing.

[0003] The existing capacitive detection structure has poor anti-interference performance in actual use. If there are significant changes in room temperature or drastic noise fluctuations in the power supply voltage, false detections are likely to occur, affecting the detection reliability of the capacitive sensor. Utility Model Content

[0004] In view of the shortcomings of the prior art, the present invention provides a capacitance detection circuit. The technical problem to be solved is that the existing capacitance detection circuit has poor anti-interference ability, and temperature changes and power supply voltage changes will affect the reliability of the detection results.

[0005] To solve the above technical problems, this utility model provides the following technical solution: a capacitance detection circuit, including two capacitance detection units, each capacitance detection unit including a capacitor CP, a switch S2, a waveform shaping unit and a T flip-flop;

[0006] One end of the capacitor CP is connected to the input terminal of the switch S2 and the input terminal of the waveform shaping unit, respectively; the other end of the capacitor CP is electrically connected to the output terminal of the switch S2 and grounded; the output terminal of the waveform shaping unit is electrically connected to the control terminal of the switch S2 and the clock input terminal of the T flip-flop, respectively.

[0007] One capacitor CP terminal of a capacitance detection unit is used to input a first current and is electrically connected to one end of the capacitor under test through switch S1, while the other end of the capacitor under test is grounded; one capacitor CP terminal of another capacitance detection unit is used to input a second current.

[0008] The Q output of the T flip-flop in each capacitor detection unit is electrically connected to a counter.

[0009] In one embodiment, the waveform shaping unit includes a first inverter INV1 and a second inverter INV2 connected in series. The input terminal of the first inverter INV1 is the input terminal of the waveform shaping unit, and the output terminal of the second inverter INV2 is the output terminal of the waveform shaping unit.

[0010] In certain embodiments, the switch S2 is turned on when the output terminal of the waveform shaping unit outputs a high level signal, and is turned off when the output terminal of the waveform shaping unit outputs a low level signal.

[0011] In certain embodiments, the switch S2 is an NMOS tube.

[0012] In certain embodiments, the first current and the second current have the same magnitude.

[0013] In certain embodiments, the utility model further includes a current generating circuit, the current generating circuit is electrically connected with two capacitor detection units, and provides the first current and the second current for the two capacitor detection units.

[0014] In certain embodiments, the current generating circuit includes MOS tubes P1, P2, P3, P4, an NMOS tube N1, a resistor RS and K MOS tubes N2; K is a positive integer.

[0015] The source of the MOS tube P1 is electrically connected with the source of the MOS tube P2, the source of the MOS tube P3 and the source of the MOS tube P4, and is used for connecting a power supply voltage VDD.

[0016] The gate of the MOS tube P1 is electrically connected with the gate of the MOS tube P2, the drain of the MOS tube P2, the drain of the K MOS tubes N2, the gate of the MOS tube P3 and the gate of the MOS tube P4.

[0017] The drain of the MOS tube P1 is electrically connected with the drain of the MOS tube N1, the gate of the MOS tube N1 and the gate of the K MOS tubes N2; the source of the MOS tube N1 is grounded, and the source of the K MOS tubes N2 is electrically connected with one end of the resistor RS, and the other end of the resistor RS is grounded.

[0018] The drain of the MOS tube P3 is used for outputting the first current, and the drain of the MOS tube P4 is used for outputting the second current.

[0019] In certain embodiments, the channel width of the MOS tube P1, the channel width of the MOS tube P2, the channel width of the MOS tube P3 and the channel width of the MOS tube P4 are the same.

[0020] The channel length of the MOS tube P1, the channel length of the MOS tube P2, the channel length of the MOS tube P3 and the channel length of the MOS tube P4 are the same.

[0021] In certain embodiments, the channel width of the MOS tube N1 and the channel width of the MOS tube N2 are the same; and the channel length of the MOS tube N1 and the channel length of the MOS tube N2 are the same.

[0022] In some embodiments, the switch S1 is an NMOS transistor.

[0023] The utility model discloses a beneficial effect compared with prior art is: the utility model discloses through setting up two identical capacitors detection unit, and let one capacitor detection unit pass through switch S1 and be connected with the capacitor to be detected, such that the T flip-flop of this capacitor detection unit is used for output detection clock signal, and the T flip-flop of another capacitor detection unit is used for output standard clock signal, and the detection clock signal and standard clock signal are counted to two counters, thereby can realize the detection of the capacitor to be detected according to the count value of two counters;

[0024] In addition, the circuit structure of the other two capacitor detection units is same, and the influence of temperature change and power supply voltage change on the two capacitor detection units is same, that is, the influence on the output clock signal and standard clock signal is same, so that the count value of two counters changes same, thereby the detection accuracy of the capacitor to be detected is not affected, and the anti-interference of the circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is the structural schematic diagram of the capacitor detection circuit in the embodiment;

[0026] Figure 2 It is the circuit diagram of the capacitor detection unit in the embodiment;

[0027] Figure 3 It is the circuit diagram of the current generating circuit in the embodiment;

[0028] Figure 4 It is the level waveform diagram of the relevant node of the capacitor detection unit connected with the capacitor to be detected. DETAILED DESCRIPTION

[0029] The utility model will be further explained in detail in combination with the drawings. These drawings are all simplified schematic diagrams, and only illustrate the basic structure of the utility model in a schematic manner, so it only shows the relevant constitution of the utility model.

[0030] As Figure 1 Indicated, a kind of capacitor detection circuit, including two capacitor detection units 1, as Figure 2 Indicated, each capacitor detection unit 1 includes capacitor CP, switch S2, waveform shaping unit 10 and T flip-flop respectively;

[0031] Capacitor CP one end is connected with the input end of switch S2 and the input end of waveform shaping unit 10 respectively;Capacitor CP other end and the output end of switch S2 are electrically connected, and ground;The output end of waveform shaping unit 10 is electrically connected with the control end of switch S2 and the clock input end of T flip-flop respectively;

[0032] One end of the capacitor CP of one capacitor detection unit 1 is used for inputting a first current I1, and is electrically connected with one end of the to-be-detected capacitor C1 through a switch S1, and the other end of the to-be-detected capacitor C1 is grounded, wherein the switch S1 can be an NMOS tube; one end of the capacitor CP of another capacitor detection unit 1 is used for inputting a second current I2.

[0033] The Q output end of the T flip-flop of each capacitor detection unit 1 is electrically connected with a counter 2 respectively.

[0034] In actual use, the utility model discloses two same capacitor detection units 1, and one capacitor detection unit 1 is connected with the to-be-detected capacitor C1 through the switch S1, so that the T flip-flop of the capacitor detection unit 1 is used for outputting the detection clock signal CLKA, and the T flip-flop of another capacitor detection unit is used for outputting the standard clock signal CLKB, and the detection clock signal CLKA and the standard clock signal CLKB are counted through two counters 1, so that the detection of the to-be-detected capacitor can be realized according to the counting values of the two counters 2.

[0035] In addition, the circuit structures of the other two capacitor detection units 1 are same, the temperature change and the power supply voltage change of the outside world have same influence on the two capacitor detection units 1, that is, have same influence on the output clock signal CLKA and the standard clock signal CLKB, so that the counting values of the two counters 2 change same, thereby the detection accuracy of the to-be-detected capacitor C1 is not influenced, and the anti-interference of the circuit is improved

[0036] Specifically, in the embodiment, the waveform shaping unit 10 includes a first inverter INV1 and a second inverter INV2 connected in series, the input end of the first inverter INV1 is the input end of the waveform shaping unit 10, and the output end of the second inverter INV2 is the output end of the waveform shaping unit 10.

[0037] Specifically, in the embodiment, the switch S2 is turned on when the output end of the waveform shaping unit 10 outputs a high level signal, and is turned off when the output end of the waveform shaping unit 10 outputs a low level signal. The switch S2 can be an NMOS tube.

[0038] In some embodiments, the switch S2 can be selected as other transistors.

[0039] In the embodiment, the first current and the second current have same size. In addition, the utility model also includes a current generating circuit, the current generating circuit is electrically connected with the two capacitor detection units 1, and provides the first current I1 and the second current I2 for the two capacitor detection units 1.

[0040] The circuit of the current generating circuit is as follows: Figure 3As shown, it includes MOSFETs P1, P2, P3, P4, N1, resistor RS, and K MOSFETs N2; K is a positive integer.

[0041] The source of MOSFET P1 is electrically connected to the sources of MOSFET P2, MOSFET P3 and MOSFET P4 respectively, for connection to the power supply voltage VDD.

[0042] The gate of MOSFET P1 is electrically connected to the gate of MOSFET P2, the drain of MOSFET P2, the drains of K MOSFETs N2, the gate of MOSFET P3, and the gate of MOSFET P4, respectively.

[0043] The drain of MOSFET P1 is electrically connected to the drain of MOSFET N1, the gate of MOSFET N1, and the gates of K MOSFETs N2, respectively; the source of MOSFET N1 is grounded, and the sources of K MOSFETs N2 are electrically connected to one end of resistor RS, while the other end of resistor RS is grounded.

[0044] The drain of MOSFET P3 is used to output the first current, and the drain of MOSFET P4 is used to output the second current.

[0045] More specifically, the channel widths of MOSFET P1, MOSFET P2, MOSFET P3, and MOSFET P4 are the same.

[0046] The channel lengths of MOSFET P1, MOSFET P2, MOSFET P3, and MOSFET P4 are the same.

[0047] More specifically, the channel width of MOSFET N1 is the same as that of MOSFET N2; the channel length of MOSFET N1 is the same as that of MOSFET N2.

[0048] for Figure 3 In the circuit shown, MOSFETs P1, P2, P3, and P4 form a current mirror, and MOSFET N1 and K MOSFETs N2 form another current mirror. The number of K is set according to actual needs; for example, K can be 2, 3, 4, 5, 6, or other numbers.

[0049] for Figure 3 In the circuit shown, since the gates of MOSFET N1 and MOSFET N2 are interconnected, we can obtain:

[0050] VGS_N1=VGSN2+Iref×RS

[0051] Where VGS_N1 is the gate-source voltage of MOSFET N1, and VGS_N2 is the gate-source voltage of MOSFET N2; from this formula, we can obtain:

[0052]

[0053] Wherein W is the channel width of MOS tube N1, L is the channel length of MOS tube N1; In addition, since the size of MOS tube P3 and the size of MOS tube P4 are same, I1=I2=Iref.

[0054] The circuit of Figure 1 , Figure 2 and Figure 3 is analyzed as follows:

[0055] First, the capacitor detection unit 1, when the voltage of node CAP_SEN is less than the first inverter INV1 turning point, clock CLK=0, namely low level state, switch S2 is opened, the first current I1 charges the capacitor Cp, the voltage of node CAP_SEN slowly rises;

[0056] When the voltage of node CAP_SEN is greater than the first inverter INV1 turning point, clock CLK=1, namely high level state, switch S2 is closed, node CAP_SEN is pulled to ground, at this time node CAP_SEN=0, the state of detection clock signal CLKA is low level state, the first current I1 charges the capacitor Cp;

[0057] The level change of relevant node in the whole working process of capacitor detection unit 1 is shown in Figure 4 From Figure 4 , for the detection clock signal CLKA, half cycle time t1=0.5*(VDD / I1)*Cp; At this time, the calculation formula of the frequency FA of detection clock signal CLKA is as follows:

[0058]

[0059] When switch S1 is closed, the calculation formula of the frequency FA of detection clock signal CLKA is as follows:

[0060]

[0061] In actual work, the utility model has two working stages, which are initialization stage and normal working stage respectively:

[0062] In the initialization stage, the switch S1 is disconnected, the capacitor detection unit 1 is not connected to the external capacitor C1 to be detected, at this time, because the first current I1 is equal to the second current I2, the two capacitor detection units 1 are the same in structure, the CLKA=CLKB can be obtained, then the count values of the two counters 2 are the same, the count values of the two counters 2 are respectively denoted as A and B, then A=B, FA=FB=(I1 / VDD)*Cp, FB is the frequency of the standard clock signal CLKB;

[0063] In this stage, when the current generating circuit is stable, it is considered that the initialization stage is completed.

[0064] In the normal working stage, the switch S1 is closed, one capacitor detection unit 1 is connected to the capacitor C1 to be detected, the frequency of the detection clock signal CLKA is slow, at this time, the corresponding count value A and the count value B are obtained.

[0065] The frequency of the detection clock signal CLKA is:

[0066]

[0067] The frequency of the standard clock signal CLKB is:

[0068]

[0069] And because the first current I1 and the second current I2 are the same, therefore

[0070]

[0071] FA and FB are brought into and the following can be obtained:

[0072]

[0073] Finally, the following can be obtained:

[0074]

[0075] From the calculation formula of the capacitor C1, it can be obtained that the capacitor CP is known, and A and B are the count values of the two counters 2, therefore, after A and B are known, the capacitor value of the capacitor C1 to be detected can be known, the capacitor detection calculation can be realized without the need of an ADC and other digital-analog conversion modules, and the structure is simple.

[0076] According to the above description, the related personnel can make various changes and modifications without deviating from the technical idea of the present application. The technical scope of the present application is not limited to the content in the specification, and must be determined according to the scope of the claims.

Claims

1. A capacitance detection circuit, characterized by, The two capacitor detection units each include a capacitor CP, a switch S2, a waveform shaping unit and a T flip-flop; One end of the capacitor CP is connected with the input end of the switch S2 and the input end of the waveform shaping unit respectively; the other end of the capacitor CP is electrically connected with the output end of the switch S2 and grounded; the output end of the waveform shaping unit is electrically connected with the control end of the switch S2 and the clock input end of the T flip-flop respectively; One end of the capacitor CP of one capacitor detection unit is used for inputting a first current and is electrically connected with one end of a to-be-detected capacitor through a switch S1, and the other end of the to-be-detected capacitor is grounded; one end of the capacitor CP of the other capacitor detection unit is used for inputting a second current; The Q output end of the T flip-flop of each capacitor detection unit is electrically connected with a counter respectively.

2. The capacitance detection circuit of claim 1, wherein, The waveform shaping unit includes a first inverter INV1 and a second inverter INV2 connected in series, the input end of the first inverter INV1 is the input end of the waveform shaping unit, and the output end of the second inverter INV2 is the output end of the waveform shaping unit.

3. The capacitance detection circuit of claim 1, wherein, The switch S2 is turned on when the output end of the waveform shaping unit outputs a high-level signal, and is turned off when the output end of the waveform shaping unit outputs a low-level signal.

4. The capacitance detection circuit of claim 3, wherein, The switch S2 is an NMOS tube.

5. The capacitance detection circuit of claim 1, wherein, The first current and the second current have the same size.

6. The capacitance detection circuit of claim 5, wherein, The current generating circuit is further electrically connected with the two capacitor detection units and provides the first current and the second current for the two capacitor detection units.

7. The capacitance detection circuit of claim 6, wherein, The current generating circuit includes MOS tubes P1, P2, P3, P4, N1, a resistor RS and K MOS tubes N2; K is a positive integer. The source of the MOS tube P1 is electrically connected with the source of the MOS tube P2, the source of the MOS tube P3 and the source of the MOS tube P4 respectively, and is used for connecting a power supply voltage VDD. The gate of the MOS tube P1 is electrically connected with the gate of the MOS tube P2, the drain of the MOS tube P2, the drain of the K MOS tubes N2, the gate of the MOS tube P3 and the gate of the MOS tube P4 respectively. The drain of the MOS tube P1 is electrically connected with the drain of the MOS tube N1, the gate of the MOS tube N1 and the gate of the K MOS tubes N2 respectively; the source of the MOS tube N1 is grounded, and the source of the K MOS tubes N2 is electrically connected with one end of the resistor RS respectively, and the other end of the resistor RS is grounded. The drain of the MOS tube P3 is used for outputting the first current, and the drain of the MOS tube P4 is used for outputting the second current.

8. The capacitance detection circuit of claim 7, wherein, The channel width of the MOS tube P1, the channel width of the MOS tube P2, the channel width of the MOS tube P3 and the channel width of the MOS tube P4 are the same. The channel length of the MOS tube P1, the channel length of the MOS tube P2, the channel length of the MOS tube P3 and the channel length of the MOS tube P4 are the same.

9. The capacitance detection circuit of claim 8, wherein, The channel width of the MOS tube N1 and the channel width of the MOS tube N2 are the same; the channel length of the MOS tube N1 and the channel length of the MOS tube N2 are the same.

10. The capacitance detection circuit of claim 1, wherein, The switch S1 is an NMOS tube.

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