Sepic power factor correction converter

Abstract

The utility model belongs to the technical field of converters, and discloses a Sepic power factor correction converter, which comprises a conversion circuit, the conversion circuit comprises a port L and a port N. The port L is connected with one end of a capacitor C201 and one end of an inductor L21, the other end of the capacitor C201 is connected with one end of a capacitor C244, the other end of the inductor L21 is connected with a drain electrode of an MOS tube Q15, a negative end of a diode D57 and one end of a capacitor C277, and the other end of the capacitor C277 is connected with a negative end of a diode D57. The other end of the capacitor C277 is connected with one end of an inductor L17 and a pin 1 of a transformer T4, and a source electrode of the MOS tube Q15 is connected with a source electrode of the MOS tube Q14, a positive end of a diode D57, a positive end of a diode D58, the other end of the inductor L17, one end of an inductor L20, a pin 2 of the transformer T4 and a pin 3 of the transformer T4. The beneficial effects of the utility model are that the protection function is complete, the circuit reliability is high, the software control is simple, and the cost is low.

Description

TECHNICAL FIELD

[0001] The utility model relates to inverter technical field especially relates to a Sepic power factor correction inverter. BACKGROUND

[0002] Switching power supply with its light, high efficiency, control flexibility, power density, reliability and a series of advantages arouses the industry's attention, and is widely applied in modern power conversion device. The part of alternating current nonlinear load in the switching power supply represented conversion equipment or circuit can produce a large number of harmonic current components that make the alternating current input waveform distortion inject into the power grid, which has negative influence on the power quality and transmission efficiency of alternating current power grid, therefore, the harmonic pollution of conversion equipment is governed, and the input power factor performance is improved to become the key topic to be conquered in green power electronics technology.

[0003] The traditional power factor correction circuit generally adopts Boost circuit, and the circuit control is complex, the output voltage is higher than the input voltage, and the electrical isolation between the input and output is difficult to realize. In order to realize the electrical isolation between the input and output, the BOOST circuit is generally used to realize the shaping of input current at present, and the output voltage of the front stage is the voltage of the energy storage capacitor. Whether the capacitor is large or small, there is a double line frequency ripple, and then the DC-DC converter is used to realize isolation and conversion to obtain high-precision DC output voltage. But it adopts two-stage circuit, and the circuit is complex, the cost is high, the whole machine efficiency is low, and the volume is large. Some scholars use the power factor correction circuit composed of flyback circuit, but it must work in the discontinuous state of inductance current, electromagnetic interference is large, and it is not suitable for high-power occasions.

[0004] The Sepic circuit has unique advantages for power factor correction. Since the front stage is similar to the Boost converter, the continuity of the input current can be ensured and the electromagnetic interference can be reduced. The output stage is similar to the flyback circuit, and the electrical isolation can be easily realized. The separate Sepic circuit only needs to work in the current discontinuous state to naturally realize the power factor. Here, the discontinuity refers to the discontinuity of the current on the diode, and the current on the input boost inductor is continuous. Therefore, the Sepic-based PFC circuit is receiving more and more attention. The traditional Sepic-type PFC circuit is only suitable for small power occasions. With the increase of output power, the output current will be distorted, and the traditional Sepic-type PFC usually uses a rectifier bridge to rectify the input voltage, which increases the on-state loss and makes it difficult to improve the efficiency of the traditional Sepic-type PFC circuit.

[0005] Therefore, it is necessary to provide a Sepic power factor correction inverter with perfect protection function, high circuit reliability, simple software control and low cost. UTILITY MODEL CONTENTS

[0006] The utility model discloses a Sepic power factor correction converter relates to power factor correction converter technical field, especially, relates to a kind of high-efficiency bridgeless Sepic power factor correction converter, it can effectively solve the technical problem involved in background art.

[0007] To achieve the above object, the technical scheme of the utility model is:

[0008] A Sepic power factor correction converter, including conversion circuit, the conversion circuit includes port L and port N, the port L connects the one end of capacitor C201 and the one end of inductor L21, the other end of capacitor C201 connects the one end of capacitor C244, the other end of inductor L21 connects the drain of MOS tube Q15, the negative end of diode D57 and the one end of capacitor C277, the other end of capacitor C277 connects the one end of inductor L17 and the pin 1 of transformer T4, the source of MOS tube Q15 connects the source of MOS tube Q14, the positive end of diode D57, the positive end of diode D58, the other end of inductor L17, the one end of inductor L20, the pin 2 of transformer T4 and the pin 3 of transformer T4, the port N connects the other end of capacitor C244, the drain of MOS tube Q14, the negative end of diode D58 and the one end of capacitor C246, the other end of capacitor C246 connects the other end of inductor L20 and the pin 4 of transformer T4;The pin 5 of transformer T4 connects the source of MOS tube Q17, the pin 6 of transformer T4 connects the pin 7 of transformer T4, the one end of capacitor C305 and port GND, the pin 8 of transformer T4 connects the source of MOS tube Q16, the drain of MOS tube Q16 connects the drain of MOS tube Q17, the one end of capacitor C301 and port VOUT+, the other end of capacitor C301 connects the other end of capacitor C305, and the converter further includes compensation circuit.

[0009] Disclosed is a high-efficiency bridgeless interleaved Sepic power factor correction converter suitable for charging piles or some intelligent power distribution systems, comprising two isolated Sepic power factor correction circuits and a ramp compensation circuit, the ramp compensation technology is used to solve the zero-crossing distortion problem of low input voltage of the converter, and the interleaved parallel connection of the converter can improve the output power of the converter and reduce the output voltage and current ripple of the converter. The high-efficiency bridgeless interleaved Sepic power factor correction converter comprises an input energy storage capacitor, an energy storage inductor, a pair of MOS transistors, an energy storage capacitor, an energy storage inductor and a transformer connected in sequence; a rectifier MOS transistor; the ramp compensation circuit comprises an error amplifier, a comparator and a compensation network; the high-efficiency bridgeless interleaved Sepic power factor correction converter can ensure continuous input current, thereby reducing electromagnetic interference; since the converter is only a single-stage circuit, the efficiency can be as high as 98%, the input current harmonic can be lower than 3%, and the PF value can be as high as 0.99 or above; the output is easy to electrically isolate, so that the whole converter is safe and stable; the converter is suitable for charging piles or some intelligent power distribution systems, has perfect protection function, high circuit reliability, simple software control and low cost.

[0010] As a preferred improvement of the utility model: the number of the conversion circuit is multiple, the port L of multiple conversion circuits is connected with each other, the port N is connected with each other, the port VOUT+ is connected with each other, and the port GND is connected with each other.

[0011] As a preferred improvement of the utility model: the number of the conversion circuit is two, and the two conversion circuits work 180 degrees staggered.

[0012] As a preferred improvement of the utility model: the port L and the port N are connected with commercial power, and the port VOUT+ is connected with load or battery.

[0013] As a preferred improvement of the utility model: one end of resistance R245 and one end of resistance R242 of gate of MOS tube Q16 are connected, the other end of resistance R245 is connected to the positive end of diode D63, the other end of resistance R242 and the negative end of diode D63 are connected to port DRV_4;One end of resistance R236 and one end of resistance R237 of gate of MOS tube Q17 are connected, the other end of resistance R237 is connected to the positive end of diode D61, the other end of resistance R236 and the negative end of diode D61 are connected to port DRV_3;One end of resistance R250, one end of resistance R256 and one end of resistance R257 of gate of MOS tube Q15 are connected, the other end of resistance R257 is connected to the source of MOS tube Q15, the other end of resistance R256 is connected to the positive end of diode D21, the other end of resistance R250 and the negative end of diode D21 are connected to port DRV_1;One end of resistance R258, one end of resistance R259 and one end of resistance R260 of gate of MOS tube Q14 are connected, the other end of resistance R260 is connected to the drain of MOS tube Q14, the other end of resistance R259 is connected to the positive end of diode D24, the other end of resistance R258 and the negative end of diode D24 are connected to port DRV_1;Port DRV_1, port DRV_3 and port DRV_4 are connected to controller.

[0014] As a preferred improvement of the utility model: the transformer further includes compensation circuit, the compensation circuit includes port V_COMP, the port V_COMP is connected to the pin 1 of comparator U27, the pin 2 of comparator U27 is connected to port CS, the pin 3 of comparator U27 is connected to the pin 1 of amplifier U26, one end of capacitor C252 and one end of capacitor C247, the other end of capacitor C252 is connected to one end of resistance R261, the pin 2 of amplifier U26 is connected to the other end of resistance R261, the other end of capacitor C247, one end of resistance R249, one end of resistance R248 and one end of capacitor C250, the other end of resistance R249 is connected to port GND, the other end of capacitor C250 is connected to one end of resistance R262, the other end of resistance R248 and the other end of resistance R262 are connected to port VOUT+, the pin 3 of amplifier U26 is connected to one end of capacitor C245 and port VREF, the other end of capacitor C245 is connected to port GND.

[0015] As a preferred improvement of the utility model: port VREF is connected to 1.5V power supply.

[0016] As a preferred improvement of the utility model: the port V_COMP connects the feedback pin of the controller, the port CS connects the reference pin of the controller, the controller connects the gate of MOS tube Q14, the gate of MOS tube Q15, the gate of MOS tube Q16 and the gate of MOS tube Q17.

[0017] The utility model discloses the beneficial effects are as follows:

[0018] Simple structure, stable operation, disclose a kind of high-efficiency bridgeless Sepic power factor correction conversion circuit, its efficiency can be as high as 98%, its input current harmonic can be lower than 3%, PF value is as high as 0.99 above;Its output is easily electrically isolated The advantage makes the whole converter become safe, stable;It is applicable to charging pile or some intelligent power distribution system, and protection function is perfect, circuit reliability is high, software control is simple, and cost is low. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the drawings needed to be used in the embodiment description will be simply introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without creative labor, wherein:

[0020] Figure 1 It is the schematic diagram of the utility model conversion circuit;

[0021] Figure 2 It is the schematic diagram of the utility model compensation circuit;

[0022] Figure 3 It is the structural schematic diagram of embodiment one. DETAILED DESCRIPTION

[0023] The technical scheme in the embodiment of the utility model will be clearly and completely described below, obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0024] It should be noted that all directionality indications (such as up, down, left, right, front, back...) in the embodiment of the application are only used to explain the relative position relationship, movement condition and the like between components in a certain specific posture (as shown in the drawings), if the specific posture changes, then the directionality indication also changes accordingly.

[0025] In addition, the descriptions such as "first", "second", etc. in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0026] In the present application, unless otherwise specifically defined and limited, the terms "connection", "fixation" and the like should be understood broadly, for example, "fixation" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0027] In addition, the technical solutions of various embodiments of the present application can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection required by the present application.

[0028] Please refer to Figure 1The utility model provides a Sepic power factor correction converter, including conversion circuit, compensation circuit and controller, the conversion circuit includes port L and port N, one end of port L is connected with capacitor C201 and inductance L21, the other end of capacitor C201 is connected with one end of capacitor C244, the other end of inductance L21 is connected with the drain electrode of MOS tube Q15, the negative end of diode D57 and one end of capacitor C277, one end of capacitor C277 is connected with inductance L17 and the pin 1 of transformer T4, the source electrode of MOS tube Q15 is connected with the source electrode of MOS tube Q14, the positive end of diode D57, the positive end of diode D58, the other end of inductance L17, one end of inductance L20, the pin 2 of transformer T4 and the pin 3 of transformer T4, port N is connected with the other end of capacitor C244, the drain electrode of MOS tube Q14, the negative end of diode D58 and one end of capacitor C246, the other end of capacitor C246 is connected with the other end of inductance L20 and the pin 4 of transformer T4, the pin 5 of transformer T4 is connected with the source electrode of MOS tube Q17, the pin 6 of transformer T4 is connected with the pin 7 of transformer T4, one end of capacitor C305 and port GND, the pin 8 of transformer T4 is connected with the source electrode of MOS tube Q16, the drain electrode of MOS tube Q16 is connected with the drain electrode of MOS tube Q17, one end of capacitor C301 and port VOUT+, the other end of capacitor C301 is connected with the other end of capacitor C305, port L and port N are connected with commercial power, port VOUT+ is connected with load or battery, and compensation circuit is connected with port VOUT+.

[0029] Disclosed is a high-efficiency bridgeless interleaved Sepic power factor correction converter, comprising a Sepic power factor correction conversion circuit and a ramp compensation circuit, the ramp compensation technique is used to solve the zero-crossing distortion problem of the low input voltage of the converter, and meanwhile, the converter adopts interleaved parallel connection to improve the output power of the converter and reduce the output voltage and current ripple of the converter; the high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit is sequentially connected with an input energy storage capacitor, an energy storage inductor, a top-to-top MOS tube, an energy storage capacitor, an energy storage inductor and a transformer; a rectification MOS tube; the ramp compensation circuit comprises an error amplifier, a comparator and a compensation network thereof; the conversion efficiency of the converter can be as high as 98%, the input current harmonic can be lower than 3%, and the PF value can be higher than 0.99.

[0030] As an implementation manner, one end of a gate of the MOS tube Q16 is connected with one end of a resistor R245 and one end of a resistor R242, the other end of the resistor R245 is connected with a positive end of a diode D63, the other end of the resistor R242 and a negative end of the diode D63 are connected with a port DRV_4; one end of a gate of the MOS tube Q17 is connected with one end of a resistor R236 and one end of a resistor R237, the other end of the resistor R237 is connected with a positive end of a diode D61, the other end of the resistor R236 and a negative end of the diode D61 are connected with a port DRV_3; one end of a gate of the MOS tube Q15 is connected with one end of a resistor R250, one end of a resistor R256 and one end of a resistor R257, the other end of the resistor R257 is connected with a source of the MOS tube Q15, the other end of the resistor R256 is connected with a positive end of a diode D21, the other end of the resistor R250 and a negative end of the diode D21 are connected with a port DRV_1; one end of a gate of the MOS tube Q14 is connected with one end of a resistor R258, one end of a resistor R259 and one end of a resistor R260, the other end of the resistor R260 is connected with a drain of the MOS tube Q14, the other end of the resistor R259 is connected with a positive end of a diode D24, the other end of the resistor R258 and a negative end of the diode D24 are connected with a port DRV_1; the port DRV_1, the port DRV_3 and the port DRV_4 are connected with a controller. It needs to be further explained that other components are adopted to achieve the above effects, which should belong to the inventive concept of the utility model and should belong to the protection scope of the utility model.

[0031] Please refer to Figure 2As shown, the converter further comprises a compensation circuit, the compensation circuit comprises a port V_COMP, a pin 1 of a comparator U27 is connected to the port V_COMP, a pin 2 of the comparator U27 is connected to a port CS, a pin 3 of the comparator U27 is connected to a pin 1 of an amplifier U26, one end of a capacitor C252 and one end of a capacitor C247, the other end of the capacitor C252 is connected to one end of a resistor R261, a pin 2 of the amplifier U26 is connected to the other end of the resistor R261, the other end of the capacitor C247, one end of a resistor R249, one end of a resistor R248 and one end of a capacitor C250, the other end of the resistor R249 is connected to a port GND, the other end of the capacitor C250 is connected to one end of a resistor R262, the other end of the resistor R248 and the other end of the resistor R262 are connected to a port VOUT+, a pin 3 of the amplifier U26 is connected to one end of a capacitor C245 and a port VREF, the other end of the capacitor C245 is connected to the port GND, the port VREF is connected to a 1.5V power supply, the port V_COMP is connected to a feedback pin of a controller, the port CS is connected to a reference pin of the controller, and the controller is connected to a gate of a MOS Q14, a gate of a MOS Q15, a gate of a MOS Q16 and a gate of a MOS Q17. It should be further explained that other components can be used to achieve the above effects, which should be within the inventive concept of the present application and should be within the protection scope of the present application.

[0032] As an embodiment, the number of the conversion circuits is multiple, the ports L of the multiple conversion circuits are connected to each other, the ports N are connected to each other, the ports VOUT+ are connected to each other, and the ports GND are connected to each other. Preferably, the number of the conversion circuits is two, and the two conversion circuits work staggered by 180 degrees.

[0033] Embodiment one

[0034] Please refer to Figure 3 As shown, a high-efficiency bridgeless interleaved Sepic power factor correction converter comprises two isolated Sepic power factor correction conversion circuits and a ramp compensation circuit. The ramp compensation technology is used to solve the zero-crossing distortion problem of the low input voltage of the converter. Meanwhile, the converter adopts interleaved parallel connection, which can improve the output power of the converter and reduce the output voltage and current ripple of the converter. The efficiency of the converter can be as high as 98%, the input current harmonic can be lower than 3%, and the PF value can be as high as 0.99 or above.

[0035] The first path of the above-mentioned bridgeless interleaved Sepic power factor correction conversion circuit includes a first energy storage inductor L21, a first MOS tube Q15, a second MOS tube Q14, a first diode D57, a second diode D58, a first energy storage capacitor C277, a second energy storage capacitor C246, a second energy storage inductor L17, a third energy storage inductor L20, and a first transformer T4 primary side. The energy storage inductor L21 is connected to the input live line and the cathode of the first diode D57 and the first energy storage capacitor C277, the source of the first MOS tube Q15 is connected to the anode of the first diode D57, the source of the second MOS tube Q14 is connected to the anode of the second diode D58, the drain of the second MOS tube Q14 is connected to the input neutral line and the cathode of the second diode D58, the second energy storage capacitor C246 is connected to the second energy storage inductor L17 and the third energy storage inductor L20, and the first transformer primary side center tap is connected to the second energy storage inductor L17 and the third energy storage inductor L20. The midpoint of the second energy storage inductor L17 and the third energy storage inductor L20 is connected to the source of the first MOS tube Q15, and the gates of the first MOS tube Q15 and the second MOS tube Q14 are connected to the driving circuit.

[0036] The first path of the above-mentioned high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit includes a first transformer secondary side, a third MOS tube Q16, and a fourth MOS tube Q17. The first transformer secondary side is connected to the source of the third MOS tube Q16 and the fourth MOS tube Q17. The first transformer secondary side center tap is connected to the output ground. The drain of the third MOS tube Q16 is connected to the drain of the fifth MOS tube Q17, and the output positive terminal is connected.

[0037] The second path of the above-mentioned high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit includes a fourth energy storage inductor L18, a fifth MOS tube Q8, a sixth MOS tube Q9, a third diode D35, a fourth diode D36, a third energy storage capacitor C203, a fourth energy storage capacitor C208, a fifth energy storage inductor L22, a sixth energy storage inductor L23, and a second transformer T1 primary side. The energy storage inductor L18 is connected to the input live line and the cathode of the third diode D35 and the third energy storage capacitor C203. The source of the fifth MOS tube Q18 is connected to the anode of the third diode D35, the source of the sixth MOS tube Q9 is connected to the anode of the fourth diode D36, the drain of the sixth MOS tube Q9 is connected to the input neutral line and the cathode of the fourth diode D36, the second energy storage capacitor C208 is connected to the fourth energy storage capacitor C208 and the third energy storage capacitor C203, the fifth energy storage inductor L22 is connected to the fifth energy storage inductor L22 and the sixth energy storage inductor L23, and the second transformer primary side center tap is connected to the fifth energy storage inductor L22 and the sixth energy storage inductor L23. The midpoint of the fifth energy storage inductor L22 and the sixth energy storage inductor L23 is connected to the source of the fifth MOS tube Q8, and the gates of the fifth MOS tube Q15 and the sixth MOS tube Q9 are connected to the driving circuit.

[0038] The second path of the high-efficiency bridgeless interleaved Sepic power factor correction conversion circuit comprises a second transformer secondary side, a seventh MOS tube Q10, and an eighth MOS tube Q11. The second transformer secondary side is connected to the source of the seventh MOS tube Q10 and the eighth MOS tube Q11. The center tap of the second transformer secondary side is connected to an output ground. The drains of the seventh MOS tube Q10 and the eighth MOS tube Q11 are connected and connected to an output positive terminal.

[0039] The ramp compensation circuit of the high-efficiency bridgeless interleaved Sepic power factor correction converter comprises an error amplifier U26, a comparator U27, and a compensation network C252, R261, and C247. A sampling voltage dividing resistor R248 is connected to the 2-pin of the error amplifier U26 and a differential circuit composed of a feedforward R262 and a C250. R249 is connected to ground. The 3-pin of the error amplifier U26 is connected to a given reference. The 1-pin of the output of the error amplifier U26 is connected to the 3-pin of the comparator U27. The 2-pin of the comparator U27 is connected to a sawtooth wave generator CS (generated by a chip). The output of the comparator U27 controls the drive duty cycle of the MOS tube.

[0040] Working principle:

[0041] Please refer to Figure 1 When the input is a positive half cycle, the MOS tube drive DRV_1 is high, Q15 and Q14 are simultaneously turned on, the L-L21-Q15-Q14-N loop and the C277-Q15-L17 loop are simultaneously turned on, L21 and L17 store energy, when the MOS tube drive DRV_1 is low, the L-L21-C277-T4A-Q14(D58)-N loop and the L17-T4-A loop are simultaneously turned on. At this time, the input and L21 supply power to the load, and C277 is also charged. The energy stored in C277 is transferred to L17 when the drive DRV_1 is high. At this time, the secondary side transformer T4 discharges to the load through Q16. When Q16 is turned on, the synchronous rectification function is realized, and the conversion efficiency is improved.

[0042] When the input is a negative half cycle, the MOS tube drive DRV_1 is high, Q15 and Q14 are simultaneously turned on, the N-Q14-Q15-L21-L loop and the C246-Q14-L20 loop are simultaneously turned on, L21 and L20 store energy, when the MOS tube drive DRV_1 is low, the N-C246-T4A-Q15(D57)-L21-L loop and the L20-T4-A loop are simultaneously turned on. At this time, the input and L21 supply power to the load, and C246 is also charged. The energy stored in C246 is transferred to L20 when the drive DRV_1 is high. At this time, the secondary side transformer T4 discharges to the load through Q17. When Q17 is turned on, the synchronous rectification function is realized, and the conversion efficiency is improved.

[0043] Referring to Figure 2 , the voltage compensator, high efficiency no bridge interleave Sepic power factor correction conversion electric output voltage by voltage divider resistor R248, R249 and feedforward R262, C250 handle after, access error amplifier inverting terminal compared with given reference, error signal after the compensation network of C247, C252, R261 generates, it is compared with sawtooth wave CS output MOS pipe duty cycle drive pulse.

[0044] This converter second road operation, only and the first road interleave 180 degrees work, its principle is completely identical, here no longer repeat.

[0045] The above-mentioned high efficiency no bridge interleave Sepic power factor correction converter can ensure the continuity of input current, thereby reducing electromagnetic interference, since the converter is only a single-stage circuit, the efficiency can be as high as 98%, the input current harmonic can be lower than 3%, and the PF value can be as high as 0.99 or more. The output is easily electrically isolated, which makes the whole converter safe and stable, suitable for charging piles or some intelligent power distribution systems, and has perfect protection function, high circuit reliability, simple software control, low cost and other advantages.

[0046] Although the embodiments of the present application have been disclosed as above, it is not limited to the application listed in the specification and the embodiments, it can be fully applied to various fields suitable for the present application, and for those skilled in the art, other modifications can be easily realized, therefore, the present application is not limited to specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

Claims

1. A Sepic power factor correction converter characterized by: The transformer T4 pin 5 connects the MOS tube Q17 source, the transformer T4 pin 6 connects the transformer T4 pin 7, the capacitor C305 one end and the port GND, the transformer T4 pin 8 connects the MOS tube Q16 source, the MOS tube Q16 drain connects the MOS tube Q17 drain, the capacitor C301 one end and the port VOUT+, the capacitor C301 other end connects the capacitor C305 other end. The number of the conversion circuit is multiple, the port L of multiple conversion circuits is connected with each other, the port N is connected with each other, the port VOUT+ is connected with each other, the port GND is connected with each other.

2. A Sepic power factor correction converter according to claim 1, characterized in that: The number of the conversion circuit is two, two conversion circuits stagger 180 degrees work.

3. A Sepic power factor correction converter according to claim 2, characterized by: The port L and the port N connect the mains, the port VOUT+ connects the load or battery.

4. A Sepic power factor correction converter according to claim 1, characterized by: The MOS tube Q16 gate connects the resistance R245 one end and the resistance R242 one end, the resistance R245 other end connects the diode D63 positive end, the resistance R242 other end and the diode D63 negative end connect the port DRV_4; 5. A Sepic power factor correction converter according to claim 1, characterized by: The MOS tube Q17 gate connects the resistance R236 one end and the resistance R237 one end, the resistance R237 other end connects the diode D61 positive end, the resistance R236 other end and the diode D61 negative end connect the port DRV_3; The MOS tube Q15 gate connects the resistance R250 one end, the resistance R256 one end and the resistance R257 one end, the resistance R257 other end connects the MOS tube Q15 source, the resistance R256 other end connects the diode D21 positive end, the resistance R250 other end and the diode D21 negative end connect the port DRV_1; ​ One end of resistance R258, one end of resistance R259 and one end of resistance R260 are connected to the gate of MOS transistor Q14, the other end of resistance R260 is connected to the drain of MOS transistor Q14, the other end of resistance R259 is connected to the positive end of diode D24, the other end of resistance R258 and the negative end of diode D24 are connected to port DRV_1; The port DRV_1, the port DRV_3 and the port DRV_4 are connected to a controller.

6. A Sepic power factor correction converter according to claim 1, characterized by: The converter further comprises a compensation circuit, the compensation circuit comprises port V_COMP, pin 1 of comparator U27 is connected to the port V_COMP, pin 2 of the comparator U27 is connected to port CS, pin 3 of the comparator U27 is connected to pin 1 of amplifier U26, one end of capacitor C252 and one end of capacitor C247, the other end of capacitor C252 is connected to one end of resistance R261, pin 2 of the amplifier U26 is connected to the other end of resistance R261, the other end of capacitor C247, one end of resistance R249, one end of resistance R248 and one end of capacitor C250, the other end of resistance R249 is connected to port GND, the other end of capacitor C250 is connected to one end of resistance R262, the other end of resistance R248 and the other end of resistance R262 are connected to port VOUT+, pin 3 of the amplifier U26 is connected to one end of capacitor C245 and port VREF, the other end of capacitor C245 is connected to port GND.

7. A Sepic power factor correction converter as claimed in claim 6, characterized in that: The port VREF is connected to a 1.5V power supply.

8. A Sepic power factor correction converter according to claim 6, characterized by: The port V_COMP is connected to a feedback pin of the controller, the port CS is connected to a reference pin of the controller, the controller is connected to the gate of MOS transistor Q14, the gate of MOS transistor Q15, the gate of MOS transistor Q16 and the gate of MOS transistor Q17.

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