TMBS semiconductor device structure with ultra-low voltage drop
By employing a double-layer epitaxial structure and superjunction array design in TMBS devices, the problem of low on-resistance and high voltage withstand capability of existing TMBS devices is solved, achieving ultra-low voltage drop and improved voltage withstand capability, making them suitable for semiconductor manufacturing processes.
Patent Information
- Application Number
- CN202423175345.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-23
AI Technical Summary
While improving the withstand voltage of existing TMBS devices, the on-resistance increases, making it difficult to reduce the on-resistance without increasing the difficulty of the manufacturing process and the cost.
A dual-layer epitaxial structure is adopted, with a superjunction array set in the lower first conductivity type epitaxial layer. Depletion is achieved by staggered second conductivity type pillars and first conductivity type pillars. Combined with trench structure and polysilicon gate, an ultra-low voltage drop TMBS semiconductor device structure is formed.
Without increasing the difficulty and cost of existing processes, the device's voltage withstand capability is improved, on-resistance and power loss are reduced, it is compatible with existing semiconductor manufacturing processes, and it is easy to mass-produce.
Smart Images
Figure CN223568305U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The patent relates to the design improvement of TMBS semiconductor devices, in particular to a TMBS semiconductor device structure with ultra-low voltage drop. BACKGROUND
[0002] In order to improve the performance of TMBS devices, the planar barrier area is usually increased or the planar barrier density per unit area is increased, so as to achieve the purpose of reducing the forward voltage drop. The common TMBS devices at present are all trench gate type structures for voltage resistance, and planar barriers for current passing, as shown in the drawing, the planar barrier has limited improvement in barrier density. Figure 1
[0003] The common trench gate type TMBS devices at present also increase the epitaxial layer resistivity and thickness, and increase the trench depth to improve the voltage resistance, which will result in high on-resistance.
[0004] In summary, how to further increase the voltage resistance of TMBS devices while reducing the on-resistance is a technical problem to be solved. CONTENT OF THE INVENTION
[0005] In view of the problems mentioned in the technical background, the purpose of the patent is to provide a TMBS semiconductor device structure with ultra-low voltage drop, which can effectively solve the problem of low voltage resistance and large on-resistance of the trench gate type structure.
[0006] The technical scheme of the present application is as follows: a TMBS semiconductor device with ultra-low voltage drop, from top to bottom, is provided with an upper first conductive type epitaxial layer, a lower first conductive type epitaxial layer containing a super junction array, and a first conductive type substrate, the super junction array includes second conductive type columns and first conductive type columns arranged alternately, the upper first conductive type epitaxial layer is provided with a trench structure, the bottom of the trench structure is connected with the top of the second conductive type column in the super junction array through the upper first conductive type epitaxial layer; further comprising an internal surface in each trench structure forming a gate oxide layer, and a polysilicon gate filled in each trench structure forming the gate oxide layer; a barrier alloy on the surface of the upper first conductive type epitaxial layer; a front metal layer on the surface of the barrier alloy; and a back metal layer on the back surface of the first conductive type substrate.
[0007] As a preferred, the bottom of the trench structure extends into the lower first conductive type epitaxial layer, and the distance from the surface of the lower first conductive type epitaxial layer is 0.2um-0.5um.
[0008] The TMBS semiconductor device structure with ultra-low voltage drop has the following advantages:
[0009] 1) The TMBS semiconductor device structure of the present application has the characteristics that a double epitaxial layer (a lower first conductive type epitaxial layer and an upper first conductive type epitaxial layer) is arranged through an epitaxial growth process, and the double epitaxial layer can realize different device functions;
[0010] 2) The super junction array (second conductive type columns and first conductive type columns are arranged at intervals) is realized in the lower first conductive type epitaxial layer, the second conductive type columns and the first conductive type columns are mutually depleted, so as to improve the withstand voltage capacity of the lower first conductive type epitaxial layer; meanwhile, in the case of the same withstand voltage capacity, the resistivity of the lower first conductive type epitaxial layer where the super junction array is located can be very small, and thus the on-state voltage drop of the entire TMBS device can be reduced;
[0011] 3) In the case of the same withstand voltage, the gate oxide layer can be thinner (for example, in the case of a 45V TMBS device, the thickness of the gate oxide layer can be reduced from 1500A to 800A), the junction capacitance of the device is smaller, and the power loss is smaller;
[0012] 4) The process manufacturing method of the present application is compatible with the existing widely used semiconductor manufacturing technology process, and is beneficial to popularization and mass production. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 It is a common TMBS device structure
[0014] Figure 2 It is a structure diagram of the present application Figure 1 ;
[0015] Figure 3 It is a diagram of the preparation process of the present application Figure 1 ;
[0016] Figure 4 It is a diagram of the preparation process of the present application Figure 2 ;
[0017] Figure 5 It is a diagram of the preparation process of the present application Figure 3 ;
[0018] Figure 6 It is a diagram of the preparation process of the present application Figure 4 ;
[0019] Figure 7 It is a diagram of the preparation process of the present application Figure 5 ;
[0020] Figure 8 It is a diagram of the preparation process of the present application Figure 6 .
[0021] Reference numerals: 1. Substrate of first conductivity type; 2. Lower epitaxial layer of first conductivity type; 3. Pillar of second conductivity type; 4. Upper epitaxial layer of first conductivity type; 5. Trench structure; 6. Gate oxide layer; 7. Polysilicon gate; 8. Barrier alloy; 9. Front metal layer; 10. Back metal layer; 11. Pillar of first conductivity type. Detailed Implementation
[0022] like Figure 2 As shown, the ultra-low voltage drop TMBS semiconductor device structure of this utility model includes a first conductivity type substrate 1, a lower first conductivity type epitaxial layer 2 grown on the surface of the first conductivity type substrate 1, and a plurality of superjunction arrays arranged alternately by second conductivity type pillars 3 and first conductivity type pillars 11 in the lower first conductivity type epitaxial layer 2.
[0023] An upper first conductivity type epitaxial layer 4 is grown on the surface of the lower first conductivity type epitaxial layer 2. The upper first conductivity type epitaxial layer 4 has a strip-shaped trench structure, which includes multiple trench structures 5.
[0024] The trench structure 5 passes through the upper first conductive type epitaxial layer 4 and is connected to the second conductive type pillar 3 in the lower first conductive type epitaxial layer 2. The bottom of the trench structure 5 extends into the lower first conductive type epitaxial layer 2 and is 0.2um-0.5um away from the surface of the lower first conductive type epitaxial layer 2.
[0025] A gate oxide layer 6 is formed on the inner surface of each of the trench structures 5, and a polysilicon gate 7 is filled in each of the trench structures 5 in which the gate oxide layer 6 is formed. Ti metal is sputtered onto the surfaces of the polysilicon gate 7, the gate oxide layer 6, and the upper first conductivity type epitaxial layer 4, and a Schottky metal contact is formed under pure N2 annealing to generate a barrier alloy 8. A front metal layer 9 covers the surface of the barrier alloy 8, and the front metal layer 9 leads out the positive electrode. A back metal layer 10 is formed on the back side of the first conductivity type substrate 1, and the back metal layer 10 leads out the negative electrode.
[0026] The fabrication method for the ultra-low voltage drop TMBS semiconductor structure with the above structure, using a deep trench epitaxial filling process, includes the following steps:
[0027] Step a, such as Figure 3 As shown, a first conductivity type substrate 1 (N-type substrate) is selected, and an epitaxial process is used to grow a lower first conductivity type epitaxial layer 2 (lower N-type epitaxial layer) on the upper surface of the first conductivity type substrate 1 (N-type substrate).
[0028] Step b, as follows Figure 4As shown, a hard mask layer is deposited on the lower first conductivity type epitaxial layer 2 (lower N-type epitaxial layer), and the hard mask layer is selectively masked and etched to form a plurality of hard mask first windows and hard mask second windows for masking. Then, a deep trench is formed by a deep trench etching process.
[0029] Step c: A second conductivity type epitaxial layer (P-type epitaxial layer) is grown in the deep trench using an epitaxial process. Then, the excess second conductivity type epitaxial layer (P-type epitaxial layer) on the surface is removed by a chemical mechanical polishing process, resulting in a second conductivity type pillar 3 (P-type pillar) and a first conductivity type pillar 11 (N-type pillar) located between the second conductivity type pillar 3 (P-type pillar). The second conductivity type pillar 3 (P-type pillar) and the first conductivity type pillar 11 (N-type pillar) are arranged alternately to form a superjunction structure.
[0030] Step d, as follows Figure 5 As shown, an upper epitaxial layer 4 (upper N-type epitaxial layer) of the first conductivity type is grown on the surface of the lower first conductivity type epitaxial layer 2 (lower N-type epitaxial layer).
[0031] Step e, as Figure 6 As shown, a hard mask layer is deposited on the upper first conductivity type epitaxial layer 4 (upper N-type epitaxial layer), and the hard mask layer is selectively masked and etched to form multiple hard mask first windows and hard mask second windows for masking. Then, a trench structure 5 is formed by trench etching process. The trench structure 5 passes through the upper first conductivity type epitaxial layer 4 and is connected to the second conductivity type pillar 3 in the lower first conductivity type epitaxial layer 2. The bottom of the trench structure 5 extends into the lower first conductivity type epitaxial layer 2 and is 0.2um-0.5um away from the surface of the lower first conductivity type epitaxial layer 2.
[0032] Step f, as follows Figure 7 As shown, a gate oxide layer 6 is formed using a deposition process. The gate oxide layer 6 is formed on the side and bottom surfaces of the trench structure 5.
[0033] Step g: Polysilicon deposition is performed to form a polysilicon gate 7, which is located in a trench structure 5 in which a gate oxide layer 6 is formed on the surface. Then, polysilicon etch-back is performed so that the top surface of the polysilicon gate 7 after etch-back is lower than the top of the trench structure 5.
[0034] Step h, such as Figure 8 As shown, Ti metal is sputtered onto the surfaces of the polysilicon gate 7, the gate oxide layer 6, and the upper first conductivity type epitaxial layer 4 (upper N-type epitaxial layer), and Schottky metal contacts are formed under pure N2 annealing to generate barrier alloy 8.
[0035] Step i, sputtering ALSICU front metal layer 9 above barrier alloy 8, and using photolithography to etch the ALSICU front metal layer 9 to form a positive electrode;
[0036] Step j, as shown in the drawings, back-thinning the first conductive type substrate 1 (N-type substrate), and forming a TI / NIV / Ag back metal layer 10 on the back of the first conductive type substrate 1 (N-type substrate) after thinning, and the back TI / NIV / Ag back metal layer 10 leads out a negative electrode. Figure 1
[0037] Taking 45V TMBS as an example:
[0038] The conventional 45V TMBS has an epitaxial layer resistivity of 0.45Ω and a thickness of 6um, the utility model sets the lower first conductive type epitaxial layer 2 (lower N-type epitaxial layer) containing the super junction array under the upper first conductive type epitaxial layer 4 (upper N-type epitaxial layer), improves the withstand voltage of the upper first conductive type epitaxial layer 4 (upper N-type epitaxial layer), and therefore, the upper first conductive type epitaxial layer 4 (upper N-type epitaxial layer) has a smaller resistivity of 0.35Ω and a thickness of 2.5um, compared with the conventional one, under the same withstand voltage, the epitaxial layer has a smaller resistivity and thickness, and the on-state voltage drop of the whole TMBS device is smaller.
[0039] The utility model can make the thickness and resistivity of the lower first conductive type epitaxial layer 2 (lower N-type epitaxial layer) and the upper first conductive type epitaxial layer 4 (upper N-type epitaxial layer) different according to the size of the device driving voltage in the manufacturing process, the greater the device driving voltage, the greater the thickness and resistivity of the epitaxial layer; the width of the second conductive type column 3 (P-type column) arranged at intervals also changes according to the size of the device voltage.
[0040] In summary, the TMBS semiconductor device combined with the super junction structure can break through the performance of the existing TMBS structure, has a TMBS semiconductor device structure with higher barrier density per unit area, and can manufacture the TMBS semiconductor device with ultra-low voltage drop without increasing the difficulty of the existing process and manufacturing cost.
[0041] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the utility model, and the scope of the utility model is defined by the appended claims and their equivalents.
Claims
1. A TMBS semiconductor structure with ultra-low voltage drop, characterized in that, The structure consists of an upper first conductivity type epitaxial layer (4), a lower first conductivity type epitaxial layer (2) containing a superjunction array, and a first conductivity type substrate (1) arranged sequentially from top to bottom. The superjunction array includes staggered second conductivity type pillars (3) and first conductivity type pillars (11). The upper first conductivity type epitaxial layer (4) has a trench structure (5). The bottom of the trench structure (5) passes through the upper first conductivity type epitaxial layer (4) and is connected to the top of the second conductivity type pillars (3) in the superjunction array. The structure also includes a gate oxide layer (6) formed on the inner surface of each trench structure (5), and a polysilicon gate (7) filled in each trench structure (5) forming the gate oxide layer (6). A barrier alloy (8) is located on the surface of the upper first conductivity type epitaxial layer (4). A front metal layer (9) is located on the surface of the barrier alloy (8). A back metal layer (10) is located on the back of the first conductivity type substrate (1).
2. The ultra-low voltage drop TMBS semiconductor structure as described in claim 1, characterized in that, The bottom of the trench structure (5) extends into the lower first conductive type epitaxial layer (2) and the distance from the surface of the lower first conductive type epitaxial layer (2) is 0.2um-0.5um.