High-speed communication core board based on ARM and FPGA
By connecting the ARM and FPGA core boards through PCIe gold fingers and slots, and controlling the power supply using PCIe power circuitry, the problems of slow communication speed and high power consumption are solved, achieving high-speed data transmission and low power consumption.
Patent Information
- Application Number
- CN202423276406.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-30
AI Technical Summary
The existing communication speed between ARM core boards and FPGA core boards is slow, and the continued power supply when the connection is disconnected results in high power consumption.
The ARM core board and FPGA core board are connected by PCIe gold fingers and PCIe slots. The power supply is controlled by the PCIe power circuit to improve the data transmission speed and automatically cut off the power supply to reduce power consumption when the connection is disconnected.
It improves data transmission speed, expands application scenarios, and reduces overall power consumption by controlling power supply methods, thus saving energy.
Smart Images
Figure CN223582483U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to core board technical field especially is related to a high speed communication core board based on ARM and FPGA. BACKGROUND
[0002] The core board is a computer module, which is composed of a processor or a microcontroller, a memory, a storage, a power management and a circuit board, and combines an operating system to form a minimized computer system. According to the architecture of the processor, the core board is mainly divided into an ARM core board and an FPGA core board at present. The ARM core board is good at system flow control, human-computer interaction and external communication, while the FPGA core board is good at high-speed data processing and parallel computing. With the development of science and technology industry, it is difficult for a single core board to meet the functional requirements of industrial applications, especially in the fields of video processing, automatic driving, intelligent medical treatment and energy power. Therefore, it is often necessary to use the ARM core board and the FPGA core board at the same time to integrate the advantages of both. However, the communication connection between the two core boards is mainly established through SPI, I2C and SDIO. The speed of these interfaces is relatively low, which cannot meet the needs of high-speed communication occasions, limits the comprehensive operation performance of the core board, and the power supply between the traditional ARM core board and the FPGA core board cannot be disconnected. When the ARM core board and the FPGA core board are disconnected, the power supply is still maintained, which leads to high power consumption and high energy consumption. Therefore, it is necessary to improve. SUMMARY
[0003] In view of the defects in the prior art, the utility model aims at providing a high-speed communication core board based on ARM and FPGA, which establishes a connection between the ARM core board and the FPGA core board, improves the data transmission speed between the ARM core board and the FPGA core board, expands the application scenarios, and reduces the power consumption.
[0004] In order to achieve the above-mentioned purpose, the utility model adopts the technical scheme of a high-speed communication core board based on ARM and FPGA, which comprises an ARM core board, an FPGA core board and a PCIe power circuit. The FPGA core board is provided with a PCIe gold finger, the ARM core board is provided with a PCIe slot, the PCIe gold finger is plugged and matched with the PCIe slot, the ARM core board is provided with an ARM main chip,
[0005] The PCIe power supply circuit includes a 3V3 power supply circuit and a 12V power supply circuit, the input ends of the 3V3 power supply circuit and the 12V power supply circuit are connected with the 12V power supply end respectively, the VCC3V3_PCIEx4 output end of the 3V3 power supply circuit and the VCC12V_PCIEx4 output end of the 12V power supply circuit are connected with the PCIe slot respectively, and the control ends of the 3V3 power supply circuit and the 12V power supply circuit are connected with the PCIEx4_PWR_EN pin of the ARM main chip of the ARM core board.
[0006] In a further technical solution, the 3V3 power supply circuit includes a power conversion chip U28, an inductor L17, a resistor R252, a resistor R251, a resistor R250, a resistor R249, a capacitor C195, a capacitor C196, a capacitor C179, a capacitor C194, a capacitor C180, a capacitor C193,
[0007] The VIN pin of the power conversion chip U28 is connected with the first end of the capacitor C196, the first end of the capacitor C195 and the 12V power supply end respectively, the EN pin of the power conversion chip U28 is connected with the first end of the resistor R252 and the first end of the resistor R251 respectively, the second end of the resistor R251 is connected with the PCIEx4_PWR_EN pin of the ARM main chip, the BOOT pin of the power conversion chip U28 is connected with the first end of the capacitor C179, the SW pin of the power conversion chip U28 is connected with the second end of the capacitor C179 and the first end of the inductor L17 respectively, the FB pin of the power conversion chip U28 is connected with the first end of the resistor R250, the first end of the resistor R249 and the first end of the capacitor C194 respectively, the second end of the inductor L17, the second end of the capacitor C194, the second end of the resistor R249, the first end of the capacitor C180 and the first end of the capacitor C193 are connected with the VCC3V3_PCIEx4 output end respectively, and the second end of the capacitor C195, the second end of the capacitor C196, the GND pin of the power conversion chip U28, the second end of the resistor R252, the second end of the resistor R250, the second end of the capacitor C180 and the second end of the capacitor C193 are grounded respectively.
[0008] In a further technical solution, the model of the power conversion chip U28 is ASP9135ZC-R.
[0009] In a further technical solution, the 12V power supply circuit includes a MOS tube Q30, a triode Q31, a resistor R255, a resistor R256, a resistor R257, a capacitor C197, a capacitor C198,
[0010] 12V power supply end is connected with the first end of resistor R255 and the source of MOS tube Q30, the gate of MOS tube Q30 is connected with the second end of resistor R255 and the collector of triode Q31, VCC12V_PCIEx4 output end is connected with the drain of MOS tube Q30, the first end of capacitor C197 and the first end of capacitor C198, the base of triode Q31 is connected with the first end of resistor R257 and the second end of resistor R256, the first end of resistor R256 is connected with the PCIEx4_PWR_EN pin of ARM main chip, the emitter of triode Q31 is connected with the second end of resistor R257 and the ground, the second end of capacitor C197 and the second end of capacitor C198 are grounded.
[0011] In the further technical scheme, the model of MOS tube Q30 is SSM3J328R-LF, and the model of triode Q31 is SS8050.
[0012] In the further technical scheme, the FPGA core board is provided with an FPGA power supply circuit, and the FPGA power supply circuit comprises a socket JACK1, a switch SW1, a fuse F1, a diode D1, a diode D4, capacitors C1, C2, C3 and C4.
[0013] The P pin of socket JACK1 is connected with the positive electrode of diode D1, the negative electrode of diode D1 is connected with the second pin of switch SW1, the third pin of SW1 is connected with the first end of fuse F1 and the negative electrode of diode D4, the positive electrode of diode D4 is connected with the VCC12V_PCIEx4 output end of 12V power supply circuit, the second end of fuse F1 is connected with the first end of capacitor C1, the first end of capacitor C2, the first end of capacitor C3, the first end of capacitor C4 and the FPGA core board, the G2 pin and the G3 pin of socket JACK1, the second end of capacitor C1, the second end of capacitor C2, the second end of capacitor C3 and the second end of capacitor C4 are grounded.
[0014] In the further technical scheme, the models of diode D1 and diode D4 are both SS510, and the model of fuse F1 is SMD1812P200TF16.
[0015] Further technical solutions, the FPGA core board is provided with an FPGA main chip and a crystal oscillator circuit, the FPGA main chip is provided with a GTP high-speed transceiver, the crystal oscillator circuit includes a crystal oscillator U12, an inductor L8, a resistor R66, a capacitor C165, a capacitor C166 and a capacitor C167, an EN pin of the crystal oscillator U12 is connected with a second end of the resistor R66, a first end of the resistor R66 is connected with a VDD pin of the crystal oscillator U12, a first end of the capacitor C165 and a first end of the inductor L8 respectively, an OUT_N pin of the crystal oscillator U12 is connected with an MGT_CLK0_N pin of the GTP high-speed transceiver, an OUT_P pin of the crystal oscillator U12 is connected with an MGT_CLK0_P pin of the GTP high-speed transceiver, a GND pin of the crystal oscillator U12 is grounded, a second end of the inductor L8, a first end of the capacitor C166 and a first end of the capacitor C167 are connected with a 3V3 power supply circuit through PCIe gold fingers respectively, a second end of the capacitor C165, a second end of the capacitor C166 and a second end of the capacitor C167 are grounded respectively.
[0016] Further technical solutions, the ARM core board is further provided with a clock generator, the clock generator is connected with the PCIe slot through a PCIEx4_REF_CLKP pin and a PCIEx4_REF_CLKN pin, and the clock generator is connected with the ARM main chip through a PCIE30_PORT1_REF_CLKP pin and a PCIE30_PORT1_REF_CLKN pin.
[0017] Further technical solutions, the PCIe gold finger is a PCIe x4 gold finger, and the PCIe slot is a PCIe x4 slot.
[0018] After the above structure is adopted, compared with the prior art, the application has the advantages that: the ARM core board and the FPGA core board are connected through the PCIe gold finger and the PCIe slot, the ARM core board and the FPGA core board are connected through the PCIe bus, the data transmission speed between the ARM core board and the FPGA core board is improved, and the application scenario is expanded; the FPGA core board is powered through the PCIe power supply circuit, the ARM core board controls the opening and closing and power-on timing of the PCIe power supply circuit, when the FPGA core board is disconnected from the ARM core board or communication is disconnected, the PCIe power supply circuit stops power supply, so as to reduce power consumption and save energy; when the FPGA core board and the ARM core board communicate, the FPGA core board does not need independent power supply, and only needs to output 12V voltage through the PCIe power supply circuit to supply power to the FPGA core board, when the FPGA core board and the ARM core board are disconnected or communicate, the FPGA core board is directly independently powered by an external power supply through the FPGA power supply circuit, so that it can independently run, and power consumption is further reduced. BRIEF DESCRIPTION OF DRAWINGS
[0019] The utility model is further illustrated below in combination with the drawings and embodiments.
[0020] Figure 1 The circuit block diagram of the utility model is as shown in the figure;
[0021] Figure 2 The circuit diagram of the 3V3 power supply circuit of the utility model is as shown in the figure;
[0022] Figure 3 The circuit diagram of the 12V power supply circuit of the utility model is as shown in the figure;
[0023] Figure 4 The circuit block diagram of the FPGA power supply circuit of the utility model is as shown in the figure;
[0024] Figure 5 The circuit diagram of the FPGA power supply circuit of the utility model is as shown in the figure;
[0025] Figure 6 The circuit diagram of the crystal oscillator circuit of the utility model is as shown in the figure;
[0026] Figure 7 The circuit diagram of the GTP high-speed transceiver of the utility model is as shown in the figure;
[0027] Figure 8 The circuit diagram of the PCIe gold finger of the utility model is as shown in the figure;
[0028] Figure 9 The circuit diagram of the ARM main chip and PCIe slot connection part of the utility model is as shown in the figure;
[0029] Figure 10 The circuit diagram of the PCIe slot of the utility model is as shown in the figure. DETAILED DESCRIPTION
[0030] The following is only the preferred embodiment of the utility model, and does not limit the protection scope of the utility model.
[0031] A high-speed communication core board based on ARM and FPGA, like Figures 1 to 10As shown, including ARM core board, FPGA core board and PCIe power circuit, the FPGA core board is provided with PCIe golden finger, the ARM core board is provided with PCIe slot, the PCIe golden finger is matched with the PCIe slot, the ARM core board is provided with ARM main chip, the PCIe power circuit includes 3V3 power supply circuit and 12V power supply circuit, the input end of 3V3 power supply circuit and 12V power supply circuit is connected with 12V power supply end respectively, the VCC3V3_PCIEx4 output end of 3V3 power supply circuit and the VCC12V_PCIEx4 output end of 12V power supply circuit are connected with PCIe slot respectively, the control end of 3V3 power supply circuit and 12V power supply circuit is connected with the PCIEx4_PWR_EN pin of ARM main chip of the ARM core board respectively.The conventional ARM core board and FPGA core board are connected through SPI, I2C, SDIO and the like, its transmission speed is slow, when not communicating with each other, the power supply cannot be cut off, the power consumption is high, and the PCIe golden finger and the PCIe slot are used to connect the ARM core board and the FPGA core board in the utility model, the ARM core board and the FPGA core board are connected through the PCIe bus, the data transmission speed between the ARM core board and the FPGA core board is improved, and the application scenarios are expanded, the FPGA core board is powered through the PCIe power circuit, the ARM core board controls the opening and closing and power-on timing of the PCIe power circuit, when the FPGA core board is disconnected with the ARM core board or communication is disconnected, the PCIe power circuit stops power supply, so as to reduce the power consumption and save energy.
[0032] Specifically, as Figure 2As shown, the 3V3 power supply circuit includes a power conversion chip U28, an inductor L17, a resistor R252, a resistor R251, a resistor R250, a resistor R249, a capacitor C195, a capacitor C196, a capacitor C179, a capacitor C194, a capacitor C180, and a capacitor C193. The VIN pin of the power conversion chip U28 is connected to the first end of the capacitor C196, the first end of the capacitor C195, and the 12V power supply end respectively. The EN pin of the power conversion chip U28 is connected to the first end of the resistor R252 and the first end of the resistor R251 respectively. The second end of the resistor R251 is connected to the PCIEx4_PWR_EN pin of the ARM main chip. The BOOT pin of the power conversion chip U28 is connected to the first end of the capacitor C179. The SW pin of the power conversion chip U28 is connected to the second end of the capacitor C179 and the first end of the inductor L17 respectively. The FB pin of the power conversion chip U28 is connected to the first end of the resistor R250, the first end of the resistor R249, and the first end of the capacitor C194 respectively. The second end of the inductor L17, the second end of the capacitor C194, the second end of the resistor R249, the first end of the capacitor C180, and the first end of the capacitor C193 are connected to the VCC3V3_PCIEx4 output end respectively. The second end of the capacitor C195, the second end of the capacitor C196, the GND pin of the power conversion chip U28, the second end of the resistor R252, the second end of the resistor R250, the second end of the capacitor C180, and the second end of the capacitor C193 are grounded respectively. By connecting the external 12V power supply to the 3V3 power supply circuit, when the ARM main chip outputs a high level using one GPIO signal PCIEx4_PWR_EN, the voltage of PCIEx4_PWR_EN is 3.3V. PCIEx4_PWR_EN is divided by the resistor R252 and the resistor R251. At this time, the voltage of the EN pin of the power conversion chip U28 is 3V, which is higher than the opening voltage threshold 1.2V of the power conversion chip U28, so as to open the power conversion chip U28 to output 3.3V voltage, so that the voltage of the VCC3V3_PCIEx4 output end is 3.3V.
[0033] When the ARM main chip controls PCIEx4_PWR_EN to output a low level, the voltage output by PCIEx4_PWR_EN is 0V. At this time, the voltage of the EN pin of the power conversion chip U28 is 0V, which is lower than the opening voltage threshold 1.2V of the power conversion chip U28, so as to close the power conversion chip U28 to make the voltage of the VCC3V3_PCIEx4 output end be 0V, thereby automatically cutting off the 3.3V power supply when disconnecting the connection or communication between the FPGA core board and the ARM core board, so as to reduce the power consumption.
[0034] Specifically, the model of the power conversion chip U28 is ASP9135ZC-R.
[0035] Specifically, as shown in Figure 3 the 12V power supply circuit includes a MOS tube Q30, a triode Q31, a resistor R255, a resistor R256, a resistor R257, a capacitor C197, and a capacitor C198. The 12V power supply end is connected with the first end of the resistor R255 and the source of the MOS tube Q30. The gate of the MOS tube Q30 is connected with the second end of the resistor R255 and the collector of the triode Q31. The VCC12V_PCIEx4 output end is connected with the drain of the MOS tube Q30, the first end of the capacitor C197, and the first end of the capacitor C198. The base of the triode Q31 is connected with the first end of the resistor R257 and the second end of the resistor R256. The first end of the resistor R256 is connected with the PCIEx4_PWR_EN pin of the ARM main chip. The emitter of the triode Q31 is connected with the second end of the resistor R257 and the ground. The second end of the capacitor C197 and the second end of the capacitor C198 are grounded. A switch circuit is formed by the MOS tube Q30 and the triode Q31. When the ARM main chip controls the PCIEx4_PWR_EN to output a high level, the base voltage of the triode Q31 is 0.7V. At this time, the triode Q31 is turned on, the gate voltage of the MOS tube Q30 is pulled down to 0V, and the MOS tube Q30 is turned on, so that the voltage of the VCC12V_PCIEx4 output end is 12V.
[0036] When the ARM main chip controls the PCIEx4_PWR_EN to output a low level, the triode Q31 is not turned on, so that the MOS tube Q30 is not turned on, so that the voltage of the VCC12V_PCIEx4 output end is 0V. Thus, when the connection or communication between the FPGA core board and the ARM core board is disconnected, the 12V power supply is automatically cut off, so as to reduce the power consumption.
[0037] Specifically, the model of the MOS tube Q30 is SSM3J328R-LF, and the model of the triode Q31 is SS8050. The MOS tube Q30 and the triode Q31 are used to control the opening and closing of the VCC12V_PCIEx4 output end. Compared with using an electronic switch chip, a larger current can be output while the cost is low. Moreover, the input voltage of a general electronic switch is relatively narrow. If the input voltage fluctuates greatly, the failure rate of the resistor switch will increase. The withstand voltage of the MOS tube Q30 is generally 2-3 times the input voltage, which greatly reduces the failure rate.
[0038] Specifically, as shown in Figure 4 and Figure 5As shown in the figure, the FPGA core board is provided with an FPGA power supply circuit, the FPGA power supply circuit comprises a socket JACK1, a switch SW1, a fuse F1, a diode D1, a diode D4, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, the P pin of the socket JACK1 is connected with the positive electrode of the diode D1, the negative electrode of the diode D1 is connected with the second pin of the switch SW1, the third pin of the switch SW1 is respectively connected with the first end of the fuse F1 and the negative electrode of the diode D4, the positive electrode of the diode D4 is connected with the VCC12V_PCIEx4 output end of the 12V power supply circuit, the second end of the fuse F1 is respectively connected with the first end of the capacitor C1, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4 and the FPGA core board, the G2 pin and the G3 pin of the socket JACK1, the second end of the capacitor C1, the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C4 are grounded respectively. When the FPGA core board communicates with the ARM core board through the FPGA power supply circuit, the FPGA core board does not need to be independently powered, and only needs to output 12V voltage through the PCIe power supply circuit to power the FPGA core board. When the FPGA core board is disconnected or communicates with the ARM core board, the FPGA core board is independently powered by the external power supply through the FPGA power supply circuit, so that it can independently run, and the power consumption is further reduced.
[0039] Specifically, the models of the diode D1 and the diode D4 are both SS510, and the model of the fuse F1 is SMD1812P200TF16.
[0040] Specifically, as shown in the figure, Figure 1 , Figure 6 Figure 7 and Figure 8 As shown in the figure, the FPGA core board is provided with an FPGA main chip and a crystal oscillator circuit, the FPGA main chip is provided with a GTP high-speed transceiver, the crystal oscillator circuit comprises a crystal oscillator U12, an inductor L8, a resistor R66, a capacitor C165, a capacitor C166 and a capacitor C167, the EN pin of the crystal oscillator U12 is connected with the second end of the resistor R66, the first end of the resistor R66 is respectively connected with the VDD pin of the crystal oscillator U12, the first end of the capacitor C165 and the first end of the inductor L8, the OUT_N pin of the crystal oscillator U12 is connected with the MGT_CLK0_N pin of the GTP high-speed transceiver, the OUT_P pin of the crystal oscillator U12 is connected with the MGT_CLK0_P pin of the GTP high-speed transceiver, the GND pin of the crystal oscillator U12 is grounded, the second end of the inductor L8, the first end of the capacitor C166 and the first end of the capacitor C167 are respectively connected with the 3V3 power supply circuit through the PCIe gold finger, and the second end of the capacitor C165, the second end of the capacitor C166 and the second end of the capacitor C167 are grounded respectively.
[0041] The FPGA main chip adopts a chip of model XC7A35TFGG484 of XILINX company, and the FPGA main chip has a GTP high-speed transceiver inside, and has four channels in total; the speed can support PCIe 2.0 standard, and the transmission rate of a single channel of PCIe 2.0 standard is 5GT / s, and since 8 / 10b coding is adopted, the bandwidth of a single channel is 500MB / s.
[0042] The PCIe gold finger adopts PCIe x4 gold finger, and can support transmission of 4-channel data at most; since the GTP high-speed transceiver has four GTP high-speed transceiver channels, two channels of the PCIe x4 gold finger are connected to two channels of the BANK216 of the GTP high-speed transceiver, and the other two channels of the PCIe x4 gold finger are used for other peripheral interfaces.
[0043] Two data channels of the PCIe x4 gold finger are connected to two channels of the high-speed transceiver BANK216 of the main chip, wherein the PCIE_RX0_P pin of the PCIe x4 gold finger is connected to the MGT_RX0_P pin of the FPGA main chip, the PCIE_RX0_N pin of the PCIe x4 gold finger is connected to the MGT_RX0_N pin of the FPGA main chip, the PCIE_RX1_P pin of the PCIe x4 gold finger is connected to the MGT_RX1_P pin of the FPGA main chip, the PCIE_RX1_N pin of the PCIe x4 gold finger is connected to the MGT_RX1_N pin of the FPGA main chip, the PCIE_TX0_P pin of the PCIe x4 gold finger is connected to the MGT_TX0_P pin of the FPGA main chip, the PCIE_TX0_N pin of the PCIe x4 gold finger is connected to the MGT_TX0_N pin of the FPGA main chip, the PCIE_TX1_P pin of the PCIe x4 gold finger is connected to the MGT_TX1_P pin of the FPGA main chip, and the PCIE_TX1_N pin of the PCIe x4 gold finger is connected to the MGT_TX1_N pin of the FPGA main chip.
[0044] The reference clock signal is generated by the crystal oscillator U12, and the crystal oscillator U12 generates a pair of differential clocks MGT_CLK0_P and MGT_CLK0_N, which are connected to the MGT_CLK0_P pin and the MGT_CLK0_P pin of the BANK216 of the FPGA main chip respectively.
[0045] There is also a reset signal PCIE_PERST, and since the reset signal is not a high-speed signal, the reset signal PCIE_PERST is connected to the general pin F21 of the BANK16 of the FPGA main chip.
[0046] Specifically, as Figure 1、 Figure 9 and Figure 10 As shown in the figure, the ARM core board is further provided with a clock generator, the clock generator is connected with the PCIe slot through a PCIEx4_REF_CLKP pin and a PCIEx4_REF_CLKN pin, and the clock generator is connected with the ARM main chip through a PCIE30_PORT1_REF_CLKP pin and a PCIE30_PORT1_REF_CLKN pin.
[0047] The ARM main chip adopts an RK3588 chip of Ruiyi Micro, and can support a PCIe 3.0 standard in speed; the PCIe slot is a PCIe x4 slot, the PCIe x4 slot is a 2Lanes PCIe x4 standard interface, and can communicate with a network card, a graphics card and other modules in addition to communicating with the FPGA core board. The PCIe x4 slot is equipped with necessary signals of a PCIe x4 bus, and contains signals such as power supply, reset, wake-up, hot plug and 2Lanes PCIe, so that the expansion capability of the high-speed communication core board is improved, and the high-speed communication core board is not limited to communicating with the FPGA core board.
[0048] The above is only a preferred embodiment of the present application, and for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed, and the content of the specification should not be understood as a limitation of the present application.
Claims
1. A high-speed communication core board based on ARM and FPGA, characterized in that: The PCIe power supply circuit includes a 3V3 power supply circuit and a 12V power supply circuit, the input ends of the 3V3 power supply circuit and the 12V power supply circuit are connected with the 12V power supply end respectively, the VCC3V3_PCIEx4 output end of the 3V3 power supply circuit and the VCC12V_PCIEx4 output end of the 12V power supply circuit are connected with the PCIe slot respectively, and the control ends of the 3V3 power supply circuit and the 12V power supply circuit are connected with the PCIEx4_PWR_EN pin of the ARM main chip of the ARM core board. The 3V3 power supply circuit includes a power conversion chip U28, an inductor L17, a resistor R252, a resistor R251, a resistor R250, a resistor R249, a capacitor C195, a capacitor C196, a capacitor C179, a capacitor C194, a capacitor C180 and a capacitor C193.
2. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The VIN pin of the power conversion chip U28 is connected with the first end of the capacitor C196, the first end of the capacitor C195 and the 12V power supply end respectively, the EN pin of the power conversion chip U28 is connected with the first end of the resistor R252 and the first end of the resistor R251 respectively, the second end of the resistor R251 is connected with the PCIEx4_PWR_EN pin of the ARM main chip, the BOOT pin of the power conversion chip U28 is connected with the first end of the capacitor C179, the SW pin of the power conversion chip U28 is connected with the second end of the capacitor C179 and the first end of the inductor L17 respectively, the FB pin of the power conversion chip U28 is connected with the first end of the resistor R250, the first end of the resistor R249 and the first end of the capacitor C194 respectively, the second end of the inductor L17, the second end of the capacitor C194, the second end of the resistor R249, the first end of the capacitor C180 and the first end of the capacitor C193 are connected with the VCC3V3_PCIEx4 output end respectively, and the second end of the capacitor C195, the second end of the capacitor C196, the GND pin of the power conversion chip U28, the second end of the resistor R252, the second end of the resistor R250, the second end of the capacitor C180 and the second end of the capacitor C193 are grounded. The model of the power conversion chip U28 is ASP9135ZC-R.
3. The high-speed communication core board based on ARM and FPGA according to claim 2, characterized in that: The 12V power supply circuit includes a MOS tube Q30, a triode Q31, a resistor R255, a resistor R256, a resistor R257, a capacitor C197 and a capacitor C198.
4. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The first end of the resistor R255 and the source of the MOS tube Q30 are connected with the 12V power supply end, the gate of the MOS tube Q30 is connected with the second end of the resistor R255 and the collector of the triode Q31, the drain of the MOS tube Q30, the first end of the capacitor C197 and the first end of the capacitor C198 are connected with the VCC12V_PCIEx4 output end, the first end of the resistor R256 is connected with the PCIEx4_PWR_EN pin of the ARM main chip, the base of the triode Q31 is connected with the first end of the resistor R257 and the second end of the resistor R256, the emitter of the triode Q31 is connected with the second end of the resistor R257 and the ground, and the second end of the capacitor C197 and the second end of the capacitor C198 are grounded.
5. The high-speed communication core board based on ARM and FPGA according to claim 4, characterized in that: The model of the MOS tube Q30 is SSM3J328R-LF, and the model of the triode Q31 is SS8050.
6. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The FPGA core board is provided with an FPGA power supply circuit, which comprises a socket JACK1, a switch SW1, a fuse F1, a diode D1, a diode D4, capacitors C1, C2, C3 and C4, The P pin of the socket JACK1 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the second pin of the switch SW1, the third pin of the switch SW1 is connected with the first end of the fuse F1 and the cathode of the diode D4, the anode of the diode D4 is connected with the VCC12V_PCIEx4 output end of the 12V power supply circuit, the second end of the fuse F1 is connected with the first end of the capacitor C1, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4 and the FPGA core board, the G2 pin and the G3 pin of the socket JACK1, the second end of the capacitor C1, the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C4 are grounded.
7. The high-speed communication core board based on ARM and FPGA according to claim 6, characterized in that: The models of the diode D1 and the diode D4 are both SS510, and the model of the fuse F1 is SMD1812P200TF16.
8. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The FPGA core board is provided with an FPGA main chip and a crystal oscillator circuit, the FPGA main chip is internally provided with a GTP high-speed transceiver, the crystal oscillator circuit comprises a crystal oscillator U12, an inductor L8, a resistor R66, a capacitor C165, a capacitor C166 and a capacitor C167, an EN pin of the crystal oscillator U12 is connected with a second end of the resistor R66, first ends of the resistor R66, the capacitor C165 and the inductor L8 are respectively connected with a VDD pin of the crystal oscillator U12, a first end of the capacitor C165 and a first end of the inductor L8, an OUT_N pin of the crystal oscillator U12 is connected with an MGT_CLK0_N pin of the GTP high-speed transceiver, an OUT_P pin of the crystal oscillator U12 is connected with an MGT_CLK0_P pin of the GTP high-speed transceiver, a GND pin of the crystal oscillator U12 is grounded, a second end of the inductor L8, a first end of the capacitor C166 and a first end of the capacitor C167 are respectively connected with the 3V3 power supply circuit through the PCIe gold finger, and second ends of the capacitor C165, the capacitor C166 and the capacitor C167 are respectively grounded.
9. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The ARM core board is further provided with a clock generator, the clock generator is connected with the PCIe slot through a PCIEx4_REF_CLKP pin and a PCIEx4_REF_CLKN pin, and the clock generator is connected with the ARM main chip through a PCIE30_PORT1_REF_CLKP pin and a PCIE30_PORT1_REF_CLKN pin.
10. The high-speed communication core board based on ARM and FPGA according to claim 1, characterized in that: The PCIe gold finger is a PCIe x4 gold finger, and the PCIe slot is a PCIe x4 slot.