Chip, ultrasonic fingerprint module and electronic equipment
By setting an avoidance design between the electrodes and the internal conductive layer on the chip substrate, the problem of short circuits caused by chip electrode damage is solved, improving production yield and reliability.
Patent Information
- Application Number
- CN202520269857.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2035-02-19
AI Technical Summary
The bonding pad and the trace below the pad of the chip were short-circuited due to pressure damage, causing the chip to malfunction.
Electrodes and an internal conductive layer are disposed on the substrate of the chip, so that the electrode placement area has no or partially no traces of the second conductive layer along the second direction of the substrate, ensuring that there is clearance space between the electrode and the traces below to avoid short circuits.
This improved chip production yield, reduced chip reliability risks, and ensured the stability of chip functionality.
Smart Images
Figure CN223582513U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip technical field, and particularly to a chip, an ultrasonic fingerprint module and an electronic device. BACKGROUND
[0002] Currently, a chip is generally connected to a gold finger of a circuit board through an anisotropic conductive film (ACF) bonding process, such as the connection between an ultrasonic fingerprint chip in an ultrasonic fingerprint module for fingerprint identification and a module circuit board.
[0003] The ACF bonding process needs appropriate temperature and pressure to ensure electrical connection between the electrode of the chip and the circuit board, and there is a metal trace under the electrode in the chip. If there is foreign matter such as silicon debris on the electrode of the chip, the electrode of the chip and the trace under the electrode will be short-circuited due to electrode bruising, resulting in failure of the chip function. UTILITY MODEL CONTENT
[0004] The present application provides a chip, an ultrasonic fingerprint module and an electronic device, which are used to solve the technical problem that the bonding PAD of the chip and the trace under the PAD are short-circuited due to PAD bruising, resulting in failure of the chip function.
[0005] Based on the above technical problem, the following solution is provided:
[0006] In a first aspect, a chip is provided, the chip comprising a substrate, the substrate comprising an electrode on the substrate and an internal conductive layer inside the substrate;
[0007] The internal conductive layer inside the substrate comprises a first conductive layer on a top layer and a second conductive layer below the first conductive layer, the electrode is electrically connected to the first conductive layer, the electrode is also used for electrical connection with a circuit board through an anisotropic conductive adhesive film (ACF) bonding process, the minimum distance between the edge end of the substrate provided with the electrode and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, the arrangement position area of the electrode is all or partially free of the trace of the second conductive layer in the second direction of the substrate, and the first direction is perpendicular to the second direction.
[0008] Further, the first preset distance comprises a first distance, the minimum distance between the edge end of the substrate provided with the electrode and the trace of the second conductive layer in the first direction of the substrate is the first distance, and part of the arrangement position area of the electrode is free of the trace of the second conductive layer in the second direction of the substrate.
[0009] Further, a proportion of the partial arrangement position area of the electrode to the total arrangement position area of the electrode is greater than 50%.
[0010] Further, the first preset distance includes a second distance, and a minimum distance between an edge end of the substrate provided with the electrode and a trace of the second conductive layer in a first direction of the substrate is the second distance, so that the total arrangement position area of the electrode is free of the trace of the second conductive layer in a second direction of the substrate.
[0011] Further, a minimum distance between an edge end of the substrate provided with the electrode and a trace of the first conductive layer is a second preset distance, and the second preset distance is less than the first preset distance.
[0012] Further, the circuit board includes a flexible circuit board.
[0013] Further, the chip includes an ultrasonic fingerprint chip.
[0014] In a second aspect, an ultrasonic fingerprint module is provided, and the ultrasonic fingerprint module includes an ultrasonic fingerprint chip and a circuit board.
[0015] The ultrasonic fingerprint chip includes a substrate, the substrate includes an electrode on the substrate and an internal conductive layer inside the substrate, the internal conductive layer inside the substrate includes a first conductive layer on a top layer and a second conductive layer below the first conductive layer, the electrode is electrically connected with the first conductive layer, the electrode is also used for electrical connection with the circuit board through anisotropic conductive film ACF bonding process, a minimum distance between an edge end of the substrate provided with the electrode and a trace of the second conductive layer in a first direction of the substrate is a first preset distance, and an arrangement position area of the electrode is free of the trace of the second conductive layer in a second direction of the substrate.
[0016] Further, the first preset distance includes a first distance, and a minimum distance between an edge end of the substrate provided with the electrode and a trace of the second conductive layer in a first direction of the substrate is the first distance, so that a partial arrangement position area of the electrode is free of the trace of the second conductive layer in a second direction of the substrate.
[0017] Further, a proportion of the partial arrangement position area of the electrode to the total arrangement position area of the electrode is greater than 50%.
[0018] Further, the first preset distance includes a second distance, and a minimum distance between an edge end of the substrate provided with the electrode and a trace of the second conductive layer in a first direction of the substrate is the second distance, so that the total arrangement position area of the electrode is free of the trace of the second conductive layer in a second direction of the substrate.
[0019] Further, the minimum distance between the edge end of the substrate provided with the electrode and the trace of the first conductive layer is a second preset distance, which is smaller than the first preset distance.
[0020] Further, the circuit board comprises a flexible circuit board.
[0021] In a third aspect, an electronic device is provided, which comprises the chip according to any one of the preceding aspects, or the ultrasonic fingerprint module according to any one of the preceding aspects.
[0022] In one of the above-mentioned implementations, the chip comprises a substrate, the substrate comprises an electrode on the substrate and an internal conductive layer inside the substrate; the internal conductive layer inside the substrate comprises a first conductive layer on a top layer and a second conductive layer below the first conductive layer, the electrode is electrically connected to the first conductive layer, the electrode is also used for electrical connection with a circuit board through anisotropic conductive film (ACF) bonding process, the minimum distance between the edge end of the substrate provided with the electrode and the trace of the second conductive layer in a first direction of the substrate is a first preset distance, the arrangement position area of the electrode is free of the trace of the second conductive layer in a second direction of the substrate, and the first direction is perpendicular to the second direction. It can be seen that the arrangement position area of the electrode of the chip is free of the trace of the second conductive layer in the second direction, and thus, the electrode and the trace below have an avoiding space in the second direction, so that even if the electrode of the chip is pressed, short circuit will not occur, and the subsequent chip function will not be affected, the production yield can be improved, the reliability risk of the chip is reduced, and the application value is high. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0024] Figure 1 is a cross-sectional view of the connection relationship between the chip and the circuit board and the conductive trace inside the chip substrate;
[0025] Figure 2 is a top view of the arrangement relationship between the conductive trace inside the chip substrate and the electrode of the chip;
[0026] Figure 3 is a cross-sectional view of the connection relationship between the chip and the circuit board and the conductive trace inside the chip substrate in the local avoiding mode;
[0027] Figure 4 is a top view schematic diagram of the arrangement relationship between the conductive traces inside the chip substrate and the chip electrodes in the partial avoidance mode;
[0028] Figure 5 is a sectional view schematic diagram of the connection relationship between the chip and the circuit board and the conductive traces inside the chip substrate in the full avoidance mode;
[0029] Figure 6 is a top view schematic diagram of the arrangement relationship between the conductive traces inside the chip substrate and the chip electrodes in the full avoidance mode. DETAILED DESCRIPTION
[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0031] In order to thoroughly understand the present application, detailed structures and steps will be proposed in the following description to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail as follows, however, the present application can have other implementation manners besides these detailed descriptions.
[0032] In an embodiment, a chip is provided, the chip type of which includes but is not limited to an ultrasonic fingerprint chip or other chip that is electrically connected with the gold fingers 21 of a circuit board 2 by using a substrate and ACF bonding process, and the specific chip type is not limited. The anisotropic conductive adhesive film 3 is arranged between the gold fingers 21 of the circuit board 2 and the electrodes of the chip 1, and the ACF bonding process is used to connect the electrodes between the chip 1 and the substrate 11 to conduct electricity by using conductive particles 31.
[0033] In this embodiment, the chip 1 includes a substrate 11, and the substrate 11 includes the electrodes 12 on the substrate and the internal conductive layer inside the substrate 11. The substrate 11 includes but is not limited to a silicon substrate, a silicon carbide substrate or a gallium nitride substrate, and the specific substrate is not limited. The electrodes 12 on the substrate 11 are the bonding pads on the chip, the internal conductive layer inside the substrate 11 is a metal layer inside the substrate, and the internal conductive layer inside the substrate 11 includes the required circuit layer for realizing the chip function. For example, the internal conductive layer includes a conductive layer for realizing the signal transmission and power distribution inside the chip, and the circuit function of the chip is realized by the wiring of the internal conductive layer. Exemplarily, the internal conductive layer can be made of aluminum, copper or other conductive materials, and the specific material is not limited.
[0034] The internal conductive layer inside the substrate 11 includes a first conductive layer 131 (Top Metal) on the top layer and a second conductive layer 132 below the first conductive layer 131, that is, the internal conductive layer of the substrate 11 includes a multi-layer circuit layer, wherein the uppermost conductive layer inside the substrate is denoted as the first conductive layer 131, and the conductive layer below the first conductive layer 131 is denoted as the second conductive layer 132, the electrode 12 is electrically connected with the first conductive layer 131, and the electrode 12 is also used for electrical connection with the circuit board through ACF bonding process, the circuit board refers to a module used for connecting with the electrode of the chip 1 to realize the corresponding function of the chip, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, so that the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11, and the first direction and the second direction are perpendicular to each other. That is, the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 below.
[0035] It should be understood that, as Figure 1 and Figure 2 shown, Figure 1 and Figure 2 show the structure schematic diagram when the arrangement position area of the electrode 12 has the second conductive layer 132 below, wherein, Figure 2 is a top view schematic diagram, Figure 2 the small square box line on the lower edge of the chip represents the electrode of the chip 1, and the large square box line represents the trace of the second conductive layer 132, it can be seen that the electrode 12 of the chip 1 and the trace of the second conductive layer 132 overlap in the second direction without avoiding space. As Figure 1 shown, the ACF bonding process needs appropriate temperature and pressure to ensure electrical connection, so that the gold fingers 21 of the circuit board 2 are connected with the electrodes 12 of the external connection chip 1, when there is foreign matter (including silicon debris) on the electrode 12, the circuit of the electrode 12 and the trace of the second conductive layer 132 below the electrode 12 will be short-circuited due to the pressure injury of the electrode 12, resulting in failure of the chip function. It should be noted that in some cases, the electrode 12 of the chip 1 may be normal in the pressure injury test, but the chip 1 will also trigger problems after stress or aging, thereby affecting the reliability of the chip.
[0036] Therefore, in the embodiment of the present application, the arrangement position region of the electrode 12 is partially or entirely free of the traces of the second conductive layer 132 in the second direction of the substrate 11, so that the electrode 12 and the traces of the second conductive layer 132 below have a space in the second direction, and thus, even if the electrode 12 of the chip 1 is pressed, short circuit will not occur, and the subsequent function of the chip 1 will not be affected, the production yield is improved, the reliability risk of the chip 1 is reduced, and the application value is great.
[0037] It should be noted that, in the present application, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the traces of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, and the arrangement position region of the electrode 12 is entirely or partially free of the traces of the second conductive layer 132 in the second direction of the substrate 11, which can have various implementation manners, which will be introduced below.
[0038] The first mode is shown in Figure 3 and Figure 4 As an example, the first preset distance includes a first distance, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the traces of the second conductive layer 132 in the first direction of the substrate 11 is the first distance, and part of the arrangement position region of the electrode 12 is free of the traces of the second conductive layer 132 in the second direction of the substrate 11.
[0039] This embodiment is a local trace avoidance implementation, the first preset distance includes a first distance, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the traces of the second conductive layer 132 in the first direction of the substrate 11 is the first distance, and part of the arrangement position region of the electrode 12 is free of the traces of the second conductive layer 132 in the second direction of the substrate 11, that is, part of the traces of the second conductive layer 132 below the electrode 12 avoids the arrangement position region of the electrode 12. Figure 3 and Figure 4 The electrode 12 is shown in the structure diagram of the local avoidance of the arrangement position region and the traces of the second conductive layer 132 below, wherein, Figure 4 is a schematic top view, Figure 4 The small square box line on the lower edge of the chip 1 in indicates the electrode 12 of the chip 1, and the large square box line indicates the traces of the second conductive layer 132, and it can be seen that the electrode 12 of the chip 1 and the traces of the second conductive layer 132 are locally overlapped in the second direction, and there is a local avoidance space.
[0040] The inventors discovered that when the electrodes 12 of chip 1 are connected to the circuit board via ACF bonding, foreign objects (such as silicon debris) are prone to accumulate on the electrodes 12 of chip 1, especially at the bonding points near the edges of chip 1. Therefore, if... Figure 3 As shown, in this embodiment, the minimum distance between the edge of the substrate 11 where the electrode 12 is located and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the first distance. This ensures that a portion of the area where the electrode 12 is located has no trace of the second conductive layer 132 along the second direction of the substrate 11. In other words, the trace of the second conductive layer 132 near the edge of the chip 1 where the electrode 12 is located partially avoids the electrode 12 above it. Since there is no trace below the area where foreign objects are easily dropped, even if the electrode 12 of the chip 1 is damaged, it will not affect subsequent functions. Moreover, because it is a partial avoidance method, part of the trace of the second conductive layer 132 is still located below the electrode 12, so that the trace of the second conductive layer 132 in the chip 1 does not occupy much chip space, ensuring that the chip size is not too large.
[0041] In one embodiment, the proportion of a portion of the electrode 12's arrangement area to the entire arrangement area of the electrode 12 is greater than 50%. In this embodiment, more than half of the electrode 12's arrangement area is separated from the traces of the underlying second conductive layer 132. Therefore, it can be effectively ensured that the subsequent chip function will not be affected when the electrode 12 of the chip 1 is damaged.
[0042] The second method, such as Figure 3 and Figure 4 As shown, as an example, the first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance, so that there are no traces of the second conductive layer 132 in the entire arrangement area of the electrode 12 along the second direction of the substrate 11.
[0043] This embodiment is a method of completely avoiding the traces. The first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance. This ensures that there are no traces of the second conductive layer 132 in the entire arrangement area of the electrode 12 along the second direction of the substrate 11. In other words, the traces of the second conductive layer 132 below the electrode 12 completely avoid the arrangement area of the electrode 12. Figure 5 and Figure 6 The diagram shows a structure where the arrangement area of electrode 12 and the wiring of the underlying second conductive layer 132 are completely avoided. Figure 5is a schematic view from above, Figure 5 The small square frame line on the lower end of the chip 1 in the figure indicates the electrode 12 of the chip 1, and the large square frame line above indicates the trace of the second conductive layer 132. It can be seen that the electrode 12 of the chip 1 and the trace of the second conductive layer 132 do not overlap in the second direction, and there is full avoidance space.
[0044] The inventor found that when the electrode 12 of the chip 1 is connected to the circuit board through the ACF bonding process, foreign matter (such as silicon debris) is easily deposited on the electrode 12 of the chip 1. Therefore, in this embodiment, the entire arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11. Since there is no trace below the position where foreign matter is easily deposited, even if the electrode 12 of the chip 1 is crushed, it will not affect the subsequent function. Moreover, since it is a full avoidance method, it greatly guarantees the normal function of the chip when the electrode 12 is crushed.
[0045] In an embodiment, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the trace of the first conductive layer 131 is a second preset distance, which is smaller than the first preset distance. In this embodiment, the first conductive layer 131 is a top conductive layer directly connected to the electrode 12, and the trace of the first conductive layer 131 can be arranged below the arrangement position area of the electrode 12.
[0046] In an embodiment, the circuit board includes a flexible circuit board. In other embodiments, it can also be other printed circuit boards that can be connected to the electrode 12 of the chip 1 through the ACF bonding process, and the specific embodiments of the present application are not limited.
[0047] In this embodiment, the printed circuit board connected to the electrode 12 of the chip 1 through the ACF bonding process can include a flexible circuit board or other types of printed circuit boards, which can all adopt the trace design of the internal conductive layer of the chip provided by the embodiments of the present application, thereby solving the problem of possible failure of the chip function or low production yield.
[0048] In an embodiment, the chip 1 includes an ultrasonic fingerprint chip. In this embodiment, the chip 1 provided by the embodiments of the present application includes but is not limited to an ultrasonic fingerprint chip or other biometric detection chips, and can also be other chips suitable for using the ACF bonding process, and the specific embodiments are not limited. The ultrasonic fingerprint chip refers to a chip embedded with ultrasonic fingerprint recognition technology, which can realize functions such as ultrasonic fingerprint image acquisition, feature extraction, and feature comparison of fingerprints through the ultrasonic fingerprint chip.
[0049] Through the ultrasonic fingerprint chip scheme provided in the embodiments of the present application, the minimum distance between the edge of the substrate 11 provided with the electrode 12 and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, and the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11, so that the circuit of the electrode 12 and the circuit below have a space for avoiding each other. Therefore, even if the electrode 12 of the ultrasonic fingerprint chip 1 is pressed, the subsequent chip function of the ultrasonic fingerprint chip is not affected, the production yield of the ultrasonic fingerprint chip can be improved, the reliability risk of the ultrasonic fingerprint chip can be reduced, and the ultrasonic fingerprint chip has great application value.
[0050] In an embodiment, an ultrasonic fingerprint module is provided, which includes an ultrasonic fingerprint chip 1 and a circuit board; the ultrasonic fingerprint chip includes a substrate, the substrate includes an electrode on the substrate and an internal conductive layer in the substrate, the internal conductive layer in the substrate includes a first conductive layer on a top layer and a second conductive layer below the first conductive layer, the electrode is electrically connected with the first conductive layer, the electrode is further electrically connected with the circuit board through anisotropic conductive film ACF bonding process, and the minimum distance between the edge of the substrate provided with the electrode and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, so that the arrangement position area of the electrode is free of the trace of the second conductive layer in the second direction of the substrate.
[0051] Therefore, the ultrasonic fingerprint module is provided, the anisotropic conductive film 3 is arranged between the gold fingers 21 of the circuit board 2 and the electrodes of the chip 1, and the ACF bonding process is used to connect the electrodes between the chip 1 and the substrate 11 through conductive particles 31 to conduct electricity. In the ultrasonic fingerprint module, the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11, so that the electrode 12 and the trace below have a space for avoiding each other in the second direction. Therefore, even if the electrode 12 of the chip 1 is pressed, short circuit is not caused, the subsequent chip function is not affected, the production yield is improved, the reliability risk of the chip 1 is reduced, and the ultrasonic fingerprint module has great application value.
[0052] It should be noted that in the ultrasonic fingerprint module provided in the present application, the minimum distance between the edge of the substrate 11 provided with the electrode 12 and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, and the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11, so that the arrangement position area of the electrode 12 is free of the trace of the second conductive layer 132 in the second direction of the substrate 11, which can have various implementation manners, which will be introduced below.
[0053] The first mode is as follows: Figure 3 andFigure 4 As shown, as an example, the first preset distance includes a first distance, where the minimum distance between the edge of the substrate 11 on which the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the first distance, so that the part of the arrangement area of the electrode 12 has no trace of the second conductive layer 132 along the second direction of the substrate 11.
[0054] In the ultrasonic fingerprint module provided in this embodiment, a partial routing avoidance implementation is adopted. The first preset distance includes a first distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the routing of the second conductive layer 132 in the first direction of the substrate 11 is the first distance. This makes it so that the routing of the second conductive layer 132 is not present in the part of the electrode 12 along the second direction of the substrate 11. That is, the routing of the second conductive layer 132 below the electrode 12 avoids the routing area of the electrode 12. Figure 3 and Figure 4 The diagram shows a structure where the arrangement of electrode 12 and the wiring of the underlying second conductive layer 132 are partially avoided. Figure 4 This is a top-down schematic diagram. Figure 4 The small square at the bottom edge of chip 1 represents the electrode 12 of chip 1, and the large square represents the trace of the second conductive layer 132. It can be seen that the electrode 12 and the trace of the second conductive layer 132 of chip 1 partially overlap in the second direction, with some clearance. Moreover, due to this partial clearance, part of the trace of the second conductive layer 132 is still located below the electrode 12, ensuring that the trace of the second conductive layer 132 within chip 1 does not occupy a large amount of chip space, thus keeping the chip size relatively small.
[0055] In one embodiment, the proportion of a portion of the electrode 12's arrangement area to the entire arrangement area of the electrode 12 is greater than 50%. In this embodiment, more than half of the electrode 12's arrangement area is separated from the traces of the underlying second conductive layer 132. Therefore, it can be effectively ensured that the subsequent chip function will not be affected when the electrode 12 of the chip 1 is damaged.
[0056] The second method, such as Figure 5 and Figure 6 As shown, as an example, the first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance, so that there are no traces of the second conductive layer 132 in the entire arrangement area of the electrode 12 along the second direction of the substrate 11.
[0057] The embodiment provides the ultrasonic fingerprint module, and all the wirings are avoided. The first preset distance includes a second distance. The minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the wirings of the second conductive layer 132 in the first direction of the substrate 11 is the second distance. The arrangement position region of the electrode 12 is free of the wirings of the second conductive layer 132 in the second direction of the substrate 11, that is, the wirings of the second conductive layer 132 below the electrode 12 are all avoided from the arrangement position region of the electrode 12. Figure 5 and Figure 6 The structure diagram is shown, in which the arrangement position region of the electrode 12 is free of the wirings of the second conductive layer 132 below. Figure 5 The structure diagram is shown, in which the arrangement position region of the electrode 12 is free of the wirings of the second conductive layer 132 below. Figure 5 The small square frame line on the lower edge of the chip 1 in the structure diagram represents the electrode 12 of the chip 1, and the large square frame line above represents the wirings of the second conductive layer 132. It can be seen that the electrode 12 of the chip 1 is free of the wirings of the second conductive layer 132 in the second direction, and there is a free space. Moreover, since the wirings are all avoided, the normal function of the chip can be ensured when the electrode 12 is pressed.
[0058] In an embodiment, the minimum distance between the edge end of the substrate 11 provided with the electrode 12 and the wirings of the first conductive layer 131 is a second preset distance, and the second preset distance is smaller than the first preset distance. In the embodiment, the first conductive layer 131 is a top conductive layer directly connected with the electrode 12, and the wirings of the first conductive layer 131 can be arranged below the arrangement position region of the electrode 12.
[0059] In an embodiment, the circuit board 2 in the ultrasonic fingerprint module includes a flexible circuit board. In other embodiments, the printed circuit board connected with the electrode 12 of the chip 1 through the ACF bonding process can be other printed circuit boards, and the specific embodiments are not limited.
[0060] In the embodiment, the printed circuit board connected with the electrode 12 of the chip 1 through the ACF bonding process can include a flexible circuit board or other types of printed circuit boards, and the internal conductive layer of the chip can be designed according to the embodiment, so that the problem of possible failure of the chip function or low production yield is solved, and the application scenarios of the scheme are improved.
[0061] In the ultrasonic fingerprint module provided by the embodiment, the trace of the second conductive layer 132 under the electrode 12 of the chip 1 has a minimum distance of a first preset distance in the first direction of the substrate 11, and the arrangement position area of the electrode 12 is completely or partially free of the trace of the second conductive layer 132 in the second direction of the substrate 11, so that the circuit of the electrode 12 and the circuit below have a space for avoiding each other. Therefore, even if the electrode 12 of the ultrasonic fingerprint chip 1 is pressed, the subsequent chip function of the ultrasonic fingerprint chip will not be affected, the production yield of the ultrasonic fingerprint chip can be improved, the reliability risk of the ultrasonic fingerprint chip can be reduced, and the ultrasonic fingerprint chip has great application value.
[0062] In an embodiment, the embodiment also provides an electronic device including the chip or the ultrasonic fingerprint module according to any one of the preceding embodiments. Details are not repeated here, and refer to the above embodiments.
[0063] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.
[0064] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.
Claims
1. A chip, characterized in that, The chip includes a substrate, on which electrodes are located on the substrate and an internal conductive layer is located inside the substrate; The internal conductive layer inside the substrate includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrode is electrically connected to the first conductive layer. The electrode is also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, so that the area where the electrode is disposed is wholly or partially free of traces of the second conductive layer along the second direction of the substrate. The first direction is perpendicular to the second direction.
2. The chip according to claim 1, characterized in that, The first preset distance includes a first distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the first distance, so that there is no trace of the second conductive layer in the part of the electrode's arrangement area along the second direction of the substrate.
3. The chip according to claim 2, characterized in that, The proportion of the partial arrangement area of the electrode to the total arrangement area of the electrode is greater than 50%.
4. The chip according to claim 1, characterized in that, The first preset distance includes a second distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, such that there are no traces of the second conductive layer in the entire arrangement area of the electrode along the second direction of the substrate.
5. The chip according to any one of claims 1-4, characterized in that, The minimum distance between the edge of the substrate on which the electrode is provided and the trace of the first conductive layer is a second preset distance, and the second preset distance is less than the first preset distance.
6. The chip according to any one of claims 1-4, characterized in that, The circuit board includes a flexible circuit board.
7. The chip according to any one of claims 1-4, characterized in that, The chip includes an ultrasonic fingerprint chip.
8. An ultrasonic fingerprint module, characterized in that, The ultrasonic fingerprint module includes an ultrasonic fingerprint chip and a circuit board; The ultrasonic fingerprint chip includes a substrate, on which electrodes are located and an internal conductive layer is located. The internal conductive layer includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrodes are electrically connected to the first conductive layer. The electrodes are also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate where the electrodes are located and the trace of the second conductive layer in a first direction of the substrate is a first preset distance, so that the area where the electrodes are located is entirely or partially free of traces of the second conductive layer along a second direction of the substrate.
9. The ultrasonic fingerprint module according to claim 8, characterized in that, The first preset distance includes a first distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the first distance, so that there is no trace of the second conductive layer in the part of the electrode's arrangement area along the second direction of the substrate.
10. The ultrasonic fingerprint module according to claim 9, characterized in that, The proportion of the partial arrangement area of the electrode to the total arrangement area of the electrode is greater than 50%.
11. The ultrasonic fingerprint module according to claim 8, characterized in that, The first preset distance includes a second distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, such that there are no traces of the second conductive layer in the entire arrangement area of the electrode along the second direction of the substrate.
12. The ultrasonic fingerprint module according to any one of claims 8-11, characterized in that, The minimum distance between the edge of the substrate on which the electrode is provided and the trace of the first conductive layer is a second preset distance, and the second preset distance is less than the first preset distance.
13. The ultrasonic fingerprint module according to any one of claims 8-11, characterized in that, The circuit board includes a flexible circuit board.
14. An electronic device, characterized in that, Includes the chip as described in any one of claims 1-7, or the ultrasonic fingerprint module as described in any one of claims 8-13.