Package structure including package cover having plurality of fins

Abstract

The utility model provides a packaging structure comprising a packaging cover with a plurality of fins. The packaging structure comprises a packaging substrate, an intermediate layer module located on the packaging substrate, a thermal interface material located on the intermediate layer module, a thermal interface material layer, and the packaging cover located on the intermediate layer module and the thermal interface material layer. The package cover includes a package cover leg portion attached to the package substrate, a package cover plate portion connected to the package cover leg portion, and a plurality of fins extending from the package cover plate portion to the thermal interface material layer over the interposer module.

Description

TECHNICAL FIELD

[0001] The present utility model relates to a packaging structure, and in particular to a packaging structure including a packaging lid having a plurality of fins. BACKGROUND

[0002] In electronic devices and other semiconductor components, heat can be generated during operation. Efficient dissipation of the generated heat will help maintain the performance of the electronic device and prevent overheating, which can lead to performance degradation or even permanent damage.

[0003] A packaging structure (e.g., a semiconductor package) can sometimes include a thermal interface material (TIM) layer to help dissipate heat generated in the packaging structure. The TIM layer can enhance heat transfer between two surfaces having different thermophysical properties. The TIM layer can be located, for example, between an interposer module (e.g., a package module) and a packaging lid (e.g., a heat sink). The TIM layer can improve thermal contact by filling microscopic gaps and irregularities between the interposer module and the packaging lid.

[0004] The TIM layer can include one or more metallic materials. The TIM layer can include, for example, a thermal grease or paste. The thermal grease can include, for example, a mixture of metallic particles (e.g., silver, aluminum, or copper) suspended in a silicone or hydrocarbon-based grease. The TIM layer can include a thermal adhesive that includes metallic particles mixed with an adhesive resin that solidifies after application. The TIM layer can include thermal pads that include metallic particles or metallic foils, or films that include, for example, copper or aluminum. The TIM layer can also include metal-infiltrated graphite sheets. SUMMARY

[0005] The present utility model provides a packaging structure, comprising: a packaging substrate; an interposer module located on the packaging substrate; a thermal interface material layer located on the interposer module; and a packaging lid located on the thermal interface material layer, the packaging lid comprising: a packaging lid foot portion attached to the packaging substrate; a packaging lid plate portion connected to the packaging lid foot portion; and a plurality of fins extending from the packaging lid plate portion to the thermal interface material layer above the interposer module.

[0006] The utility model provides a kind of packaging structure, comprising: packaging substrate;Interposer module, located on the packaging substrate and comprising multiple semiconductor dies;Metal thermal interface material layer, located on the interposer module;And packaging cover, located on the metal thermal interface material layer, comprising: packaging cover foot part, attached to the packaging substrate;Packaging cover plate portion, on the interposer module and connected to the packaging cover foot part;And multiple fins, from the packaging cover plate portion extends into the metal thermal interface material layer on the multiple semiconductor dies of the interposer module, wherein the multiple fins include cylindrical shape, and the end portion of the arc shape of the multiple fins is embedded into the metal thermal interface material layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] The aspects of the disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale in order to illustrate clearly the concepts. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] FIG. 1A is a vertical cross-sectional view of a packaging structure according to one or more embodiments.

[0009] FIG. 1B is a plan view (e.g., top view) of a packaging structure according to one or more embodiments.

[0010] FIG. 1C is a detailed vertical cross-sectional view of a portion of a packaging cover in a packaging structure according to one or more embodiments.

[0011] FIG. 2A shows a stamp being pressed onto a bottom surface of a packaging cover plate portion according to one or more embodiments.

[0012] FIG. 2B shows the stamp being withdrawn from the bottom surface after forming fins according to one or more embodiments.

[0013] FIG. 3A to FIG. 3E shows various protruding pads that can be used in an imprinting process according to one or more embodiments.

[0014] FIG. 4 shows a packaging cover after forming a plating layer according to one or more embodiments.

[0015] FIG. 5A is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, including a packaging substrate with upper and lower bonding pads on the packaging substrate.

[0016] FIG. 5BA vertical cross-sectional view of an intermediate structure is shown, in which a die module can be mounted on a package substrate, according to one or more embodiments.

[0017] FIG. 5C A vertical cross-sectional view of an intermediate structure is shown, in which a package underfill layer can be formed on a package substrate, according to one or more embodiments.

[0018] FIG. 5D A vertical cross-sectional view of an intermediate structure is shown, in which surface mount elements can be mounted on a package substrate, according to one or more embodiments.

[0019] FIG. 5E A vertical cross-sectional view of an intermediate structure is shown, in a first flux jetting step, according to one or more embodiments.

[0020] FIG. 5F A vertical cross-sectional view of an intermediate structure is shown, in which a TIM layer can be formed on (e.g., attached to) a die module, according to one or more embodiments.

[0021] FIG. 5G A vertical cross-sectional view of an intermediate structure is shown, in a second flux jetting step, according to one or more embodiments.

[0022] FIG. 5H A vertical cross-sectional view of an intermediate structure is shown, in which an adhesive layer and an inner adhesive layer can be applied to a package substrate, according to one or more embodiments.

[0023] FIG. 5I A vertical cross-sectional view of an intermediate structure is shown, in which a package cap can be attached to (e.g., mounted on) a package substrate, according to one or more embodiments.

[0024] FIG. 5J A vertical cross-sectional view of an intermediate structure is shown, in which a plurality of solder balls can be formed on a package substrate, according to one or more embodiments.

[0025] FIG. 6 A flowchart illustrating a method of forming a package structure is shown, according to one or more embodiments.

[0026] FIG. 7A A vertical cross-sectional view of a package structure having a first alternative design is shown, according to one or more embodiments.

[0027] FIG. 7B A perspective view of a portion of a fin in a package structure having a first alternative design is shown, according to one or more embodiments.

[0028] FIG. 7C A bottom surface of a package cap of a package structure having a first alternative design is shown, according to one or more embodiments.

[0029] FIG. 8 is a vertical cross-sectional view of a package structure having a second alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0030] The present disclosure provides a number of different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature on top of or over a second feature in the following description can include embodiments in which the first feature is formed directly contacting the second feature, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact each other. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless otherwise noted, each element having a same reference numeral is assumed to be the same as that described in relation to the embodiment of the same reference numeral.

[0032] In related package structures, a TIM (thermal interface material) layer can include, for example, a metal such as indium or gallium. In related package structures, a coefficient of thermal expansion (CTE) mismatch between a package cap and a package substrate can cause high stress in the package structure. The stress can cause internal cracks to form within the TIM layer after performing thermal cycle testing.

[0033] In one or more embodiments of the present disclosure, a package structure can include a package lid including a package lid plate portion and a plurality of fins extending from the package lid plate portion. The plurality of fins can form an innovative fin as a heat spreader of the package structure in an embodiment. The plurality of fins can enhance the mechanical structure of a TIM layer (e.g., a metal TIM layer). In one or more embodiments, the package lid can provide optimized thermal dissipation performance in the package structure. The plurality of fins can substantially increase the bonding area to enhance the structural strength and inhibit the formation of cracks in the TIM layer. In particular, internal cracks (e.g., in an indium TIM layer) can be inhibited by the plurality of fins of the package lid.

[0034] In at least one embodiment, the plurality of fins can constitute a "fin-like structure" formed over a interposer module (e.g., a chip-on-wafer region). In at least one embodiment, the TIM layer can include an indium-based material or a gallium-based material. In at least one embodiment, the TIM layer can include indium that can fill gaps between the fins. The package lid can include a surface composition (from inside to outside) including copper, nickel, and gold (or silver) or including only copper and nickel. In at least one embodiment, the package lid can include a plating layer including nickel, gold, etc. on the plurality of fins.

[0035] The interposer module can include a backside metal (BSM) layer on an upper surface of the interposer module. The package structure can also include a first intermetallic compound (IMC) layer (e.g., an indium / BSM interface) in an interface of a joint of the TIM layer and the backside metal layer. The package structure can also include a second intermetallic compound layer (e.g., an indium / plating layer interface) in an interface of a joint of the TIM layer and the package lid. Each of the first and second intermetallic compound layers can have a thickness in a range of about 0.5 pm to about 2.0 pm (e.g., about 1.0 pm). Each of the first and second intermetallic compound layers can include, for example, Au-In, Ni-In, Ni-Au-In, etc.

[0036] The interposer module can include one or more dies (e.g., semiconductor dies). A side surface (die side surface) on the die can include one or more metal layers. The metal layers can include, for example, an adhesion layer, a diffusion barrier layer, and an anti-oxidation layer (e.g., a layer including gold).

[0037] FIG. 1A is a vertical cross-sectional view of a package structure 100 according to one or more embodiments. FIG. 1Bis a plan view (e.g., top view) of a package structure 100 according to one or more embodiments. FIG. 1A is a vertical cross-sectional view of the package structure 100 in FIG. 1B is along line segment A-A’ in FIG. 1C is a detailed vertical cross-sectional view of a portion of a package lid 130 in the package structure 100 according to one or more embodiments.

[0038] As shown in FIG. 1A , the package structure 100 can include a package substrate 110, an interposer module 120 on the package substrate 110, and a thermal interface material (TIM) layer 170 on the interposer module 120. The package structure 100 can also include a package lid 130 on the TIM layer 170. The package lid 130 can include a package lid foot portion 130a attached to the package substrate 110. The package lid 130 can also include a package lid plate portion 130p connected to the package lid foot portion 130a. The package lid 130 can also include a plurality of fins 130f extending from the package lid plate portion 130p to the TIM layer 170 above the interposer module 120. The plurality of fins 130f can form an innovative fin heat spreader in the package structure 100. The plurality of fins 130f can enhance the mechanical structure of the TIM layer 170 (e.g., a metal TIM layer).

[0039] The package substrate 110 can include a core or a coreless substrate. For example, in at least one embodiment, the package substrate 110 can include a core 112, a package substrate upper dielectric layer 114 (e.g., a first side or chip-side of the package substrate 110) formed on the core 112, and a package substrate lower dielectric layer 116 (e.g., a second side or board-side of the package substrate 110) formed on the core 112. In particular, the package substrate 110 can include a build-up film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 can be described as an ABF layer.

[0040] The core 112 can help provide rigidity to the package substrate 110. The core 112 can include, for example, an epoxy such as a bismaleimide triazine epoxy (BT epoxy) and / or a fiberglass laminate. The core 112 can alternatively or additionally include an organic material such as a polymeric material. In particular, the core 112 can include a dielectric polymeric material such as polyimide (PI), benzocyclo-butene (BCB) polymer, or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the intended scope of the present disclosure.

[0041] The core 112 can include one or more vias 112a. The vias 112a can extend from a lower surface of the core 112 to an upper surface of the core 112. The vias 112a can allow for electrical connections between the dielectric layer 114 over the package substrate and the dielectric layer 116 under the package substrate. The vias 112a can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the intended scope of the present disclosure.

[0042] The dielectric layer 114 over the package substrate can be formed on the upper surface of the core 112. The dielectric layer 114 over the package substrate can include multiple layers and, in particular, can include a build-up film (e.g., ABF). The dielectric layer 114 over the package substrate can also include an organic material such as a polymeric material. In particular, the dielectric layer 114 over the package substrate can include a dielectric polymeric material such as polyimide (PI), benzocyclo-butene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the intended scope of the present disclosure.

[0043] The dielectric layer 114 on package substrate can include one or more bond pads 114a on a chip side surface thereof. The bond pads 114a on package substrate can be exposed on the chip side surface of the dielectric layer 114 on package substrate. The dielectric layer 114 on package substrate can also include one or more metal interconnect structures 114b. The metal interconnect structures 114b can electrically couple the bond pads 114a on package substrate to the vias 112a in the die 112. The metal interconnect structures 114b can include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The bond pads 114a on package substrate and the metal interconnect structures 114b can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplation of the present disclosure.

[0044] A passivation layer 110a on package substrate can be formed on the chip side surface of the dielectric layer 114 on package substrate. The passivation layer 110a on package substrate can at least partially cover the bond pads 114a on package substrate. The passivation layer 110a on package substrate can include silicon oxide, silicon nitride, low-k dielectric materials (e.g., carbon-doped oxides), ultra-low-k dielectric materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials.

[0045] A dielectric layer 116 under package substrate can be formed on a lower surface of the die 112. The dielectric layer 116 under package substrate can also include multiple layers, and in particular, can include a build-up film (e.g., ABF). The dielectric layer 116 under package substrate can also include an organic material, such as a polymeric material. In particular, the dielectric layer 116 under package substrate can include a dielectric polymeric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplation of the present disclosure.

[0046] The under-substrate dielectric layer 116 may include one or more under-substrate bonding pads 116a on its side surface. The under-substrate dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b may electrically couple the under-substrate bonding pads 116a to vias 112a in the core 112. The metal interconnect structures 116b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The under-substrate bonding pads 116a and the metal interconnect structures 116b may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are contemplated within the scope of this disclosure.

[0047] A passivation layer 110b under the package substrate may be formed on the board-side surface of the dielectric layer 116 under the package substrate. The passivation layer 110b under the package substrate may at least partially cover the bonding pad 116a under the package substrate. The passivation layer 110b under the package substrate may include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0048] A ball-grid array (BGA), including multiple solder balls 110c, can be formed on the board-side surface of the package substrate 110. The solder balls 110c allow the package structure 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The multiple solder balls 110c can each contact the bonding pad 116a under the package substrate. Therefore, the solder balls 110c can be electrically connected to the bonding pad 114a on the package substrate via metal interconnect structures 116b, vias 112a, and metal interconnect structures 114b. The solder balls 110c of the BGA can be formed in a two-dimensional array on the board-side surface of the package substrate 110. The solder balls 110c can be located, for example, below the package cover feet 130a and below the interposer module 120.

[0049] like FIG. 1A As shown, the width of the packaging substrate 110 in the x-direction can be greater than the width of the interposer module 120 in the x-direction. The length of the packaging substrate 110 in the y-direction can be greater than the length of the interposer module 120 in the y-direction. The interposer module 120 can be located at the center portion of the packaging substrate 110. The interposer module 120 may include an interposer 200 and one or more dies 140 (e.g., semiconductor dies, top dies, etc., see [reference]) on the interposer 200. FIG. 1BThe interposer module 120 can be attached to the package substrate on- bond pads 114a in the package substrate 110 by C4 bumps 121. The C4 bumps 121 can include metal posts (not shown) and solder bumps (e.g., SnAg solder bumps) on the metal posts. The solder bumps can collapse to connect the metal posts of the C4 bumps 121 to the package substrate on-bond pads 114a.

[0050] A package underfill layer 119 can be formed on the package substrate 110 under and around the interposer module 120. The package underfill layer 119 can also be formed around the C4 bumps 121. In this way, the package underfill layer 119 can securely affix the interposer module 120 to the package substrate 110. The package underfill layer 119 can be formed of an epoxy-based polymer material.

[0051] The interposer module 120 is not limited to any particular architecture. The interposer module 120 can include, for example, a flip chip-chip scale package design, a chip-on-wafer-on-substrate design, an integrated fan-out design, etc. In at least one embodiment, the interposer 200 can be omitted from the interposer module 120. In such an embodiment, the die 140 can be directly attached to the package substrate 110.

[0052] The interposer 200 of the interposer module 120 can comprise an inorganic interposer. The interposer 200 can include a semiconductor material layer 202. In at least one embodiment, the semiconductor material layer 202 can comprise a silicon-based semiconductor material. The semiconductor material layer 202 can include single crystalline silicon or polycrystalline silicon. The semiconductor material layer 202 can be undoped or doped with electrical dopants, such as p-type or n-type dopants.

[0053] The interposer 200 can include a plurality of via cavities 201 in the semiconductor material layer 202. The via cavities 201 can extend through an entire thickness of the semiconductor material layer 202 in the z-direction. The lateral dimension (e.g., diameter) of the via cavities 201 can be in a range of 0.5 microns to 10 microns, such as 1 micron to 6 microns, although smaller or larger lateral dimensions can also be used. In at least one embodiment, the pattern of the array of via cavities 201 can have a two-dimensional periodicity on the interposer 200.

[0054] An insulating liner 203 can be formed in a peripheral portion of the via cavity 201 and on an upper surface portion of the semiconductor material layer 202. The insulating liner 203 can include, for example, silicon oxide, silicon nitride, low-k dielectric material (e.g., carbon-doped oxide), ultra-low-k dielectric material (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials. The insulating liner 203 can have a thickness in a range from 1% to 20%, for example, from 2% to 5%, of a lateral dimension of the via cavity 201.

[0055] A plurality of through silicon vias (TSVs) 204 can be respectively located in the plurality of via cavities 201. The through silicon vias 204 can include at least one electrically conductive material, for example, at least one metallic material, in a central portion of the via cavity 201. The through silicon vias 204 and the front insulating liner 203 can substantially fill the via cavity 201. The through silicon vias 204 can include, for example, a combination of a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal filler material (such as Cu, Co, Ru, Mo, W, etc.). Other suitable metal barrier materials and metal filler materials are contemplated within the scope of the present disclosure.

[0056] The interposer 200 can further include a lower insulating layer 205 on a bottom surface of the semiconductor material layer 202. The lower insulating layer 205 can connect the insulating liner 203 in the via cavity 201. The lower insulating layer 205 can include the same or similar material as the material of the insulating liner 203. The lower insulating layer 205 can include, for example, silicon oxide, silicon nitride, low-k dielectric material (e.g., carbon-doped oxide), ultra-low-k dielectric material (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials.

[0057] The interposer 200 can further include an interposer lower bonding pad 206 on the through silicon via 204 on a board-side surface of the interposer 200. The interposer 200 can further include a lower passivation layer 207 on the board-side surface of the interposer 200. The lower passivation layer 207 can at least partially cover and the interposer lower bonding pad 206. A plurality of C4 bumps 121 can be respectively connected to the interposer lower bonding pad 206 on the board-side surface of the interposer 200. In at least one embodiment, the C4 bump 121 can include an underbump metallurgy (UBM) layer on the interposer lower bonding pad 206. The C4 bump 121 can be at least partially located on the lower insulating layer 205. The lower insulating layer 205 can be used to electrically insulate the C4 bump 121 from the semiconductor material layer 202.

[0058] The interposer 200 can also include an interposer- up bond pad 208 on the through-silicon via 204 on the chip-side surface of the interposer 200. The interposer 200 can also include an upper passivation layer 209 on the board-side surface of the interposer 200. The upper passivation layer 209 can at least partially cover the interposer-up bond pad 208. The interposer-down bond pad 206 and the interposer-up bond pad 208 can be substantially similar to the package substrate-down bond pad 116a and the package substrate-up bond pad 114a, respectively. The lower passivation layer 207 and the upper passivation layer 209 can be substantially similar to the package substrate- down passivation layer 110b and the package substrate-up passivation layer 110a, respectively.

[0059] In at least one embodiment, the interposer module 120 can include a redistribution layer (RDL) structure (not shown) on the chip-side surface of the interposer 200. The RDL structure can include a plurality of polymer layers and a plurality of redistribution layer interchanges stacked. The redistribution layer can include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. The redistribution layer can include metal connection structures, i.e., metal structures that provide electrical connections and nodes between structures. In at least one embodiment, the redistribution layer can include a plurality of traces and a plurality of vias connecting the plurality of traces to each other. The traces can be located on the polymer layers, respectively, and can extend in an x-direction (a first horizontal direction) and a y-direction (a second horizontal direction) on an upper surface of the polymer layers. The redistribution layer can wire the die 140 and / or connect the die 140 to the through-silicon via 204 in the interposer 200.

[0060] The die 140 can be attached to the chip-side surface of the interposer 200 (or, if the RDL structure is present, to the RDL structure). In particular, the die 140 can be flip-chip mounted on the upper surface of the interposer 200. That is, an active region of the die 140 can face the interposer 200, and a bulk semiconductor region of the die 140 can be opposite the active region. The die 140 can have an upper surface 140a (e.g., an upper surface of the bulk semiconductor region) that is substantially coplanar. In particular, the upper surface 140a of the die 140 can be at the same height as measured from an upper surface of the upper passivation layer 209.

[0061] In at least one embodiment, the die 140 can be bonded to the interposer upper bonding pads 208 on the chip side surface of the interposer 200 through micro bumps 128. The micro bumps 128 can each include a copper post and a solder bump on the copper post. In at least one embodiment, the die 140 can include one or more die bonding pads 155 electrically coupled to an active region of the die 140. The micro bumps 128 can contact the die bonding pads 155 of the die 140. The die bonding pads 155 can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the intended scope of the present disclosure.

[0062] The interposer module underfill layer 129 can be formed (e.g., individually or collectively) under and around each of the die 140. The interposer module underfill layer 129 can also be formed around the micro bumps 128. In this way, the interposer module underfill layer 129 can secure each of the die 140 to the interposer 200. The interposer module underfill layer 129 can be formed of an epoxy-based polymeric material. Other suitable metal materials are within the intended scope of the present disclosure.

[0063] In addition to utilizing the micro bumps 128 and the interposer module underfill layer 129, the die 140 can also be bonded to the interposer 200 through a hybrid bond, which can also be referred to as a direct bond or a wafer-to-wafer bond. The hybrid bond can include a metal portion and a dielectric portion. In at least one embodiment, the hybrid bond can include a metal-to-metal bond and an oxide-to-oxide bond. Specifically, the hybrid bond can include a bond between the die bonding pads 155 and the interposer upper bonding pads 208, and a bond between a dielectric layer (e.g., an oxide layer) on the die 140 and a dielectric layer (e.g., an oxide layer) on the interposer 200.

[0064] The die 140 can include a first die 141 and a second die 142 adjacent to the first die 141. Each die 140 can include, for example, a single semiconductor die structure, a system-on-chip (SoC) die, or a system-on-integrated chips (SoIC) die, and can be implemented by a chip-on-wafer-on-substrate (CoWoS) technology or an integrated fan-out on substrate (InFO) technology. Specifically, each semiconductor die 140 can include, for example, a semiconductor chip or a small chip for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a high-bandwidth memory (HBM) die, a hybrid memory cube (HMC), a dynamic random-access memory (DRAM) die, a wide I / O die, an M-RAM die, an R-RAM die, a NAND die, a static random-access memory (SRAM), etc.), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field-programmable gate array (FPGA) chip, a network chip, an application-specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (AI / DNN) accelerator chip, and the like, a co-processor, an accelerator, an on-chip memory buffer, a high-data-rate transceiver die, an I / O interface die, an IPD die, a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a monolithic 3D heterogeneous small chip stack die, and the like. Other dies are within the intended scope of the present disclosure. In at least one embodiment, the first die 141 can include a primary die (e.g., a system-on-chip die), and the second die 142 can include a secondary die (e.g., a DRAM die, an HBM die, etc.) to support operation of the primary die.

[0065] The sidewall (e.g., a die sidewall) of the die 140 can include one or more metal layers (not shown). The metal layers can include, for example, an adhesion layer, a diffusion barrier layer, and an anti-oxidation layer (e.g., a layer including gold).

[0066] The interposer module 120 can also include a mold encapsulation material layer 127 on the interposer 200, on and around the die 140, and between the dies 140. The mold encapsulation material layer 127 can be formed on (e.g., covering) and engaged with one or more die sidewalls (e.g., all die sidewalls) on the die 140. In at least one embodiment, the die 140 can be substantially "embedded" within the mold encapsulation material layer 127. The mold encapsulation material layer 127 can also be formed on and engaged with a surface of the upper passivation layer 209 (or RDL structure, if present) of the interposer 200.

[0067] An upper surface of the mold encapsulation material layer 127 can be substantially uniform (e.g., planar). The upper surface can also be substantially coplanar with the upper surface 140a of the die 140. An outer sidewall 127a of the mold encapsulation material layer 127 can be substantially aligned with an outer sidewall of the interposer 200. In at least one embodiment, an outer sidewall of the interposer module 120 can be at least partially formed by the outer sidewall 127a of the mold encapsulation material layer 127 and at least partially formed by the outer sidewall of the interposer 200.

[0068] In at least one embodiment, the mold encapsulation material layer 127 can be formed from a curable material that can be cured to form a hard, solid structure. The mold encapsulation material layer 127 can include, for example, an epoxy molding compound (EMC). In at least one embodiment, the mold encapsulation material layer 127 can include a polymeric material, particularly an epoxy-based polymeric material. Other suitable mold encapsulation materials can be used.

[0069] In at least one embodiment, the mold encapsulation material layer 127 can have a CTE that is substantially similar to that of the interposer 200. In at least one embodiment, the mold encapsulation material layer 127 can include added materials (e.g., filler materials) to improve physical properties (e.g., thermal conductivity, CTE, etc.) of the mold encapsulation material layer 127. The added materials can include, for example, metal powders, metal oxide powders, etc. Other materials in the mold encapsulation material layer 127 are also contemplated within the scope of the present disclosure.

[0070] The interposer module 120 can also optionally include a backside metal layer 151 on the upper surface of the mold encapsulation material layer 127 and / or on the upper surface 140a of the die 140. The backside metal layer 151 can be thermally conductive and enhance the thermal dissipation characteristics of the interposer module 120. In at least one embodiment, the backside metal layer 151 can cover the entire upper surface of the interposer module 120, including the entirety of the upper surface of the mold encapsulation material layer 127 and / or the entirety of the upper surface 140a of the die 140. In at least one embodiment, the backside metal layer 151 can only cover a portion of the upper surface of the interposer module 120, including a portion of the upper surface of the mold encapsulation material layer 127 and / or a portion of the upper surface 140a of the die 140. This improved thermal dissipation can allow the interposer module 120 to further incorporate a lid structure to improve warpage characteristics. The backside metal layer 151 can have a substantially uniform thickness. The backside metal layer 151 can include a thermally conductive metal, such as copper or a copper alloy. The backside metal layer 151 can include other suitable materials.

[0071] The TIM layer 170 can be located on the upper surface of the mold encapsulation material layer 127 and / or on the upper surface 140a of the die 140. The TIM layer 170 can be located on the optional backside metal layer 151 (if present) instead of or in addition to. In at least one embodiment, the center of the TIM layer 170 can be substantially aligned with the center of the interposer module 120. In at least one embodiment, the outer sidewalls of the TIM layer 170 can be substantially aligned with the outer sidewalls of the interposer module 120 (e.g., the outer sidewalls of the mold encapsulation material layer 127). In at least one embodiment, the TIM layer 170 can be in a die-to-die gap between the dies 140, formed on the upper surface of the interposer module underfill layer 129.

[0072] The TIM layer 170 can have a low bulk thermal impedance and a high thermal conductivity. The thickness of the TIM layer 170 can be in the range of 50 pm to 300 pm. In at least one embodiment, the bond-line-thickness (BLT) (e.g., the distance between the package lid 130 and the interposer module 120) can be less than about 100 pm, although greater or lesser distances can be used. In at least one embodiment, the TIM layer 170 can cover the entire area of the upper surface of the interposer module 120. The TIM layer 170 can be formed by a thermally conductive adhesive that adheres to the upper surface of the interposer module 120 (and / or the upper surface of the optional backside metal layer 151). The TIM layer 170 can contact, for example, the upper surface 140a of the die 140, and / or the upper surface of the mold encapsulation material layer 127.

[0073] In at least one embodiment, TIM layer 170 can include one or more metals. TIM layer 170 can include, for example, a low-melting-temperature (LMT) metal TIM, or a liquid metal TIM. TIM layer 170 can include one or more metals, such as indium or gallium (e.g., an indium-rich TIM, a gallium-rich TIM, etc.). TIM layer 170 can include, for example, a gallium-based, an indium-based, a silver-based, a solder base, etc. A solder base can include tin and one or more other elements, such as copper, silver, bismuth, indium, zinc, antimony, etc. These in other metal TIM layers 170 are within the contemplation of the present disclosure.

[0074] TIM layer 170 can alternatively or additionally include a thermal grease, a thermal paste, a thermal film, a thermal adhesive, a thermal gap filler, a thermal pad (e.g., silicone), a thermal tape, or a gel-type TIM (e.g., a cross-linked polymer film). In at least one embodiment, TIM layer 170 can include graphite, carbon nanotubes (CNTs), a phase change material (PCM), etc. A PCM can include, for example, a PCM of a high-molecular material substrate. In at least one embodiment, a PCM can transition its phase from a solid to a high-viscosity semi-liquid at around 60°C. Other materials in TIM layer 170 are within the contemplation of the present disclosure.

[0075] Referring again to FIG. 1A , package structure 100 can optionally include one or more surface-mounted devices (SMDs) 190 on package substrate 110. Surface-mounted devices 190 can be located between interposer module 120 and package lid foot 130a. Surface-mounted devices 190 can include, for example, semiconductor dies, such as dies 140 described above. In at least one embodiment, surface-mounted devices 190 can include memory dies, such as DRAM dies, HBM dies, etc. Surface-mounted devices 190 can be electrically coupled to interposer module 120 (and dies 140 in interposer module 120) through package substrate 110. Surface-mounted devices 190 can also include non-functional dies (e.g., dummy dies) that can provide structural support for package structure 100.

[0076] The surface mount element 190 can be attached to the package substrate 110 by a plurality of C4 bumps 221. The C4 bumps 221 can substantially have the same structure and function as the C4 bumps 121 described above. Like the C4 bumps 121, the C4 bumps 221 can be bonded to the bond pads 114a on the package substrate, respectively. The surface mount element 190 can be electrically coupled to the package substrate 110 by the C4 bumps 221. Other suitable means of attaching the surface mount element 190 to the package substrate 110 (e.g., adhesion) can be used.

[0077] An optional underfill layer (not shown) can be formed on the package substrate 110 under and around the surface mount element 190 and around the C4 bumps 221. The optional underfill layer can help to securely hold the surface mount element 190 to the package substrate 110. The optional underfill layer can be substantially the same as the package underfill layer 119 described above. In particular, the optional underfill layer can be formed of an epoxy-based polymer material.

[0078] Referring again to FIG. 1A The package cover 130 can be positioned on the TIM layer 170 and can provide coverage for the interposer module 120. The package cover 130 can also provide coverage for the surface mount element 190. The package cover 130 can be formed of, for example, a metal, ceramic, or polymer material. Other suitable materials can be used for the package cover 130.

[0079] Package cover feet 130a of the package cover 130 can be attached to the package substrate 110. The package cover feet 130a can extend from the package cover plate portion 130p in a substantially vertical direction. The package cover feet 130a can be connected to the package substrate 110 by the adhesive layer 160. The adhesive layer 160 can include, for example, an epoxy adhesive or a silicone adhesive. Other adhesives are within the intended scope of the present disclosure.

[0080] The package structure 100 can also include an inner adhesive layer 161 on the package substrate 110 between the package cover feet 130a. The inner adhesive layer 161 can be positioned between the surface mount element 190 and the interposer module 120. The inner adhesive layer 161 can alternatively or additionally be positioned between the package cover feet 130a and the surface mount element 190. The inner adhesive layer 161 can extend from the package substrate 110 to the package cover plate portion 130p. The inner adhesive layer 161 can help to secure the package cover 130 to the package substrate 110. The inner adhesive layer 161 can include the same material as the adhesive layer 160 or a different material than the adhesive layer 160.

[0081] The package lid plate portion 130p (e.g., a main body of the package lid 130) can be connected to the package lid leg portion 130a (e.g., an upper end of the package lid leg portion 130a). In at least one embodiment, the package lid plate portion 130p can be integrally formed as one unit with the package lid leg portion 130a. Alternatively, the package lid plate portion 130p can be formed separately from the package lid leg portion 130a and attached to the package lid leg portion 130a by an adhesive (not shown). The adhesive can be substantially similar to the adhesive layer 160 described above.

[0082] The package lid plate portion 130p can have a plate shape extending in the xy-plane of the FIG. 1A , for example. An outer periphery of the package lid plate portion 130p can be substantially aligned with an outer periphery of the package lid leg portion 130a. The package lid plate portion 130p can be substantially parallel to the upper surface of the package substrate 110. The package lid plate portion 130p can include an inner region formed above a central portion of the interposer module 120. The inner region can contact at least a portion of the TIM layer 170 above the central portion of the interposer module 120. In at least one embodiment, a center of the inner region can be substantially aligned with a center of the interposer module 120 and / or with a center of the TIM layer 170.

[0083] The package lid plate portion 130p can include a bottom surface S 130p . The bottom surface S 130p may extend across an underside of the package lid plate portion 130p. In at least one embodiment, the bottom surface S 130p may extend between the package lid leg portion 130a on one side of the package structure 100 and the package lid leg portion 130a on an opposite side of the package structure 100. In at least one embodiment, the bottom surface S 130p may substantially constitute an entire underside of the package lid plate portion 130p. The bottom surface S 130p of the package lid plate portion 130p can be in contact with the TIM layer 170. In one or more embodiments, the bottom surface S 130p may directly contact an entire upper surface of the TIM layer 170. In one or more embodiments, the TIM layer 170 can be compressed between the bottom surface S 130p of the package lid plate portion 130p and an upper surface of the interposer module 120.

[0084] As shown in FIG. 1A , the plurality of fins 130f can extend from the bottom surface S 130pThe TIM layer 170 extends above the interposer module 120. The plurality of fins 130f can enhance thermal dissipation in the package structure 100 while also enhancing the mechanical structure of the TIM layer 170. The fins 130f can be separated, for example, by gaps G, and at least a portion of the TIM layer 170 can be located in the gaps G. In at least one embodiment, each fin 130f is located above the interposer module 120. In at least one embodiment, each fin 130f is located above a die 140 in the interposer module 120. In at least one embodiment, each of the fins 130f extends to some extent into the TIM layer 170.

[0085] Referring again to FIG. 1B , for ease of understanding, the package lid 130 and the TIM layer 170 are omitted from the top-down view of the package structure 100 in FIG. 1B . The locations of the package lid foot portions 130a and the locations of the fins 130f are indicated by dashed lines in FIG. 1B . As shown in FIG. 1B , the package lid foot portions 130a (and thus the package lid plate portion 130p (not shown)) can have substantially the same outer shape as the package substrate 110. Further, the interposer module 120 can be disposed in a central portion of the package substrate 110, and the surface mount elements 190 can be disposed around the interposer module 120.

[0086] Although FIG. 1B the package structure 100 is shown as including one (1) first die 141 and eight (8) second dies 142 having a particular arrangement, the number and arrangement of the first dies 141 and the second dies 142 are not limited to the number and arrangement in FIG. 1B . Although FIG. 1B the package structure 100 is shown as including two (2) surface mount elements 190 having a particular arrangement, the number of surface mount elements 190 and the arrangement of the surface mount elements 190 are not limited to the number and arrangement in FIG. 1B .

[0087] The package substrate 110 can have substantially a rectangular shape or, alternatively, substantially a square shape. Other shapes of the package substrate 110 are within the intended scope of disclosure. In at least one embodiment, the package substrate 110 can have a package substrate width in the x-direction and a package substrate length in the y-direction that is greater than the package substrate width. The package lid foot portions 130a (e.g., and the package lid plate portion 130p) can have widths and lengths that are substantially similar (e.g., slightly smaller) to the package substrate width and the package substrate length, respectively. The package lid foot portions 130a can be formed to surround an entire perimeter of the interposer module 120. Alternatively, the package lid foot portions 130a can be formed to surround only a portion of the interposer module 120.

[0088] Interposer module 120 may have an interposer module width in the x-direction and an interposer module length in the y-direction greater than the interposer module width. Interposer module 120 may have a substantially rectangular shape or alternatively a substantially square shape. Other shapes of interposer module 120 are within the scope of this disclosure. Die 140 may have a substantially rectangular shape or alternatively a substantially square shape. Other shapes of die 140 are within the scope of this disclosure. Die 140 may have a die width in the x-direction and a die length in the y-direction greater than the die width. Although in FIG. 1B The intermediate layer module 120 is shown to include two dies 140 with a specific arrangement, but the number of dies 140 and the arrangement of dies 140 are not limited to... FIG. 1C The quantity and arrangement of the items.

[0089] like FIG. 1C As shown, the inner adhesive layer 161 may surround the entire periphery of the interposer module 120. Alternatively, the inner adhesive layer 161 may surround only a portion of the interposer module 120. For example, the inner adhesive layer 161 may be formed only at a corner of the interposer module 120. The fins 130f of the encapsulation cover 130 may extend from the bottom surface S of the encapsulation cover portion. 130p Alternatively, it can extend in the form of a cylindrical body. The fin 130f can be formed as a square cylinder, in which case the fin 130f can have a square cross-section. The square end portion of the fin 130f can be embedded in the TIM layer 170. Alternatively, the fin 130f can be formed as a circular cylinder, in which case the fin 130f can have a circular cross-section. Other shapes of the fin 130f are within the scope of this disclosure. For example, elliptical cross-sections, triangular cross-sections, and other polygonal cross-sections can be used.

[0090] The fins 130f in the encapsulation cover 130 can have a spacing P in both the x and y directions. 130f (For example, the distance between centers). Alternatively, the fins 130f in the encapsulation cover 130 may have a spacing different in the y-direction than in the x-direction. In at least one embodiment, the spacing P 130f It can be within the range of 1mm to 5mm. Spacing P 130f It can be substantially uniform throughout the entire fin 130f. Alternatively, the spacing P... 130f The fins 130f can vary between the x-direction and / or the y-direction. In other words, the spacing P in the x-direction... 130f It can be related to the spacing P in the y direction 130f Same or different.

[0091] Fins 130f of package lid 130 can be formed over die 140 in interposer module 120. In at least one embodiment, the location of fins 130f can correspond to a semiconductor (e.g., silicon) region (e.g., a die region, a system chip region, an HBM region, etc.) of interposer module 120. In at least one embodiment, one or more of fins 130f can include at least a portion of interposer module 120 above mold material layer 127. In at least one embodiment, fins 130f can be formed as an array of rows and columns on first die 141. Fins 130f can also be formed as an array of rows and columns on second die 142. In at least one embodiment, a row of fins 130f on first die 141 can be substantially aligned in an x-direction with a row of fins 130f on second die 142.

[0092] Referring again to FIG. 1B , TIM layer 170 can have a first thickness T1 170 between bottom surface S130p and interposer module 120 FIG. 2A to FIG. 4 , or optionally as shown between optional backside metal layer 151 and optional plating layer 130m. The thickness of plating layer 130m can be substantially equal to the thickness of backside metal layer 151. Plating layer 130m can include a thermally conductive metal, such as copper or a copper alloy. Other suitable thermally conductive metal materials for use in plating layer 130m are within the contemplated scope of the disclosure.

[0093] TIM layer 170 can also have a second thickness T2 170 between fins 130f and interposer module 120 (e.g., between optional backside metal layer 151 and optional plating layer 130m). 170 The first thickness T1 170 may be greater than the second thickness T2 170 In at least one embodiment, the first thickness T1 170 may be at least twice the second thickness T2 170 In at least one embodiment, the first thickness T1 170 may be in a range of 200 pm to 400 pm. In at least one embodiment, the second thickness T2

[0094] Package lid plate portion 130p can have a thickness T 130p between an upper surface US 130p of package lid plate portion 130p and a bottom surface S 130p of package lid plate portion 130p. Fins 130f can have a thickness T 130f (e.g., from bottom surface S 130pto the top surface of the optional plating layer 130m, or to the top surface of the TIM layer 170, as measured. That is, the fins 130f can extend into the TIM layer 170 a length equal to the thickness T 130f . In at least one embodiment, the thickness T 130f may be equal to or less than the thickness T 130p . In at least one embodiment, the thickness T 130f may be in a range of 25% to 75% of the thickness T 130p . In at least one embodiment, the thickness T 130f may be in a range of 25 pm to 100 pm.

[0095] The fins 130f can have a width W 130f in a range of 100 pm to 1000 pm. In at least one embodiment, the width W 130f of the fins 130f can be greater than the thickness of the fins 130f. In at least one embodiment, the width W 130f of the fins 130f can be uniform across the entirety of the fins 130f. In at least one embodiment, the width W 130f of the fins 130f can vary in the x-direction and / or the y-direction.

[0096] The fins 130f can be separated by gaps G in the x-direction and the y-direction (see FIG. 2A to FIG. 2B ). In at least one embodiment, the width W G of the gaps G can be less than the width W 130f of the fins 130f. Alternatively, the width W G of the gaps G can be equal to or greater than the width W 130f of the fins 130f. In at least one embodiment, the width W G may be uniform across the entirety of the gaps G. In at least one embodiment, the width W G of the gaps G can vary in the x-direction and / or the y-direction. In at least one embodiment, the width W G of the gaps G can be in a range of 50 pm to 2000 pm.

[0097] FIG. 2A Various intermediate structures are shown that form the package lid 130 according to one or more embodiments. FIG. 2A A stamping process is shown that forms the fins 130f of the package lid 130 according to one or more embodiments.

[0098] FIG. 3A to FIG. 3E A stamping process is shown that forms the fins 130f of the package lid 130 according to one or more embodiments. 130pThe stamp 300 is applied to the bottom surface S of the package cover portion 130p after the package cover support portion 130a is formed. For example, using a computer-controlled digital polishing machine, or after forming or imprinting, the stamp 300 is applied to the bottom surface S of the package cover portion 130p through an imprinting process. 130p Fin 130f is formed on top. Alternatively, fin 130f can be formed before forming the cover support portion 130a.

[0099] Fin 130f can also be formed by other suitable methods, such as etching processes. In an etching process, for example, it can be formed on the bottom surface S of the package cover portion 130p. 130p A patterned photoresist mask is formed on the surface. The photoresist mask may include features other than those on the bottom surface S. 130p An opening is formed at a location other than the position of fin 130f. Etching can then be performed through the opening in the photoresist mask to etch the bottom surface S. 130p All positions except where fin 130f is located.

[0100] like FIG. 1B As shown, the mold 300 used in the embossing process may include a recessed pad 302 formed on the bottom of the mold 300. The recessed pad 302 may include a plurality of recesses 302a (see...). FIG. 2B It can transfer the pattern of fin 130f to the bottom surface S of the encapsulation cover portion 130p. 130p Above. The recess 302a may include an opening extending through the entire thickness of the recessed pad 302. The recess 302a may have a substantially square shape corresponding to the cross-sectional shape of the fin 130f.

[0101] During the imprinting process, the package cover 130 can be inverted and placed on a rigid structure with a flat surface, such as a tabletop. Then, the imprint 300 can be positioned on the bottom surface S of the package cover portion 130p. 130p Above, and descends into the package cover 130, so that the recessed pad 302 contacts the bottom surface S of the package cover portion 130p. 130p Next, the impression 300 can be pressed downwards, causing the recessed pad 302 to be pressed into the bottom surface S of the encapsulation cover portion 130p. 130p In the middle. A sufficient amount of pressure, both in size and duration, can be applied to force the cap material (e.g., copper) of the encapsulation cap 130 into the recess 302a, thereby forming a fin 130f within the recess 302a. The thickness of the fin 130f (see...) FIG. 3A to FIG. 3E It can be proportional to the magnitude and duration of the applied pressure.

[0102] FIG. 3A to FIG. 3E This shows the formation of fin 130f from the bottom surface S according to one or more embodiments. 130pThe retracted impression 300. When the impression 300 retracts, the cover material can be pulled out from the recess 302a, leaving the fin 130f on the bottom surface S of the encapsulation cover portion 130p. 130p superior.

[0103] FIG. 3A Various recessed pads 302 that can be used in an imprinting process according to one or more embodiments are shown. For example... FIG. 3B As shown, the recessed pad 302 may include a hexagonal recess 302a ( FIG. 3C ), the concave part of the triangle 302a ( FIG. 3D ), diamond-shaped recess 302a ( FIG. 3E ), elliptical depression 302a ( FIG. 4 ) and the straight-line depression 302a ( FIG. 5A to FIG. 5J Other shapes of the recess 302a are within the scope contemplated in this disclosure. In some embodiments, the shape of the recess (and the resulting fin 130f) may be substantially uniform. In some embodiments, the shape of the recess (and the resulting fin 130f) may vary. In at least one embodiment, the recess pad 302 may be detachably attached to the bottom of the impression 300 to allow for easy replacement of different recess pads 302 with different designs.

[0104] FIG. 5A The encapsulation cover 130 is shown after the plating layer 130m is formed according to one or more embodiments. On the bottom surface S of the encapsulation cover portion 130p... 130p After the fin 130f is formed, an optional plating layer 130m can be formed on the fin 130f. The optional plating layer 130m can be formed to cover an area substantially corresponding to the interposer module 120 (e.g., the area of ​​the TIM layer 170 on the interposer module 120). That is, in a plan view (e.g., top view of the bottom surface S) 130p The outline of the optional plating layer 130m in the interposer module 120 can be formed to match the outline of the interposer module 120. The optional plating layer 130m can be formed by an electroplating process. Other methods for forming the optional plating layer 130m are also within the scope of this disclosure.

[0105] FIG. 5B Various intermediate structures in a method of forming a package structure 100 according to one or more embodiments are shown. FIG. 5C This is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, including a package substrate 110 having an upper bonding pad 114a and a lower bonding pad 116a. The package substrate 110 may be provided including a core 112, an upper dielectric layer 114, and a lower dielectric layer 116.

[0106] The package substrate upper bonding pads 114a can be formed on, for example, the uppermost dielectric layer of the package substrate upper dielectric layers 114. The package substrate upper bonding pads 114a can be formed to contact the metal interconnect structures 114b. The package substrate upper bonding pads 114a can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the package substrate upper dielectric layers 114. The metal layer can then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the package substrate upper bonding pads 114a. Other suitable metal layer materials and etching processes can be within the contemplated scope of the present disclosure.

[0107] The package substrate lower bonding pads 116a can be formed on the lowermost dielectric layer of the package substrate lower dielectric layers 116. The package substrate lower bonding pads 116a can be formed to contact the metal interconnect structures 116b. The package substrate lower bonding pads 116a can be formed in a similar manner as the package substrate upper bonding pads 114a (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0108] After formation, the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a can be selectively subjected to a surface roughening process (e.g., a copper zarazara (CZ) process). In the surface roughening process, the surface (e.g., copper surface) of the package substrate upper bonding pads 114a and the surface (e.g., copper surface) of the package substrate lower bonding pads 116a can be etched by an organic acid-type microetching solution to produce a super-roughened surface (e.g., copper surface). The unique rough copper surface topography of the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a can help to achieve high copper-to-resin adhesion.

[0109] A package substrate upper passivation layer 110a and a package substrate lower passivation layer 110b can then be formed on the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a, respectively. In at least one embodiment, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b can each include a solder resist layer (e.g., a polymeric material), also referred to as a solder mask. The package substrate upper passivation layer 110a can also be referred to as an upper solder resist layer 110a, and the package substrate lower passivation layer 110b can also be referred to as a lower solder resist layer 110b.

[0110] The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied simultaneously. The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied, for example, as a liquid photo-imageable film. The liquid photo-imageable film can be applied, for example, by silk-screening or spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film can be applied over the bond pads 114a over the package substrate and the bond pads 116a under the package substrate. The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can alternatively be applied as dry-film photo-imageable films, which can be vacuum laminated onto the surface of the package substrate 110 and over the bond pads 114a over the package substrate and the bond pads 116a under the package substrate, respectively. The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can alternatively or additionally be formed, for example, via chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0111] The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be provided with a thickness that is slightly greater than the thickness of the bond pads 114a over the package substrate and the bond pads 116a under the package substrate, respectively. Alternatively, the passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied so as to have an upper surface that is substantially coplanar with the upper surface of the bond pads 114a over the package substrate and the bond pads 116a under the package substrate, respectively.

[0112] An opening O 110a exposing the upper surface of the bond pads 114a over the package substrate can then be formed in the passivation layer 110a over the package substrate. The opening O 110b An opening O 110a exposing the upper surface of the bond pads 116a under the package substrate can be formed in the passivation layer 110b under the package substrate. The opening O 110b may be formed, for example, by using a photolithographic process. In at least one embodiment, the opening O 110a may be formed, for example, by using a photolithographic process. In at least one embodiment, the opening O 110b may be formed by separate photolithographic processes.

[0113] An opening O 110aThe lithography process (e.g., multiple lithography processes) may include forming a patterned photoresist mask (not shown) on a passivation layer 110a on a package substrate, and etching (e.g., wet etching, dry etching, etc.) to expose the upper surface of the passivation layer 110a on the package substrate through openings in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0114] Used to form an opening O 110b The lithography process (e.g., multiple lithography processes) may include forming a patterned photoresist mask (not shown) on the passivation layer 110b under the package substrate, and etching (e.g., wet etching, dry etching, etc.) to expose the upper surface of the passivation layer 110b under the package substrate through openings in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0115] At the opening O 110a Formed in passivation layer 110a on the packaging substrate and having opening O 110b After being formed in the passivation layer 110b under the packaging substrate, the passivation layer 110a (upper solder resist) on the packaging substrate and the passivation layer 110b (lower solder resist) under the packaging substrate can be cured, for example, by thermal curing or ultraviolet (UV) curing.

[0116] FIG. 5C A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an interposer module 120 may be mounted on a package substrate 110. The interposer module 120 may be mounted on the package substrate 110, for example, via a flip chip bonding (FCB) process. A semiconductor die module may be positioned above the package substrate 110 via, for example, an electromechanical pick-and-place (PNP) machine. A C4 bump 121 on the semiconductor die module may then be lowered onto a package substrate bonding pad 114a of the package substrate 110, and then heated to collapse the C4 bump 121, thereby bonding the C4 bump 121 to the package substrate bonding pad 114a.

[0117] FIG. 5D A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an underfill layer 119 may be formed on an encapsulation substrate 110. The underfill layer 119 may be formed of an epoxy-based polymer material. FIG. 5EAs shown, the package underfill layer 119 can be formed (e.g., injected) underneath and around the interposer module 120 and the C4 bumps 121. The package underfill layer 119 can then be cured, for example, in a box oven at a temperature in the range of 120°C to 180°C for a duration of 60 minutes to 120 minutes to cure the package underfill layer 119 to have sufficient rigidity and mechanical strength.

[0118] FIG. 5E A vertical cross-sectional view of the intermediate structure is shown, in which the surface mount elements 190 can be mounted on the package substrate 110, in accordance with one or more embodiments. The surface mount elements 190 can then be positioned above the package substrate 110 by, for example, a machine tending (MT) machine. The surface mount elements 190 can then be lowered (e.g., under control of the MT machine) onto the package substrate 110 and attached to the package substrate 110. Attachment of the surface mount elements 190 can be via, for example, bonding the C4 bumps to the package substrate on bond pads 114a, respectively. The surface mount elements 190 can alternatively or additionally be attached to the package substrate 110 by applying an adhesive (not shown) between the surface mount elements 190 and the package substrate 110. The adhesive can be substantially similar to the adhesive layer 160. The surface mount elements 190 can include bond pads (not shown) that can be bonded to the package substrate on bond pads 114a of the package substrate 110. The surface mount elements 190 can thereby be electrically coupled to the package substrate 110.

[0119] FIG. 5F A vertical cross-sectional view of the intermediate structure is shown, in which the surface mount elements 190 can be mounted on the package substrate 110, in accordance with one or more embodiments. The surface mount elements 190 can then be positioned above the package substrate 110 by, for example, a machine tending (MT) machine. The surface mount elements 190 can then be lowered (e.g., under control of the MT machine) onto the package substrate 110 and attached to the package substrate 110. Attachment of the surface mount elements 190 can be via, for example, bonding the C4 bumps to the package substrate on bond pads 114a, respectively. The surface mount elements 190 can alternatively or additionally be attached to the package substrate 110 by applying an adhesive (not shown) between the surface mount elements 190 and the package substrate 110. The adhesive can be substantially similar to the adhesive layer 160. The surface mount elements 190 can include bond pads (not shown) that can be bonded to the package substrate on bond pads 114a of the package substrate 110. The surface mount elements 190 can thereby be electrically coupled to the package substrate 110.

[0120] The flux 510 can clean the upper surface of the backside metal layer 151 and remove any impurities (e.g., oxides) that can inhibit the formation of a perfect joint (e.g., solder joint). The flux 510 can also inhibit re-oxidation of the upper surface of the backside metal layer 151 during the soldering process, and reduce the surface tension and viscosity of the metal (e.g., indium in the TIM layer 170). The flux 510 can include, for example, a rosin flux, an organic acid flux, or an inorganic acid flux. Other suitable flux materials are within the contemplated scope of the present disclosure. The flux can be applied, for example, as a liquid. As FIG. 5F shown, the pressurized sprayer 500 can spray the liquid flux 510 onto the upper surface of the backside metal layer 151. In embodiments where the optional backside metal layer 151 is not present, the flux can also prepare and clean the upper surface of the die attach material layer 127 and the die 140.

[0121] FIG. 5E A vertical cross-sectional view of an intermediate structure is shown, in which a TIM layer can be formed on (e.g., attached to) the interposer module, in accordance with one or more embodiments. As FIG. 5G shown, the TIM layer 170 can be applied and have a width in the x-direction and a length in the y-direction that is less than the full width and length of the TIM layer 170, due to lateral displacement of the TIM layer 170 in the x-direction and in the y-direction caused by pushing against the fins 130f of the package lid 130.

[0122] In embodiments where the TIM layer 170 includes metal, the TIM layer 170 can then be applied to the flux 510 (see FIG. 5E ). The TIM layer 170 can be heated, in which case the flux 510 can help form the joint between the TIM layer 170 and the backside metal layer 151.

[0123] In at least one embodiment, a thermal conductive adhesive can or can not be applied to the upper surface of the interposer module 120, depending on the type of TIM layer 170 used. The material of the TIM layer 170 can be dispensed in liquid form (e.g., a paste, a gel, a cream, etc.) onto the upper surface of the interposer module 120 (or onto the thermal conductive adhesive, if present). If the TIM layer 170 includes a solid material, the TIM layer 170 can be pressed onto the interposer module 120 or the adhesive (if present).

[0124] FIG. 5HA vertical cross-sectional view of the intermediate structure is shown during a second fluxing step, according to one or more embodiments. During the second fluxing step, flux 620 can be applied to the upper surface of the TIM layer 170. The flux 620 can be substantially the same as or different from the flux 510. The flux 620 can help facilitate the formation of a joint between the TIM layer 170 (e.g., a TIM layer including a metal such as indium or gallium) and the plated layer 130m of the package lid 130. The flux can be applied, for example, as a liquid. As shown, a pressurized sprayer 600 (which can be the same as or different from the pressurized sprayer 500) can spray the liquid flux 620 onto the upper surface of the TIM layer 170. FIG. 1B

[0125] FIG. 5I A vertical cross-sectional view of the intermediate structure is shown, according to one or more embodiments, in which the adhesive layer 160 and the inner adhesive layer 161 can be applied to the package substrate 110. The adhesive layer 160 can be dispensed onto the package substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The dispensing tool can send the adhesive layer 160 to form a frame shape around the interposer module 120. Upon application, the adhesive layer 160 can be sufficiently rigid to form a semi-solid bead on the surface of the package substrate 110. In at least one embodiment, the viscosity of the adhesive layer 160 upon application can be 50,000 centipoise (cp) or greater. The shape of the semi-solid bead can remain substantially unchanged between the time of application by the dispensing tool and the time of subsequent attachment of the package lid 130. The location of the frame shape of the adhesive layer 160 can correspond to the location of the foot 130a of the package lid 130 (e.g., see FIG. 4 ). Pressing the package lid 130 onto the adhesive layer 160 can deform the adhesive layer 160.

[0126] The inner adhesive layer 161 can also be dispensed onto the package substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The inner adhesive layer 161 can be formed in the same dispensing step as the adhesive layer 160, concurrently with the formation of the adhesive layer 160, and using the same dispensing tool. Alternatively, the inner adhesive layer 161 can be formed before or after the adhesive layer 160.

[0127] ​The dispensing tool can also send the inner adhesive layer 161 to form a frame shape around the interposer module 120. At the time of application, the physical properties (e.g., viscosity) of the inner adhesive layer 161 can be substantially similar to the physical properties of the adhesive layer 160. The inner adhesive layer 161 can be applied with a thickness that is greater than the height of the upper surface of the TIM layer 170. Pressing the package lid 130 onto the inner adhesive layer 161 can deform the inner adhesive layer 161 such that the height of the upper surface of the inner adhesive layer 161 can be substantially the same as the height of the upper surface of the TIM layer 170.

[0128] FIG. 5J A vertical cross-sectional view of an intermediate structure is shown in accordance with one or more embodiments, where the package lid 130 can be affixed (e.g., mounted) onto the package substrate 110. After forming the fins 130f and optional plating layer 130m (see FIGS. 3-4) on the package lid 130, the package lid 130 can be affixed to the package substrate 110. In at least one embodiment, the package substrate 110 and the interposer module 120 can be placed on a surface. The package lid 130 can then be positioned above the package substrate 110, for example, by a machine vision pick-and-place (PNP) machine. The package lid 130 can then be lowered over the interposer module 120 and onto the package substrate 110. The feet 130a of the package lid 130 can then be aligned with the adhesive layer 160 formed on the package substrate 110. The package lid 130 can then be pressed down onto the TIM layer 170 by applying pressure downward onto the package lid 130 such that the feet 130a of the package lid 130 can be affixed to the package substrate 110 through the adhesive layer 160. FIG. 5A ) on the package lid 130, the package lid 130 can be affixed to the package substrate 110. In at least one embodiment, the package substrate 110 and the interposer module 120 can be placed on a surface. The package lid 130 can then be positioned above the package substrate 110, for example, by a machine vision pick-and-place (PNP) machine. The package lid 130 can then be lowered over the interposer module 120 and onto the package substrate 110. The feet 130a of the package lid 130 can then be aligned with the adhesive layer 160 formed on the package substrate 110. The package lid 130 can then be pressed down onto the TIM layer 170 by applying pressure downward onto the package lid 130 such that the feet 130a of the package lid 130 can be affixed to the package substrate 110 through the adhesive layer 160.

[0129] By pressing the package lid 130 onto the TIM layer 170, the TIM layer 170 can be forced to flow (shown by directional arrows) into the gaps G between the fins 130f extending from the bottom surface S 130p The amount (e.g., volume) of the TIM layer 170 dispensed on the interposer module 120 can be substantially enough to fill the gaps G while leaving enough spacing between the package lid plate portion 130p and the interposer module 120.

[0130] The package lid 130 can then be clamped to the package substrate 110 for a period of time to allow curing of the adhesive layer 160 and the inner adhesive layer 161 and form a secure joint between the package substrate 110 and the package lid 130. Clamping of the package lid 130 into the package substrate 110 can be performed, for example, by using a heat clamp module. The heat clamp module can generate a uniform force on the upper surface of the package lid 130. In one or more embodiments, the heat clamp module can apply pressure onto the package lid 130.

[0131] FIG. 6 A vertical cross-sectional view of an intermediate structure is shown, in which a plurality of solder balls 110c can be formed on the package substrate 110. The plurality of solder balls 110c can be formed by plating through openings O 110b formed on the under-bonding pad 116a of the package substrate (see FIG. 6 ). The solder balls 110c can be formed, for example, by a plating process. The solder balls 110c can be formed, for example, to be located under the foot 130a, under the interposer module 120, and in between. The plurality of solder balls 110c can constitute a ball-grid array (BGA), which can allow the package structure 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate. The formation of the package structure 100 can be completed with the formation of the solder balls 110c.

[0132] FIG. 7A is a flowchart illustrating a method of forming a package structure 100 according to one or more embodiments. Step 610 includes forming a package cap including package cap foot portions, a package cap plate portion connecting the package cap foot portions, and a plurality of fins extending from the package cap foot portions. Step 620 includes attaching an interposer module to a package substrate. Step 630 includes placing a thermal interface material (TIM) layer on the interposer module. Step 640 includes attaching the package cap to the package substrate such that the plurality of fins of the package cap plate portion extend into the TIM layer above the interposer module.

[0133] FIG. 7A The illustrated method is not intended to limit the method to the particular sequence of steps. As shown, for example, the formation of the package cap in step 610 can occur at any time prior to the attachment of the package cap 130 to the package substrate 110. The formation of the package cap in step 610 need not occur prior to the attachment of the interposer module 120 to the package substrate 110 and / or the placement of the TIM layer 170 on the interposer module 120.

[0134] FIG. 1A to FIG. 1C is a vertical cross-sectional view of a package structure 100 having a first alternative design according to one or more embodiments. As FIG. 2A to FIG. 3E shown, in the first alternative design, the fins 130f can have a circular shape. In particular, the fins 130f can have arc-shaped end portions that extend into (e.g., are embedded in) the TIM layer 170. The width, thickness, and pitch of the fins 130f in the first alternative design can be substantially the same as the width W 130f , thickness T 130f , and pitch P 130fThe same (see FIG. 7B ). The fins 130f in the first alternative design can be formed in substantially the same manner as the fins 130f in the original design (see FIG. 7B ).

[0135] FIG. 7C is a perspective view of a portion of the fins 130f in the package structure 100 having a first alternative design according to one or more embodiments. As FIG. 7C shown, the fins 130f in the first alternative design can have a cylindrical shape extending from the bottom surface S 130p of the package cap portion 130p. The arc-shaped end portions of the fins 130f can include a hemispherical shape at the distal end of the cylindrical shape.

[0136] FIG. 4 shows the bottom surface of the package cap 130 of the package structure 100 having a first alternative design according to one or more embodiments. As FIG. 1A to FIG. 1C shown, in the first alternative design, the fins 130f can have a circular cross-section. The layout of the fins 130f in the first alternative design can be substantially similar to the layout of the fins 130f in the original design (see FIG. 8 ). The pitch of the fins 130f in the first alternative design can be substantially the same as the pitch P 130f of the fins 130f in the original design (see FIG. 8 ). An optional plating layer 130m can be formed on the fins 130f. The optional plating layer 130m can have a size and shape that is substantially similar to the size and shape of the optional plating layer 130m in the original design.

[0137] FIG. 1A to FIG. 1C is a vertical cross-sectional view of the package structure 100 having a second alternative design according to one or more embodiments. FIG. 1A to 8 The second alternative design in the package structure 100 can be substantially similar to the original design (see FIG. 1A to FIG. 8However, a second alternative design of the package structure 100 can include a first intermetallic compound (IMC) layer 873 in the interface of the TIM layer 170 and the backside metal layer 151 (e.g., the indium / BSM interface). The second alternative design of the package structure 100 can also include a second intermetallic compound layer 874 in the interface of the TIM layer 170 and the bonding of the package cap portion 130p (e.g., the indium / plating layer interface). Each of the first and second intermetallic compound layers 873 and 874 can have a thickness in a range of about 0.5 pm to about 2.0 pm (e.g., about 1.0 pm). Each of the first and second intermetallic compound layers 873 and 874 can include, for example, Au-In, Ni-In, Ni-Au-In, or the like.

[0138] Referring now to FIG. 1A to FIG. 8 , the package structure 100 can include a package substrate 110, an interposer module 120 on the package substrate 110, a thermal interface material (TIM) layer 170 on the interposer module 120, and a package cap 130 on the TIM layer 170. The package cap 130 can include a package cap leg portion 130a attached to the package substrate 110, a package cap plate portion 130p connected to the package cap leg portion 130a, and a plurality of fins 130f extending from the package cap plate portion 130p into the TIM layer 170 above the interposer module 120.

[0139] In one embodiment, the TIM layer 170 can include a low melting point metal. In one embodiment, the low melting point metal can include at least one of indium, gallium, silver, or tin. In one embodiment, the package cap plate portion 130p can include a bottom surface S 130p extending from the bottom surface S 130p In one embodiment, the TIM layer 170 contacts the bottom surface S 130p of the package cap plate portion 130p in the gaps G between the plurality of fins 130f. In one embodiment, the TIM layer 170 can have a first thickness T1 130p between the bottom surface S 170 of the package cap plate portion 130p and the interposer module 120, and a second thickness T2 170 less than the first thickness T1 170 and between the plurality of fins 130f and the interposer module 120. In one embodiment, the thickness T 130f of the plurality of fins 130f can be in a range of 25 pm to 100 pm. The pitch P 130f of the plurality of fins 130f can be in a range of 1 mm to 5 mm. In one embodiment, the width W130f may be in a range of 100 pm to 1000 pm. In one embodiment, the plurality of fins 130f can include a square pillar shape and the square end portions of the plurality of fins 130f can be embedded in the TIM layer 170. In one embodiment, the interposer module 120 can include a backside metal (BSM) layer 151 and the TIM layer 170 can be on the backside metal layer 151. In one embodiment, the package cap 130 can include a plating layer 130m on the plurality of fins 130f and on a bottom surface S 130p , and the plating layer 130m contacts an upper surface of the TIM layer 170. In one embodiment, the package structure 100 can further include a first intermetallic compound (IMC) layer 873 between the TIM layer 170 and the backside metal layer 151, and a second intermetallic compound layer 874 between the package cap plate portion 130p and the TIM layer 170. In one embodiment, the first intermetallic compound layer 873 and the second intermetallic compound layer 874 can have a thickness in a range of 0.5 pm to 2.0 pm.

[0140] Referring again to FIG. 7A to FIG. 7C , a method of forming the package structure 100 can include forming a package cap 130 including a package cap leg portion 130a, a package cap plate portion 130p connected to the package cap leg portion 130a, and a plurality of fins 130f extending from the package cap plate portion 130p; attaching the interposer module 120 to the package substrate 110; placing a thermal interface material (TIM) layer 170 on the interposer module 120; and attaching the package cap 130 to the package substrate 110 such that the plurality of fins 130f in the package cap plate portion 130p extend into the TIM layer 170 above the interposer module 120.

[0141] In one embodiment, the forming of the package cap 130 can include forming the plurality of fins 130f to have a thickness in a range of 25 pm to 100 pm, a pitch in a range of 1 mm to 5 mm, and a width in a range of 100 pm to 1000 pm. In one embodiment, the forming of the package cap 130 can include forming the plurality of fins 130f to be formed as a cylindrical shape having end portions including an arc shape, and the attaching of the package cap 130 to the package substrate 110 includes embedding the arc-shaped end portions into the TIM layer 170. In one embodiment, the interposer module 120 can include a backside metal layer 151, and the placing of the TIM layer 170 on the interposer module 120 can include placing the TIM layer 170 on the backside metal layer 151 of the interposer module 120. In one embodiment, the package cap 130 can include a plating layer 130m on the plurality of fins 130f and on a bottom surface S 130pThe attaching of the encapsulation lid 130 to the encapsulation substrate 110 can include contacting the plating layer 130m with the upper surface of the TIM layer 170.

[0142] Referring again to ​ , in particular ​ An encapsulation structure 100 can include an encapsulation substrate 110, an interposer module 120 located on the encapsulation substrate 110 and including a plurality of semiconductor dies, a metal thermal interface material (TIM) layer 170 located on the interposer module 120, and an encapsulation lid 130 located on the metal TIM layer 170.

[0143] In at least one embodiment, the encapsulation lid 130 can include an encapsulation lid foot portion 130a attached to the encapsulation substrate 110, an encapsulation lid plate portion 130p over the interposer module 120 and connected to the encapsulation lid foot portion 130a, and a plurality of fins 130f extending from the encapsulation lid plate portion 130p into the metal TIM layer 170 over the plurality of semiconductor dies of the interposer module, wherein the plurality of fins 130f can include a cylindrical shape, and arcuate shaped end portions of the plurality of fins 130f can be embedded into the metal TIM layer 170.

[0144] The foregoing outlines features of several embodiments so that a technical person in possession of the disclosure can better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that they can readily apply the disclosure as a basis for the design or modification of other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A package structure, characterized by, Comprising: a package substrate; an interposer module on the package substrate; a thermal interface material layer on the interposer module; and a package cap on the thermal interface material layer, the package cap comprising: a package cap foot portion attached to the package substrate; a package cap plate portion connected to the package cap foot portion; and a plurality of fins extending from the package cap plate portion to the thermal interface material layer above the interposer module. The thermal interface material layer comprises a low melting point metal.

2. The package structure of claim 1, wherein, The package cap plate portion comprises a bottom surface that abuts the package cap foot portion and the plurality of fins extend from the bottom surface.

3. The package structure of claim 1, wherein, The thermal interface material layer contacts the bottom surface of the package cap plate portion at gaps between the plurality of fins.

4. The package structure of claim 3, wherein, The thermal interface material layer has a first thickness between the bottom surface of the package cap plate portion and the interposer module and a second thickness less than the first thickness between the plurality of fins and the interposer module.

5. The package structure of claim 1, wherein, The interposer module comprises a backside metal layer and the thermal interface material layer is on the backside metal layer.

6. The package structure of claim 1, wherein, The package cap further comprises a plating layer on the plurality of fins and on the bottom surface of the package cap plate portion and the plating layer contacts an upper surface of the thermal interface material layer.

7. The package structure of claim 6, wherein, Further comprising:

8. The package structure of claim 7, wherein, a first intermetallic compound layer between the thermal interface material layer and the backside metal layer; and a second intermetallic compound layer between the package cap plate portion and the thermal interface material layer. Comprising: a package substrate; 9. A package structure, characterized by, an interposer module on the package substrate and comprising a plurality of semiconductor dies; a metal thermal interface material layer on the interposer module; and a package cap on the metal thermal interface material layer, comprising: a package cap foot portion attached to the package substrate; a package cap plate portion on the interposer module and connected to the package cap foot portion; and a plurality of fins extending from the package cap plate portion into the metal thermal interface material layer on the plurality of semiconductor dies of the interposer module, wherein the plurality of fins comprise a cylindrical shape and arcuate shaped ends of the plurality of fins are embedded into the metal thermal interface material layer. ​ ​ ​

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