Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure. The semiconductor structure comprises an interconnection structure and a thermal sensing device which are arranged on a semiconductor substrate. The thermal sensing device includes a first transistor, a second transistor, a first capacitor coupled to the first transistor, a second capacitor coupled to the second transistor, and a metallization pattern embedded in the interconnect structure and acting as a resistive heater. At least one of the groups of the first and second transistors is selected to be embedded in the interconnect structure. By configuring the measurement circuit of the thermal sensing device in the interconnect structure, the footprint of the circuit area / device can be saved and the low resistance of the thermal sensing device provides efficient operation and reduces energy consumption.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure, and more particularly, to a semiconductor structure with a thermal sensor. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth. In large part, this growth can be attributed to a continual improvement in integration density with each new generation of ICs. This improvement in integration density translates to more functionality available on a given chip, which in turn translates to increased performance. High device densities can generate high amounts of heat, which can result in decreased performance. Thermal sensors can be needed to monitor and control heat generation. While existing semiconductor structures with thermal sensors are generally adequate for their intended purposes, they have met with only limited success. SUMMARY

[0003] Embodiments of the present application provide a semiconductor structure including a first interconnect structure disposed over a first semiconductor substrate and a thermal sensor device, the thermal sensor device including a first transistor and a second transistor, a first capacitor and a second capacitor coupled to the first transistor and the second transistor, respectively, and a metallization pattern embedded in the first interconnect structure and functioning as a resistive heater. The metallization pattern is embedded in the first interconnect structure from at least one selected from a group of the first transistor and the second transistor.

[0004] Embodiments of the present application provide a semiconductor structure including an interconnect structure over a semiconductor substrate and a thermal sensor device including a resistive component and a filtering component, the resistive component embedded in the interconnect structure and functioning as a heater, the filtering component coupled to the resistive component and allowing signals to pass between selected frequency ranges, the filtering component including a transistor and a capacitor connected to the transistor.

[0005] Based on the above, the embodiments of the present application provide a semiconductor structure with a thermal sensor device embedded in one or more tiers of the semiconductor structure to monitor the temperature of hot spots on the chip in real time. The thermal sensor device arranged in the corresponding tier can be configured to establish a heat map of the entire semiconductor structure, thereby enabling control of the temperature of the integrated circuit. The measurement circuit applied to the thermal sensor device can be integrated into the semiconductor circuit manufactured by the front-end-of-line process, the middle-of-line process, the back-end-of-line process, or any combination thereof. The thermal sensor device formed from materials compatible with the front-end-of-line process and / or the back-end-of-line process enables the transient electro-thermal sensor system to be more easily integrated into the resulting structure. Since the measurement accuracy depends on the voltage source and the filter / conversion circuit, the resistance of the thermal sensor device can be relatively small. The low resistance of the thermal sensor device provides efficient operation and reduces energy consumption. By configuring the measurement circuit in the interconnect structure, the occupied space of the circuit area / device can be saved.

[0006] In order to make the above features and advantages of the embodiments of the present application more apparent, specific embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 、 Figure 2A 、 Figure 3A and Figures 4-7 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor structure with a thermal sensor according to some embodiments.

[0008] Figure 2B and Figure 3B show schematic cross-sectional views of variants of the structures shown in Figure 2A and Figure 3A respectively, according to some embodiments.

[0009] Figure 8 shows a schematic cross-sectional view of a semiconductor structure according to some embodiments.

[0010] Figure 9 shows a schematic circuit diagram of a measurement circuit for a thermal sensor according to some embodiments.

[0011] Figure 10A shows a schematic top view of a layer of an interconnect structure in which a thermal sensor is located according to some embodiments.

[0012] Figure 10B shows a schematic cross-sectional view of a portion of a thermal sensor in an interconnect structure according to some embodiments.

[0013] REFERENCE NUMERALS

[0014] 10A, 10B: semiconductor structure; 10HS: hot spot; 101: filter; 102: redistribution structure; 103: conductive terminal; 111, 111': semiconductor substrate; 111a: front side; 111b, 111b': back side; 112: device; 112P: conductive plug; 114: via / TSV; 114a: first end; 114b: second end; 115: interconnect structure; 116: thermal sensing device; 116C: post-CMOS device / capacitor component; 116M, 116M': measurement circuitry; 116S: metallization pattern / resistive component; 116T: pre-CMOS device / pre-CMOS transistor; 116T': post-CMOS device; 117: bonding layer; 117': front-side bonding layer; 118': bonding layer / back-side bonding layer; 121: carrier; 122: heat spreading component; 131: through-level via; 1021, 1151: dielectric layer; 1022, 1152: conductive layer; 1131: interlayer dielectric / ILD layer; 1151a, 1151b, 1151c, 1151d, 1151e, 1151f, 1151g, 1151h: dielectric sublayer; 1161c: second portion; 1161v: first portion; 1162C: channel layer; 1162G: gate electrode; 1162GD: gate dielectric layer; 1162SD: source / drain contact; 1171, 1181: bonding dielectric layer; 1172, 1182: bonding feature; A1: amplifier; C H , C L : capacitor; IF1: bonding interface; M1, M2, M3, M4, M5, M6, M7, M8, Mn, Mn+1, Mn-1: conductive sublayer; R S , R T : resistor; T1: first level; T2: second level; Tx: topmost level. DETAILED DESCRIPTION

[0015] The following disclosure provides different embodiments or examples, for implementing different features of the present disclosure. Specific examples of structures and arrangements are set forth in the following description for the purpose of simplification. These are, of course, merely examples and are not intended to limit the scope of the present disclosure. For example, the phrase "on top of" or "on" a second feature as used in the following description means that the first feature can be formed directly in contact with the second feature, or that additional features can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure can use component numbers and / or letters repeatedly in various examples. Such repetition is for the purpose of simplifying and clarifying the description of the present disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0016] Moreover, spatial or directional terms, such as "below," "lower," "bottom," "top," "upper," and the like, can be used herein for ease of describing the applicable structure. The apparatus can be oriented in different directions, and terms should be construed to encompass alternative orientation(s) of the device, unless otherwise noted.

[0017] High device density brought by advanced transistors can generate heat, and accumulation of heat in a semiconductor structure can cause performance degradation. Embodiments discussed herein provide a semiconductor structure including one or more thermal sensors, which can be configured to monitor temperature of hot spots on a chip in real time and establish a 2D / 3D temperature profile of the semiconductor structure. The thermal sensors can be fabricated through front-end-of-line (FEOL) and / or back-end-of-line (BEOL) and can be formed of materials compatible with the FEOL and / or BEOL. It should be noted that the terms "thermal sensor" and "thermal sensing device" are used interchangeably herein.

[0018] Figure 1 、 Figure 2A 、 Figure 3A and Figures 4-7 show schematic cross-sectional views of intermediate stages in the fabrication of a semiconductor structure with thermal sensors according to some embodiments. Figure 2B and Figure 3B show schematic cross-sectional views of variations of the structures shown in Figure 2A and Figure 3A respectively. The fabrication methods described below are merely examples and the disclosure is not limited thereto. Additional steps can be provided before, during, and after the described methods, and some steps of the described methods can be replaced, eliminated, or moved to a different position. For the sake of brevity, not all steps are described in detail. In addition, throughout this document and in various embodiments, like reference numerals refer to like features having similar structures and compositions, unless otherwise indicated.

[0019] Reference is made to Figure 1semiconductor substrate 111 is in wafer form, chip form, panel form, etc. The semiconductor substrate 111 can include a front side 111a (or active surface) and a back side 111b opposite the front side 111a. The semiconductor substrate 111 can include one or more semiconductor materials (e.g., silicon, germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates, such as multilayer or graded substrates, can also be used.

[0020] In some embodiments, one or more devices 112 can be formed at the front side 111a of the semiconductor substrate 111. The devices 112 can be active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, inductors, etc.), combinations thereof, and / or the like. The devices 112 can be or include one or more high power devices and / or one or more low power devices. It should be understood that while the devices 112 are represented by transistors, the devices 112 can have different numbers and types than shown. In some embodiments, the devices 112 are formed using suitable front-end-of-line processes and can be referred to as front-end-of-line (FEOL) devices 112. In some embodiments, a portion of the devices 112 (e.g., front-end-of-line devices 116T) are included in measurement circuitry applied in thermal sensing devices (e.g., labeled 116M in Figure 2A In some embodiments, the front-end-of-line devices 116T are included in control circuitry of the thermal sensing device for dynamically controlling the temperature of the overall semiconductor structure. In alternative embodiments, the thermal sensing device does not include front-end-of-line devices, where the transistors of the thermal sensing device are formed by subsequent execution of back-end-of-line processes.

[0021] With continued reference to Figure 1An inter-layer dielectric (ILD) layer 1131 is formed over the front side 111a of the semiconductor substrate 111 to surround and cover the device 112. The ILD layer 1131 can include one or more dielectric materials, such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or combinations thereof. In some embodiments, conductive plugs 112P are formed and extend through the ILD layer 1131 to electrically and physically couple to the device 112. The conductive plugs 112P can be formed of W, Co, Ni, Cu, Ag, Au, Al, alloys, the like, or combinations thereof, and can be formed by a middle-end-of-line (MEOL) process. For example, when the device 112 is a transistor, the conductive plugs 112P can be coupled to the gate and source / drain (S / D) regions of the transistor. It should be noted that the S / D regions can refer to either the source or drain, alone or collectively, depending on the context. Although the conductive plugs are shown as being formed in the same profile, it should be understood that each conductive plug 112P coupled to the gate and S / D regions can be formed in a different profile, which can avoid shorting of the contacts. In some embodiments, a portion of the conductive plugs 112P (e.g., 112PT) is included in the thermal sensing device, which will be described in more detail later. Alternatively, the conductive plugs 112P are not included in the thermal sensing device.

[0022] Referring to Figure 2A and referring to Figure 1An interconnect structure 115 can be formed over the front side 111a of the semiconductor substrate 111. For example, the interconnect structure 115 is formed on the ILD layer 1131 and the conductive plug 112P by back-end-of-line processes. In some embodiments, the interconnect structure 115 includes one or more dielectric layers 1151 and one or more conductive layers 1152 covered by the dielectric layers 1151. The dielectric layers 1151 can include one or more dielectric materials, such as low-k dielectric materials (e.g., PSG, BPSG, Spin-On-Glass (SOG), silicon carbon materials, combinations thereof, etc.) or any suitable dielectric material. The dielectric layers 1151 can be referred to as metal-inter-metal dielectric (IMD) layers. For example, the dielectric layers 1151 include a plurality of inter-metal dielectric sub-layers (e.g., 1151a, 1151b, 1151c, 1151d, 1151e, 1151f, and 1151g), which can have the same material or include different materials. It should be understood that although seven inter-metal dielectric sub-layers are shown, the dielectric layers 1151 can include more than seven inter-metal dielectric sub-layers or less than seven inter-metal dielectric sub-layers, depending on the circuit and product requirements.

[0023] The conductive layers 1152 can be interconnected with the devices 112 through the conductive plug 112P to form functional circuits. The conductive layers 1152 can include one or more conductive materials, such as Ti, Cu, Ni, Ag, Au, Al, alloys, the like, or combinations thereof. In some embodiments, the conductive layers 1152 include a plurality of interconnect sub-layers (e.g., M1, M2, M3, M4, M5, M6, and M7), which can be formed of the same material or include different materials. For example, each of the interconnect sub-layers is embedded in a corresponding one of the inter-metal dielectric sub-layers. In some embodiments, each interconnect sub-layer includes a wire, a via, a conductive pad, a combination thereof, etc. The vias in the conductive layers 1152 can pass through the plane of and provide electrical connections between adjacent sub-layers. In some embodiments, the size and pitch of the upper interconnect sub-layers are greater than the size and pitch of the lower interconnect sub-layers. It should be understood that although seven interconnect sub-layers are shown, the conductive layers 1152 can include more than seven interconnect sub-layers or less than seven interconnect sub-layers, depending on the circuit and product requirements.

[0024] With continued reference to Figure 2AOne or more thermal sensing devices 116 (also referred to as thermal / temperature sensors) can be embedded in the interconnect structure 115. The thermal sensing devices 116 can or can not be electrically isolated from the conductive layers 1152 in the functional circuitry of the resulting semiconductor structure. In some embodiments, the materials and formation methods of the thermal sensing devices 116 are compatible with back-end-of-line / middle-of-line / front-end-of-line. For example, a portion of the one or more thermal sensing devices 116 embedded in the interconnect structure 115 is fabricated by back-end-of-line, a portion of the one or more thermal sensing devices 116 embedded in the ILD layer 1131 is fabricated by middle-of-line, and / or a portion of the one or more thermal sensing devices 116 formed at the front side 111a of the semiconductor substrate 111 is fabricated by front-end-of-line.

[0025] In some embodiments, the respective thermal sensing device 116 includes one or more front-end-of-line devices 116T and one or more back-end-of-line devices 116C connected to the front-end-of-line devices 116T. For example, the front-end-of-line devices 116T are implemented by front-end-of-line transistors 116T and can be formed at the same level as the devices 112. The back-end-of-line devices 116C can be implemented by capacitive components (or capacitors) 116C. For example, the front-end-of-line devices 116T and the back-end-of-line devices 116C are included in the measurement circuit 116M of the thermal sensing device 116. In some embodiments, the respective thermal sensing device 116 includes one or more metallization patterns 116S. In some embodiments, the metallization patterns 116S are formed of one or more conductive materials compatible with back-end-of-line and can be formed by processes compatible with back-end-of-line. The one or more materials of the metallization patterns 116S can include W, Ru, TiN, TaN, combinations thereof, the like, etc. In some embodiments, a portion (e.g., 112PT) of the metallization patterns 116S is formed in the ILD layer 1131. For example, the portion (e.g., 112PT) of the metallization patterns 116S includes materials compatible with middle-of-line and can be formed by processes compatible with middle-of-line. The temperature coefficient of resistance (TCR) of the circuit is determined by measuring the resistance over a range of temperatures. The metallization patterns 116S can provide a known TCR.

[0026] In some embodiments, the metallization pattern 116S serves as a sensor component as a heater and at the same time as a thermal sensor. For example, the metallization pattern 116S serves as a resistive heater (or resistive member). Since the resistance of the metallization pattern 116S varies linearly with temperature, the temperature across its length and thickness can be measured by measuring the voltage across it. In some embodiments, the metallization pattern 116S is connected to the front-of-line device 116T. The metallization pattern 116S can be formed in some of the dielectric sub-layers of the dielectric layer 1151. For example, the metallization pattern 116S is formed in / on (e.g., at the same level as and above the conductive sub-layer M4) the dielectric sub-layer 1151d, where the metallization pattern 116S can not be formed below the dielectric sub-layer 1151d. In some embodiments, the metallization pattern 116S is formed in each of the dielectric sub-layers of the dielectric layer 1151.

[0027] In some embodiments, a portion of the metallization pattern 116S is formed in a topmost one (e.g., 1151g) of the dielectric sub-layers of the dielectric layer 1151 that is closest to the subsequently formed bonding layer (e.g., 117 in Figure 3A In some embodiments, the metallization pattern 116S is distributed near areas with sharp local temperature peaks (referred to as hot spots 10HS and labeled in Figures 7-8 In some embodiments, the metallization pattern 116S is distributed near areas / paths with higher thermal bottlenecks that require heater control. The areas / paths with thermal bottlenecks can be devices / areas / paths where the heat flow results in more restriction to other devices / areas / paths in the resulting semiconductor structure. In some embodiments, the metallization pattern 116S is distributed in a denser manner near areas where high power devices are located, and the metallization pattern 116S is distributed in a sparser manner near areas where low power devices are located. The above-described devices for implementing the metallization pattern 116S, the front-of-line device 116T, and the back-of-line device 116C are provided for illustrative purposes. Various types of sensor components, front-of-line devices, and back-of-line devices are within the contemplation of the present disclosure. The metallization pattern 116S, the front-of-line device 116T, and the back-of-line device 116C will be described in more detail with reference to Figure 9 and Figures 10A-10B .

[0028] Reference is made to the structures shown in Figure 2B and Figure 2A , Figure 2B and Figure 2AThe structures shown are similar, and thus detailed descriptions are not repeated. The difference between the two is that the conductive layer 1152 includes an additional conductive sublayer M8 and the dielectric layer 1151 includes an additional dielectric sublayer 1151h. Although eight dielectric sublayers and eight conductive sublayers are shown, the interconnect structure 115 can include more or different numbers of dielectric sublayers and conductive sublayers, depending on the circuit and product requirements. One or more metallization patterns 116S of the thermal sensor device 116 as a heater can be embedded in the dielectric sublayer 1151h. In some embodiments, the metallization pattern 116S formed in the dielectric sublayer 1151h is closest to the subsequently formed bonding layer (e.g. Figure 3B The thermal sensor device 116 is shown in FIG. 11B as a heater. The thermal sensor device 116 can be implemented as a heater, a temperature sensor, or a combination thereof.

[0029] In some embodiments, the front-end-of-line device 116T is replaced by a back-end-of-line device 116T’ and the capacitive component 116C is connected to the back-end-of-line device 116T’. For example, the respective back-end-of-line device 116T’ is surrounded and covered by the dielectric layer 1151. The back-end-of-line device 116C can be disposed on and connected to the back-end-of-line device 116T’. In some embodiments, the back-end-of-line devices (116T’ and 116C) are included in the measurement circuit 116M’ of the thermal sensor device 116. The back-end-of-line device 116T’ can be implemented by a transistor. In some embodiments, the back-end-of-line device 116T’ is used in a thermal sensor by exploiting the threshold voltage of the transistor that varies with temperature. The back-end-of-line device 116T’ can be formed of materials compatible with back-end-of-line processes and by processes compatible with back-end-of-line processes. The materials compatible with back-end-of-line processes can include metal oxides, polysilicon, two-dimensional (2D) materials, carbon nanotubes (CNTs), semiconductor materials of the third-fifth groups, etc.

[0030] In some embodiments, the corresponding back-end-of-line device 116T’ includes a gate electrode 1162G, source / drain contacts 1162SD, a channel layer 1162C disposed below the gate electrode 1162G and laterally between the source / drain contacts 1162SD, and a gate dielectric layer 1162GD vertically interposed between the gate electrode 1162G and the channel layer 1162C. For example, the material of the channel layer 1162C includes a metal oxide (e.g., IGZO, In2O3, InWO, SnO, TaSnO, TiSnO, etc.), polysilicon, a 2D material (e.g., MoS2, WS2, MoSe2, WSe2, MoTe2, etc.), or any suitable channel material compatible with back-end-of-line processing. In some embodiments where the back-end-of-line device 116T’ is a 2D material-based transistor, the channel layer 1162C is formed of one or more 2D materials and can be deposited at low temperature (e.g., below 400 °C or the like) by metal-organic chemical vapor deposition (MOCVD). In some embodiments, the channel layer 1162C is formed of one or more metal oxide materials and / or polysilicon and can be deposited by sputtering or any suitable deposition process. The gate electrode 1162G and the source / drain contacts 1162SD can include one or more conductive materials. In some embodiments, the gate electrode 1162G and the source / drain contacts 1162SD are formed by sputtering or any suitable deposition process. It should be noted that the number and type of back-end-of-line devices 116T’ can be different from what is shown. In some embodiments, a combination of front-end-of-line devices 116T (as shown, for example) and back-end-of-line devices 116T’ are included in the measurement circuit 116M / 116M’. Figure 2A

[0031] In some embodiments, one or more vias 114 can be formed in the semiconductor substrate 111 and through the ILD layer 1131. For example, the via 114 is formed by depositing one or more diffusion barrier or isolation layers in a trench of the ILD layer 1131 and the underlying semiconductor substrate 111, depositing a seed layer, and depositing a conductive material (e.g., W, Ti, Al, Cu, any combination thereof, and / or the like). For example, the via 114 includes a first end 114a that is substantially flush with the ILD layer 1131 and a second end 114b opposite the first end 114a, where at this stage, the second end 114b can be buried in the semiconductor substrate 111. It should be noted that while the via 114 is shown in Figure 2B , the via 114 can also be disposed in the structure shown in Figure 2A . As another option, the via 114 can be omitted or can be formed in a subsequent step (e.g., after the backside thinning process of Figure 4 , or in Figures 5-6 ​formed after the bonding process) so the via 114 is shown in dashed line to indicate that it can or can not be present.

[0032] Referring to Figures 3A-3B and referring to Figures 2A-2B , a bonding layer 117 can be formed on the interconnect structure 115. The bonding layer 117 can be or include one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The dielectric material of the bonding layer 117 can be formed by suitable fabrication techniques such as spin-on, CVD, ALD, PVD, or the like. In some embodiments, the bonding layer 117 includes bonding features (not shown separately but similar to the bonding features 1172 described in Figure 8 ). In some other embodiments, the bonding layer 117 does not have conductive features. In some embodiments, the steps described previously in Figure 1 , Figure 2A and Figure 3A (or Figure 1 , Figure 2B and Figure 3B ) can be repeated to form multiple tiers to be bonded.

[0033] Referring to Figure 4 and referring to Figure 3A , a carrier 121 can be disposed on the bonding layer 117. In some embodiments, the carrier 121 provides mechanical and structural support in the resulting semiconductor structure. The carrier 121 can include any suitable material that is rigid enough to provide support for the underlying structure. For example, the carrier 121 includes silicon (e.g., bulk silicon), metal (e.g., steel), glass, ceramic, combinations thereof, multiple layers thereof, or the like. In some embodiments, the carrier 121 is a temporary carrier for supporting the underlying structure during a process (e.g., a thinning process, a bonding process, a singulation process, etc.) and the temporary carrier can be removed after the process is completed. In some embodiments, the carrier 121 includes one or more thermally conductive materials to facilitate heat dissipation from the underlying structure to an external member or to an overlying structure (if present).

[0034] In some embodiments, a thinning process (e.g., grinding, CMP, etching, combinations thereof, etc.) is performed on the backside of the semiconductor substrate 111 to form a semiconductor substrate 111’ having a backside 111b’. The bonding of the carrier 121 can be performed prior to the thinning process of the semiconductor substrate 111, where the carrier 121 serves as a support during the thinning process. In some embodiments, a bonding layer (not shown but similar to the bonding layer 118’ described in Figure 8 ) is formed on the backside 111b’ of the semiconductor substrate 111’ for a backside bonding process. It should be noted that while the structure shown in Figure 4 is based onFigure 3A the aforementioned steps, but Figure 3B structures of

[0035] Referring to Figure 5 and referring to Figure 4 and Figure 3B , a bonding process can be performed. In the illustrated embodiment, structures in Figure 4 as second tiers T2 are bonded together with structures in Figure 3B as first tiers T1. As an alternative, structures in Figure 4 as second tiers T2 can be bonded with structures in Figure 3A as first tiers T1. The bonding can involve wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, or the like. In some embodiments in which die-to-wafer bonding or die-to-die bonding will be performed, Figure 3B and / or Figure 3A (or Figure 4 ) as illustrated can be singulated prior to bonding to form a plurality of dies. In the illustrated embodiment, the bonding layer 117 of the first tiers T1 is bonded to the semiconductor substrate 111’ of the second tiers T2 by dielectric-to-semiconductor (e.g., oxide-to-silicon) bonding.

[0036] In some embodiments in which a bonding layer (e.g., labeled 118’ in Figure 8 is formed on the backside 111b’ of the semiconductor substrate 111’, the bonding of the first tiers T1 and the second tiers T2 includes dielectric-to-dielectric (e.g., oxide-to-oxide) bonding. In some embodiments in which the bonding layer (e.g., labeled 118’ in Figure 8 on the backside 111b’ of the semiconductor substrate 111’ and the bonding layer 117 of the first tiers T1 includes metal features, the bonding of the first tiers T1 and the second tiers T2 includes metal-to-metal (e.g., copper-to-copper) bonding, dielectric-to-dielectric (e.g., oxide-to-oxide) bonding, and / or dielectric-to-metal (e.g., oxide-to-copper) bonding. Various bonding methods are within the contemplation of the present disclosure.

[0037] Referring to Figure 6 and referring to Figure 5The carrier 121 of the second tier T2 can be removed by any suitable removal process (e.g., grinding, etching, stripping, the like, combinations thereof, etc.) in some embodiments, multiple tiers are sequentially stacked on and bonded to the second tier T2 using the bonding method described in the preceding paragraph to form a bonded structure of multiple tiers. The stacking / bonding process can continue until the stacked / bonded structure has a desired number of tiers. For example, the bonded structure includes the first tier Tl, the second tier T2 stacked on and bonded to the first tier Tl, and a topmost tier Tx stacked on the second tier T2. In alternative embodiments, the bonded structure is a two-tier structure that includes the topmost tier Tx and the first tier Tl (or the second tier T2) bonded together. The number of tiers can vary depending on the design requirements of the resulting semiconductor structure. In addition, while the topmost tier Tx is shown as having a similar structure to the other tiers, the thermal sensor device 116 in the topmost tier Tx can be replaced with the thermal sensor device 116 shown in FIG. 1 IB according to some embodiments. Figure 4 Figure 3B

[0038] In some embodiments, one or more through-tier vias 131 can be formed in the bonded structure to provide electrical interconnections between adjacent tiers. For example, the through-tier via 131 is formed by depositing one or more diffusion barrier or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., Cu, Ti, Ta, Al, alloys, any combination thereof, and / or the like) in the trench of each tier. The respective through-tier via 131 can be a long via that passes through multiple tiers and lands on a conductive pad of the interconnect structure 115 in the first tier Tl (or a tier above the first tier Tl). In some embodiments, the through-tier via 131 is laterally and electrically in contact with the conductive layer 1152 of the interconnect structure 115 in multiple tiers (e.g., T2, Tx, and tiers between T2 and Tx). In some other embodiments, the respective through-tier via 131 includes multiple segments, and a lowermost segment can pass through an entire tier (e.g., the second tier T2) and extend to an upper portion of an underlying tier (e.g., the first tier Tl) to land on a conductive pad of the interconnect structure 115 in the first tier Tl, where adjacent segments of the through-tier via 131 can be connected by a conductive feature (e.g., a conductive pad or the like; not shown). The through-tier via 131 can be formed after the stacking / bonding process is completed. In some other embodiments, the through-tier via 131 is formed after two (or more) tiers are bonded together and before additional tiers are bonded thereon.

[0039] ​​For the topmost tier Tx, the carrier 121 can remain on top (e.g., disposed on the bonding layer 117). The through-tier via 131 in the topmost tier Tx can not extend through the bonding layer 117. In some embodiments, one end of the through-tier via 131 in the topmost tier Tx is located within the interconnect structure 115 of the topmost tier Tx. For example, one end of the through-tier via 131 in the topmost tier Tx is in direct contact with a lower surface of the bonding layer 117. In some other embodiments, one end of the through-tier via 131 in the topmost tier Tx lands on a conductive pad (not shown separately) of the interconnect structure 115 of the topmost tier Tx.

[0040] Referring to Figure 7 and referring to Figure 6 A plurality of conductive terminals 103 can be formed below the first tier T1. The conductive terminals 103 can comprise a conductive material, such as solder, Cu, Al, Ag, Ni, Au, the like, or a combination thereof. The conductive terminals 103 can be or include ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed of electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. In some embodiments, the semiconductor substrate 111 of the first tier T1 is thinned to expose the through-hole 114 in an accessible manner before the conductive terminals 103 are formed for further electrical connection. In some other embodiments where the through-hole 114 is not formed in the previous step, the semiconductor substrate 111 of the first tier T1 is thinned, and then the through-hole 114 is formed through the semiconductor substrate 111’. According to some embodiments, since the through-hole 114 penetrates through the semiconductor substrate 111’, the through-hole 114 can be referred to as a through substrate via (TSV) 114.

[0041] In some embodiments, after the TSVs 114 are exposed / forming, a redistribution structure 102 is formed on the backside 111b' of the semiconductor substrate 111' of the first tier T1. The redistribution structure 102 can include a dielectric layer 1021 and a conductive layer 1022 formed in / on the dielectric layer 1021 and electrically connected to the TSVs 114. In some embodiments, the conductive terminals 103 are formed after the redistribution structure 102 is formed. For example, the conductive terminals 103 are formed on the conductive layer 1022 of the redistribution structure 102 (e.g., under bump metallization (UBM) pads or the like). It should be noted that the above-described order is merely an example and the present disclosure is not limited thereto. In alternative embodiments where the TSVs 114 are omitted, the conductive layer 1022 of the redistribution structure 102 can be in electrical and physical contact with the through-tier vias 131. Other one or more electrical paths can be formed in / on the bonded structure to provide external electrical connections to the circuits and devices of the resulting semiconductor structure.

[0042] In some embodiments, a heat dissipation member 122 is disposed on the topmost tier Tx. The heat dissipation member 122 can be formed of a material having high thermal conductivity (e.g., steel, stainless steel, copper, the like, combinations thereof, or any material having good thermal conductivity) for dissipating heat. In some embodiments, the heat dissipation member 122 is coated with another metal. The heat dissipation member 122 can be a single continuous material or can include multiple components having the same or different materials. The heat dissipation member 122 can be or include a heat sink, a heat spreader, a lid, or the like. The heat dissipation member 122 is shown for illustrative purposes and the heat dissipation member 122 can be provided in any suitable form (e.g., plate-like, fin-like, or the like).

[0043] In some embodiments, the heat dissipation member 122 is attached to the carrier 121 of the topmost tier Tx by an adhesive (not shown separately). The adhesive can be an epoxy, a glue, or the like and can include a thermally conductive material or any material capable of transferring heat. The heat dissipation member 122 can be thermally coupled to the underlying structure by the adhesive. The adhesive can be deposited at the intended location to allow the heat dissipation member 122 to be attached to the carrier 121. As another alternative, the carrier 121 of the topmost tier Tx is omitted and the heat dissipation member 122 is directly bonded to the bonding layer 117 of the topmost tier Tx. In alternative embodiments, the heat dissipation member 122 is omitted. It should be noted that the heat dissipation member 122 can be any type of heat dissipation mechanism that satisfies the heat dissipation needs of the resulting structure.

[0044] In some embodiments, singulation processes are performed to cut the bonded structure into a plurality of semiconductor structures 10A. The respective semiconductor structures 10A can then be packaged or coupled to another packaging member as desired. In some embodiments, after singulation, a heat spreading member 122 is coupled to the topmost tier Tx such that the lateral size of the heat spreading member 122 is greater than the lateral size of the underlying singulated structure. In alternative embodiments, the lateral size of the heat spreading member 122 is substantially equal to or less than the lateral size of the underlying singulated structure.

[0045] Figure 8 A schematic cross-sectional view of a semiconductor structure is shown in accordance with some embodiments. Like reference numbers indicate like features having similar structures and compositions, unless otherwise specified. Reference is made to Figure 8 and reference is made to Figure 7 , Figure 8 The semiconductor structure 10B shown can be similar to the semiconductor structure 10A shown in Figure 7 , and thus detailed descriptions are not repeated for brevity. The difference between the two is the bonding mechanism of the adjacent tiers and the omission of the through-tier vias. For example, the front-side bonding layer 117’ of the first tier T1 includes a bonding dielectric layer 1171 and one or more bonding features 1172 laterally covered by the bonding dielectric layer 1171. The respective bonding features 1172 can include one or more electrically conductive materials, such as Cu, Ti, Ta, alloys, the like, combinations thereof, and the like. The respective bonding features 1172 can be or include electrically conductive pads, vias, and / or the like and can be electrically connected to the electrically conductive layers 1152 of the underlying interconnect structure 115. The bonding surfaces of the bonding dielectric layer 1171 and the bonding surfaces of the bonding features 1172 can be substantially planar (or coplanar) within a process variation range.

[0046] The topmost tier Tx can include a backside bonding layer 118' that is directly bonded to the frontside bonding layer 117'. The backside bonding layer 118' of the topmost tier Tx can include a bonding dielectric layer 1181 and one or more bonding features 1182 laterally covered by the bonding dielectric layer 1181. In some embodiments, in the topmost tier Tx, the bonding features 1182 are electrically coupled to the conductive layers 1152 of the interconnect structure 115 through the TSVs 114. The bonding dielectric layer 1181 and the bonding features 1182 can be similar to the bonding dielectric layer 1171 and the bonding features 1172, respectively. The bonding surfaces of the bonding dielectric layer 1181 and the bonding surfaces of the bonding features 1182 can be substantially planar (or coplanar) within a process variation range. The bonding dielectric layer 1181 can be bonded to the bonding dielectric layer 1171 through a dielectric-to-dielectric (e.g., oxide-to-oxide) bonding. The bonding features 1182 can be bonded to the bonding features 1172 in a one-to-one manner through a direct metal-to-metal (e.g., copper-to-copper) bonding. Depending on product requirements, the bonding features (1172 and 1182) can be pad-to-pad bonding, via-to-via bonding, or via-to-pad bonding. In some embodiments, a metal-to-dielectric (e.g., copper-to-oxide) bond can be formed at the bonding interface IF1 of the bonded tiers. The bonding interface IF1 can be substantially planar and / or flat.

[0047] In the illustrated embodiment, the topmost tier Tx is stacked on and bonded to the first tier T1, with the backside bonding layer 118' of the topmost tier Tx directly bonded to the frontside bonding layer 117' of the first tier T1. In some embodiments, one or more tiers can be interposed between the topmost tier Tx and the first tier T1, and can be bonded to the topmost tier Tx and the first tier T1 through the same / similar bonding mechanism. The bonding mechanism of the multiple tiers in the semiconductor structure 10B can be considered as front-to-front bonding. In alternative embodiments, front-to-front bonding (e.g., the frontside bonding layer 117' of an upper tier bonded to the frontside bonding layer 117' of a lower tier) or back-to-back bonding (e.g., the backside bonding layer 118' of an upper tier bonded to the backside bonding layer 118' of a lower tier) can be applied depending on product design. It should be understood that while the bonding mechanism has been described as connecting an upper tier to a lower tier, alternative connection schemes are possible and the bonding interface is adjusted accordingly. In addition, the semiconductor structure 10B can have a different number of tiers and arrangement than illustrated.

[0048] Figure 9A schematic circuit diagram of a measurement circuit for a thermal sensor is shown in accordance with some embodiments. It is noted that the circuit is merely an exemplary circuit in connection with the method of the embodiments and does not limit the embodiments and the disclosure. In addition, the following discussion applies to a 3-omega (3ω) measurement method of the measurement circuit. For example, using the 3ω measurement method, on-chip measured parameters (e.g., temperature, thermal conductivity, heat capacity, thermal diffusivity, etc.) can be obtained.

[0049] Referring to Figure 9 and referring to Figure 7 or Figure 8 The measurement circuit 116M (or 116M’) applied in the thermal sensing device 116 can be formed in any level of the semiconductor structure 10A / 10B. The measurement circuit 116M (or 116M’) can be thermally and / or electrically coupled to the hot spot 10HS for temperature measurement. In some embodiments, the measurement circuit 116M (or 116M’) includes a metallization pattern 116S (e.g., a resistive member) to provide a resistance R T , where the subscript “T” can represent “thermal”. The resistive member 116S can be coupled to an input voltage V1ω, where the voltage V1ω can be an oscillating (or sinusoidal) voltage signal at a frequency of 1ω. When the voltage V1ω is configured to affect the resistive member 116S at a frequency of ω, a periodic heating is generated in the resistance R T of the resistive member 116S at a frequency of 2ω, which results in a heating portion at a frequency of 3ω. In other words, the input current heats the resistive member 116S at a frequency of 2ω, resulting in an oscillation of temperature rise at a frequency of 2ω. Since the resistance R T of the resistive member 116S is linearly related to temperature, the heating portion experiences a voltage drop at a frequency of 3ω, which can be used to estimate the amplitude of the temperature oscillation. The reading of the voltage V3ω can be used to calculate the amplitude from equation (1):

[0050] V3ω = (1 / 2) V0βΔT oscill (1)

[0051] where in equation (1), ΔT oscill is the extent of the temperature oscillation, β is the thermal coefficient of resistance of the metallization pattern 116S, and V0 is based on the resistance R0 without the periodic heating (V0 = I0*R0). The background temperature can be calculated from V0 by pre-calibration.

[0052] Since Fourier's law is the fundamental law of thermal conductivity and thermal resistance is the inverse of thermal conductivity, measuring V3ω and solving the specific Fourier's law can yield the local effective thermal resistance. The parameters measured on the chip (e.g., temperature, thermal conductivity, heat capacity, thermal diffusivity, etc.) can be obtained by using the 3ω measurement and solving the Fourier's law. In some embodiments, the output of the resistive member 116S is coupled to a filter 101. The measurement circuit 116M (or 116M') can include an amplifier Al coupled to the filter 101 and a circuit output terminal. The front-end process device 116T (or the back-end process device 116T') can serve as the circuit output terminal. In some embodiments, some of the front-end process device 116T (or the back-end process device 116T') are included in the amplifier Al. The filter 101 (e.g., a band-pass filter, a Fourier transform circuit, etc.) can be applied in the measurement circuit 116M (or 116M') for signal retrieval.

[0053] In some embodiments, the filter 101 is implemented as a tunable band-pass filter that allows signals between a selected frequency range to pass through and blocks other signals with other frequency ranges. The band-pass filter can include a low-pass filter and a high-pass filter, where the high-pass filter passes high frequency signals and blocks low frequency signals, and the low-pass filter passes low frequency signals and blocks high frequency signals. In some embodiments, the capacitance C L belongs to the low-pass filter and the capacitance C H belongs to the high-pass filter, where Figure 2A or Figure 2B The back-end process device 116C marked in the above equation can serve as the capacitance (C L and C H ). In some embodiments, the capacitance (C L and C H ) is connected to the front-end process device 116T (and / or the back-end process device 116T'), where the front-end process device 116T (and / or the back-end process device 116T') is used to provide the resistance R S , where the subscript "S" can represent "stabilize". For example, the front-end process device 116T (and / or the back-end process device 116T') can include a stable resistance characteristic. In some embodiments, a transistor (not shown separately) included in the amplifier Al provides the resistance for the high-pass filter part. In some embodiments, the positive input terminal of the amplifier Al is coupled to the capacitance C H , and the negative input terminal of the amplifier Al is coupled to the capacitance CL. The filter 101 can be configured to transmit selected frequency signals and have some advantages, such as saving energy, reducing noise, distortion, and complexity, etc.

[0054] By configuring the filter 101 in the measurement circuit 116M (or 116M') for 3ω signal acquisition, the circuit (e.g. lock-in amplifier or similar) or external device for signal acquisition can be omitted from the measurement circuit 116M (or 116M'). The electro-thermal measurement circuit 116M (or 116M') including a ring oscillator for generating a sinusoidal wave and a filter 101 (or Fourier transform circuit) for acquiring the signal is simple, and the measurement circuit 116M (or 116M') can occupy a smaller area in the corresponding hierarchy, thereby saving circuit area. Since the existing circuit / device in the semiconductor structure (10A / 10B) can be configured to provide an input voltage signal, an external device (e.g. a current source) can be omitted. Because the measurement accuracy depends only on the voltage supply and the filter / transform circuit, the resistance of the thermal sensing device 116 can be relatively small (e.g. a few ohms). A relatively large resistance (e.g. 2 to 10 times the sensor resistance) can be used to stabilize the current and convert the voltage source (e.g. the voltage signal of the ring oscillator) into a current source, which can be part of the interconnect structure 115.

[0055] Figure 10A A schematic top view of a layer of an interconnect structure in which a thermal sensor is located is shown according to some embodiments and Figure 10B A schematic cross-sectional view of a portion of a thermal sensor in an interconnect structure is shown according to some embodiments. Reference is made to Figures 10A-10B and to Figure 9 and Figures 2A-2B The metallization pattern 116S of the thermal sensing device 116, which acts as a heater and at the same time as a sensing element, can be embedded in a dielectric layer 1151 of the interconnect structure 115. The interconnect structure 115 comprises a plurality of conductive metal layers (i.e. M1,..., Mn), where n is an integer greater than or equal to 1. In some embodiments, the metallization pattern 116S is disposed next to the conductive metal layer Mn, where n is an integer greater than or equal to 4. Alternatively, n is an integer greater than or equal to 1. The metallization pattern 116S can be in close proximity (e.g. 10HS as indicated in Figures 7-8 ) to the hot spot 10HS. The hot spot 10HS can be an area where a high power device is located or an area / path with a thermal bottleneck. By placing the metallization pattern 116S in the vicinity of the specific / temperature sensitive area, the temperature data can be better correlated to the actual temperature at the hot spot 10HS. It is to be understood that the number and configuration of the metallization patterns 116S shown in the top view of Figure 10A is shown for illustration purposes and the metallization patterns 116S can have a different arrangement and number than shown.

[0056] Continuing with Figures 10A-10BThe metallization pattern 116S and the conductive sub-layers (Mn+1, Mn and Mn-1) can be disposed at substantially the same level. As used herein, when components are described as being at "substantially the same level," the components are formed at substantially the same height in the same layer. For example, components at substantially the same level are formed from the same / similar materials and the same / similar process steps. In some embodiments, the metallization pattern 116S includes a first portion 1161v for voltage measurement. In some embodiments, the metallization pattern 116S includes a second portion 1161c for connecting an oscillating current at a frequency of 1ω, which can heat the metallization pattern at a characteristic frequency of 2ω. In some embodiments, the first portion 1161v and the second portion 1161c are vias and can be disposed at opposite sides (e.g., upper and lower sides) of the metal lines of the metallization pattern 116S. It should be understood that Figure 10B The number and configuration of the first and second portions in FIG. 1 16S are shown for illustrative purposes and the first and second portions can have different arrangements and numbers than shown.

[0057] The foregoing features for implementing the thermal sensing device 116 are shown for illustrative purposes. The thermal sensing device 116 can have features that vary according to its temperature, but various types of thermal sensing devices 116 are within the scope contemplated by the present disclosure. The thermal sensing device 116 can be partially or completely embedded in the interconnect structure 115. The thermal sensing device 116 can be arranged in a manner that yields a temperature profile of the resulting semiconductor structure (10A / 10B). For example, the metallization pattern 116S of the thermal sensing device 116 can be disposed at different levels of the interconnect structure 115 to monitor temperatures at different depths in the corresponding tiers, thereby establishing a heat profile of the semiconductor structure (10A / 10B).

[0058] Embodiments can have one or a combination of the following features and / or advantages. The thermal sensing device 116 of embodiments is embedded in one or more tiers of a semiconductor structure (10A / 10B) to monitor the temperature of hot spots 10HS on the chip in real time. The thermal sensing device 116 disposed in the corresponding one or more tiers can be configured to establish a heat map of the entire semiconductor structure (10A / 10B) so that the temperature of the integrated circuit can be controlled. The measurement circuit (116M / 116M') applied to the thermal sensing device 116 can be integrated into the semiconductor circuit fabricated by the front-end-of-line, middle-of-line, back-end-of-line, or any combination thereof. For example, the thermal sensing device 116 formed from materials compatible with the front-end-of-line and / or back-end-of-line enables the transient electro-thermal sensing system to be more easily integrated into the resulting structure. Transient electro-thermal measurements provide better measurement circuit accuracy because resistance measurements are more accurate. The resistance of the thermal sensing device 116 can be relatively small because the measurement accuracy depends on the voltage source and filter / conversion circuitry. The low resistance of the thermal sensing device 116 can provide efficient operation and reduce energy consumption. By configuring the measurement circuitry partially (or entirely) in the interconnect structure 115, the footprint of the circuitry / device can be saved. The feedback circuitry connected to the thermal sensing device 116 can be configured to dynamically control the temperature of the entire semiconductor structure (10A / 10B). For example, adjustments are made to the circuit operation in response to the measured temperature to reduce or avoid overheating conditions, thereby enhancing the performance and reliability of the semiconductor structure (10A / 10B).

[0059] According to some embodiments, a semiconductor structure includes a first interconnect structure disposed over a first semiconductor substrate and a thermal sensing device. The thermal sensing device includes a first transistor, a second transistor, a first capacitor coupled to the first transistor, a second capacitor coupled to the second transistor, and a metallization pattern embedded in the first interconnect structure and functioning as a resistive heater. At least one of the first and second transistors is selected from a group of transistors embedded in the first interconnect structure.

[0060] In some embodiments, the first transistor and the second transistor are embedded in the first interconnect structure. In some embodiments, the first transistor is disposed on the first semiconductor substrate and under the first interconnect structure, and the second transistor is disposed on the first transistor and embedded in the first interconnect structure. In some embodiments, the semiconductor structure further includes a first bonding layer disposed on a topmost layer of the first interconnect structure, wherein at least a portion of the metallization pattern is embedded in the topmost layer of the first interconnect structure. In some embodiments, the semiconductor structure further includes a second interconnect structure disposed on a second semiconductor substrate, wherein the first bonding layer is bonded to the second semiconductor substrate. In some embodiments, the semiconductor structure further includes a via through the second interconnect structure, the second semiconductor substrate, and the first bonding layer to land on a conductive feature of the first interconnect structure. In some embodiments, the semiconductor structure further includes a second interconnect structure disposed on a second semiconductor substrate and a second bonding layer disposed under the second semiconductor substrate and bonded to the first bonding layer. In some embodiments, the first bonding layer includes a first dielectric layer and a first bonding feature, the second bonding layer includes a second dielectric layer bonded to the first dielectric layer and a second bonding feature bonded to the first bonding feature, and bonding surfaces of the first dielectric layer and the first bonding feature are substantially flush. In some embodiments, the semiconductor structure further includes a via through the first interconnect structure and the first semiconductor substrate to land on the first bonding layer. In some embodiments, the metallization pattern is distributed at different levels of the first interconnect structure. In some embodiments, the first transistor and the first capacitor are included in a low-pass filter, and the second transistor and the second capacitor are included in a high-pass filter.

[0061] According to some embodiments, a semiconductor structure includes an interconnect structure on a semiconductor substrate and a thermal sensing device. The thermal sensing device includes a resistive member embedded in the interconnect structure and a filter member coupled to the resistive member. The resistive member acts as a heater, the filter member allows signals between selected frequency ranges to pass, and the filter member includes a transistor and a capacitor connected to the transistor.

[0062] In some embodiments, the transistor of the filter component is embedded in the interconnect structure. In some embodiments, the semiconductor structure further includes a bond layer disposed on a topmost layer of the interconnect structure, wherein at least a portion of the resistive component is embedded in the topmost layer of the interconnect structure. In some embodiments, the bond layer includes a dielectric layer and a bond feature, and a bond surface of the dielectric layer and a bond surface of the bond feature are substantially planar. In some embodiments, the semiconductor structure further includes a via through the interconnect structure and the semiconductor substrate.

[0063] According to some embodiments, a method of manufacturing a semiconductor structure includes forming a device on a semiconductor substrate by a front-end-of-line (FEOL) process, forming an interconnect structure over the semiconductor substrate by a back-end-of-line (BEOL) process, and forming a thermal sensing device, wherein the thermal sensing device is formed from a material compatible with at least one selected from a group of the FEOL process and the BEOL process.

[0064] In some embodiments, forming the thermal sensing device includes forming a transistor in the interconnect structure and forming a capacitor in the interconnect structure to be coupled to the transistor by the BEOL process. In some embodiments, forming the thermal sensing device includes forming a transistor by the FEOL process when forming the device and forming a metallization pattern in the interconnect structure as a resistive heater. In some embodiments, the method of manufacturing further includes thinning the semiconductor substrate and forming a via through the interconnect structure and the semiconductor substrate after thinning the semiconductor substrate.

[0065] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the present application; even though the above-described embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the above-described embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that, include: Interconnect structures are disposed on a semiconductor substrate; as well as Thermal sensing device, including: The first transistor and the second transistor are embedded in the interconnect structure from at least one of the group selected from the first transistor and the second transistor; A first capacitor and a second capacitor are respectively coupled to the first transistor and the second transistor; and Metallized patterns are embedded in the interconnect structure and serve as a resistance heater.

2. The semiconductor structure according to claim 1, characterized in that, The first transistor and the second transistor are embedded in the interconnect structure.

3. The semiconductor structure according to claim 1, characterized in that, The first transistor is disposed on the semiconductor substrate and below the interconnect structure, and the second transistor is disposed on the first transistor and embedded in the interconnect structure.

4. The semiconductor structure according to claim 1, characterized in that, Also includes: A bonding layer is disposed on the top layer of the interconnect structure, wherein at least a portion of the metallized pattern is embedded in the top layer of the interconnect structure.

5. The semiconductor structure according to claim 1, characterized in that, The metallized pattern is distributed at different levels of the interconnect structure.

6. The semiconductor structure according to claim 1, characterized in that, The first transistor and the first capacitor are included in a low-pass filter, and the second transistor and the second capacitor are included in a high-pass filter.

7. A semiconductor structure, characterized in that, include: Interconnect structures are located on a semiconductor substrate; as well as Thermal sensing device, including: A resistive component is embedded in the internal interconnect structure and serves as a heater; as well as A filtering component, coupled to the resistive component and allowing signals to pass through within a selected frequency range, includes a transistor and a capacitor connected to the transistor.

8. The semiconductor structure according to claim 7, characterized in that, The transistors of the filtering component are embedded in the interconnect structure.

9. The semiconductor structure according to claim 7, characterized in that, Also includes: A bonding layer is disposed on the top layer of the interconnect structure, wherein at least a portion of the resistive member is embedded in the top layer of the interconnect structure.

10. The semiconductor structure according to claim 7, characterized in that, Also includes: A perforation is made that extends through the interconnect structure and the semiconductor substrate.

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