Current peak suppression circuit under hot plug of motor

Abstract

The utility model discloses a current peak suppression circuit under motor hot plug, comprising a motor M. One side of the motor M is connected in series with a driving power supply 24V. An RCD absorption circuit is connected in series between the motor M and the driving power supply 24V, the RCD absorption circuit comprises a first resistor R1, one side of the first resistor R1 is connected in parallel with a first diode D1 and a first capacitor C1, and one side of the second diode D2 and one side of the third diode D3 are connected in parallel with second capacitors C2, C3 and C4 and third capacitors C5, C6 and C7. And the outer side of the motor M is connected in parallel with a parasitic inductance detection circuit. According to the current peak suppression circuit under the hot plug of the motor disclosed by the utility model, the discharge process of the absorption capacitor at the moment of hot plug is omitted, and the operation loss of the hot plug suppression circuit is reduced; the adverse effect of the voltage peak generated by the stray inductance on the hot plug suppression circuit is reduced, and the safety and reliability of the hot plug suppression circuit for protecting the motor operation system are improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of hot plug suppression circuit, specifically relates to a current peak suppression circuit under motor hot plug. BACKGROUND

[0002] Hot plug refers to the process of hot plugging hard disk, power module, board card, motor and other loads under the condition of not closing the system power supply, and in the hot plug moment, the load is in the state of nearly straight through, and the current is in the state of nearly short circuit in the hot plug moment, and the current generated in the hot plug moment can cause damage to hard disk, power module, board card, motor and other loads.

[0003] Especially in the motor operation system, the hot plug operation of the motor in the maintenance, test, replacement process can easily lead to the damage of the whole motor operation system, in order to ensure the safe and reliable operation of the motor operation system, the corresponding hot plug suppression circuit needs to be configured to the motor operation system, so as to protect the motor operation system.

[0004] At present, the common hot plug suppression circuit mainly adopts the conventional parallel type charge-discharge RCD absorption circuit to absorb the instantaneous current generated by the hot plug of the motor operation system, so as to protect the hot plug of the motor operation system, this method can play the role of hot plug suppression protection of the motor operation system, but the hot plug suppression circuit is easily affected by the voltage peak caused by the stray inductance of the motor itself in the running process, not only the protection reliability and safety of the hot plug suppression circuit are poor, but also the absorption capacitor absorbs and releases the current generated in the hot plug moment, so that the loss of the hot plug suppression circuit is large.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a current peak suppression circuit under motor hot plug.

[0006] The information disclosed in this background section is only intended to increase the understanding of the general background of the present utility model, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. CONTENT OF THE UTILITY MODEL

[0007] The utility model aims at providing a current peak suppression circuit under motor hot plug, which can reduce the loss of the hot plug suppression circuit and improve the operation reliability and safety of the hot plug suppression circuit.

[0008] In order to achieve the above purpose, a current peak suppression circuit under motor hot plug is provided in a specific embodiment of the utility model, which comprises a motor M, and a driving power supply 24V is connected in series on one side of the motor M.

[0009] The motor M is connected in series between the driving power supply 24V, and an RCD absorption circuit is arranged between the motor M and the driving power supply 24V, the RCD absorption circuit comprises a first resistor R1, the first resistor R1 is connected in parallel between the driving power supply 24V and the motor M, one side of the first resistor R1 is connected in parallel with a first diode D1 and a first capacitor C1, one side of the first capacitor C1 is connected in parallel with a second diode D2, the second diode D2 and a third diode D3 are connected in series, and one side of the second diode D2 and the third diode D3 are connected in parallel with a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third capacitor C5, a fourth capacitor C6 and a fifth capacitor C7.

[0010] The motor M is connected in series between the driving power supply 24V, and an RCD absorption circuit is arranged between the motor M and the driving power supply 24V, the RCD absorption circuit comprises a first resistor R1, the first resistor R1 is connected in parallel between the driving power supply 24V and the motor M, one side of the first resistor R1 is connected in parallel with a first diode D1 and a first capacitor C1, one side of the first capacitor C1 is connected in parallel with a second diode D2, the second diode D2 and a third diode D3 are connected in series, and one side of the second diode D2 and the third diode D3 are connected in parallel with a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third capacitor C5, a fourth capacitor C6 and a fifth capacitor C7.

[0011] The inductance sampling circuit generates corresponding frequencies through a U1 timer, and MCU counts and times these frequencies by utilizing the capacitor three-point sine wave oscillation principle to confirm the line parasitic inductance.

[0012] In one or more embodiments of the utility model, the inductance sampling circuit uses a first chip U1 timer to form a monostable with peripheral circuits and generate a pulse waveform.

[0013] In one or more embodiments of the utility model, the inductance sampling circuit performs extreme sampling on a first inductor L1, the first inductor L1 is a to-be-measured inductor, and the oscillation frequency of the output of the first inductor L1 is

[0014] Wherein, the capacitance value of C is the series capacitance value of the 11th capacitor C11 and the 17th capacitor C17, and the calculation formula is:

[0015]

[0016] The calculation formula of L is: L = 1 / 4π 2 fc.

[0017] In one or more embodiments of the utility model, a peak current detection circuit is connected in series between the motor M and the driving power supply 24V, the peak current detection circuit comprises an operational amplifier circuit composed of a fifth resistor R5 and an operational amplifier, and the operational amplifier circuit composed of the fifth resistor R5 and the operational amplifier is connected in series between the motor M and the driving power supply 24V.

[0018] In one or more embodiments of the utility model, the driving power supply 24V, the fifth resistor R5 and the negative pole contact of the operational amplifier detection circuit are connected, and the driving power supply V1, the fifth resistor R5 and the negative pole contact of the operational amplifier detection circuit are grounded.

[0019] In one or more embodiments of the utility model, the motor M and drive power 24V have fifth resistance R5 in series.

[0020] In one or more embodiments of the utility model, the drive power 24V and motor M have second diode D2, third diode D3, second capacitor C2, C3, C4 and third capacitor C5, C6, C7 in parallel.

[0021] In one or more embodiments of the utility model, the second diode D2 and third diode D3 have first MOSFET Q1 in parallel, and the second diode and third diode are in series.

[0022] In one or more embodiments of the utility model, the second diode and third diode have second capacitor C2, C3, C4 and third capacitor C5, C6, C7 in parallel, and the second capacitor C2, C3, C4 and third capacitor C5, C6, C7 are in series.

[0023] In one or more embodiments of the utility model, the second diode and second capacitor C2, C3, C4 have dial switch in series.

[0024] In one or more embodiments of the utility model, the third diode and third capacitor C5, C6, C7 have dial switch in series.

[0025] In one or more embodiments of the utility model, the positive contact of the current acquisition circuit has fifth resistance R5 in series, and the fifth resistance R5 is connected with the motor M.

[0026] In one or more embodiments of the utility model, the fifth resistance R5 is in series with the motor M, and the fifth resistance R5 is grounded.

[0027] Compared with the prior art, the utility model discloses a kind of motor hot plug current peak suppression circuit, eliminates the discharge process of absorption capacitor at hot plug moment, reduces the operating loss of hot plug suppression circuit;

[0028] The adverse effects of voltage peak generated by stray inductance on hot plug suppression circuit are reduced, and the safety and reliability of hot plug suppression circuit for protecting motor operating system are improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to make the technical personnel of the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work should belong to the protection scope of the present application.

[0030] Figure 1 It is a circuit schematic diagram of a current peak suppression circuit under motor hot plug in an embodiment of the present application.

[0031] Figure 2 It is a schematic diagram of improved front voltage peak in an embodiment of the present application.

[0032] Figure 3 It is a schematic diagram of improved rear voltage peak in an embodiment of the present application.

[0033] Figure 4 It is a circuit schematic diagram of simulating power supply hot plug state by using a switch tube in another embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the technical personnel of the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work should belong to the protection scope of the present application.

[0035] As shown in the figure, Figures 1 to 4 A current peak suppression circuit under motor hot plug in an embodiment of the present application comprises: a motor M, and a driving power supply 24V connected in series on one side of the motor M.

[0036] As shown in the figure, Figure 1 A RCD absorption circuit is connected in series between the motor M and the driving power supply 24V, and the RCD absorption circuit comprises a first resistor R1, and the first resistor R1 is connected in parallel between the driving power supply 24V and the motor M.

[0037] As shown in the figure, Figure 1 One side of the first resistor R1 is connected in parallel with a first diode D1 and a first capacitor C1, one side of the first capacitor C1 is connected in parallel with a second diode D2, the second diode D2 and a third diode D3 are connected in series, and one side of the second diode D2 and the third diode D3 are connected in parallel with a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third capacitor C5, C6, C7.

[0038] Specifically, the first resistor R1 is used to absorb the discharge of the capacitor, and meets the extreme case that the peak voltage of the capacitor is discharged under the rated current in the hot plug. At the same time, the absorption resistor meets the requirement that the discharge is completed within the minimum time of hot plug.

[0039] As shown in Figure 1 , the motor M and the driving power supply 24V are connected in series with a peak current detection circuit, and the peak current detection circuit includes an operational amplifier circuit composed of a fifth resistor R5 and an operational amplifier. The operational amplifier circuit composed of the fifth resistor R5 and the operational amplifier is connected in series between the motor M and the driving power supply 24V.

[0040] As shown in Figure 1 , the driving power supply 24V, the fifth resistor R5 and the negative electrode contact of the operational amplifier detection circuit are connected, and the driving power supply V1, the fifth resistor R5 and the negative electrode contact of the operational amplifier detection circuit are grounded.

[0041] As shown in Figure 1 , the fifth resistor R5 is connected in series between the motor M and the driving power supply 24V.

[0042] As shown in Figure 1 , the motor M is connected in parallel with a parasitic inductance detection circuit on the outside, and the parasitic inductance detection circuit includes a voltage detection circuit, an inductance sampling circuit and a detection chip. By detecting the parasitic inductance of the detection circuit, the second capacitor C2, C3, C4 and the third capacitor C5, C6, C7 are selected.

[0043] As shown in Figure 1 , the driving power supply 24V and the motor M are connected in parallel with the second diode D2, the third diode D3, the second capacitor C2, C3, C4 and the third capacitor C5, C6, C7 in turn.

[0044] As shown in Figure 1 , the first MOSFET Q1 is connected in parallel with the second diode D2 and the third diode D3, and the second diode and the third diode are connected in series.

[0045] Specifically, the first MOSFET Q1 is connected to the back end of the second diode D2 and the third diode D3.

[0046] As shown in Figure 1 , the second diode and the third diode are connected in parallel with the second capacitor C2, C3, C4 and the third capacitor C5, C6, C7, and the second capacitor C2, C3, C4 and the third capacitor C5, C6, C7 are connected in series.

[0047] Specifically, the second diode and the second capacitor C2, C3, C4 are connected in series with a dip switch.

[0048] Specifically, the third diode and the third capacitor C5, C6, C7 are connected in series with a dip switch.

[0049] As Figure 1 shown, the positive contact of the current collection circuit is connected in series with the fifth resistor R5, and the fifth resistor R5 is connected with the motor M.

[0050] As Figure 1 shown, the fifth resistor R5 is connected in series with the motor M, and the fifth resistor R5 is grounded.

[0051] Wherein, the inductance sampling circuit generates corresponding frequency through U1 timer, and MCU counts and times these frequencies by using the principle of three-point sine wave oscillation of capacitor, to confirm the line parasitic inductance.

[0052] Specifically, the inductance sampling circuit uses the first chip U1 timer to match the peripheral circuit, to form a monostable circuit, and generate pulse waveform.

[0053] Notably, the inductance sampling circuit performs extreme sampling on the first inductor L1, which is the inductance to be measured, and the oscillation frequency of the output of the first inductor L1 is

[0054] Wherein, the capacitance value of C is the series capacitance value of the 11th capacitor C11 and the 17th capacitor C17, and the calculation formula is:

[0055] The calculation formula of L is: L = 1 / 4π 2 fc.

[0056] Specifically, by charging the second capacitor C2 and the third capacitor C3, the Vgs of the MOSFET is increased, so that the MOSFET can be slowly turned on.

[0057] As Figures 2 to 3 shown, notably, by revealing the influence of stray inductance parameters on voltage spikes, it is proved that the larger the stray inductance parameters, the higher the voltage spikes generated in the hot plug moment, so that the voltage spikes in the hot plug process can be effectively reduced by changing the absorption capacitor.

[0058] Specifically, at the hot plug moment, the current flowing through the third inductor L3 will increase rapidly, generating a large di / dt, and under the action of the RCD absorption circuit, the third inductor L3 will charge the equivalent parasitic capacitor of the MOSFET, and at the same time, the first capacitor C1 can be charged.

[0059] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that it can be implemented in other concrete forms without departing from the spirit or the essential characteristics of the present application. Therefore, the embodiments should be considered as exemplary and non-limiting, the scope of the present application being defined by the claims appended hereto rather than by the above description, and all the changes which fall within the meaning and the scope of the equivalent elements of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0060] Furthermore, it should be understood that although the present specification describes exemplary embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that a person skilled in the art can understand.

Claims

1. A current spike suppression circuit under hot-plugging of a motor, characterized in that, include: Motor M, with a 24V drive power supply connected in series on one side of motor M; An RCD snubber circuit is connected in series between the motor M and the 24V drive power supply. The RCD snubber circuit includes a first resistor R1, which is connected in parallel between the 24V drive power supply and the motor M. A first diode D1 and a first capacitor C1 are connected in parallel on one side of the first resistor R1. A second diode D2 is connected in parallel on one side of the first capacitor C1. The second diode D2 and a third diode D3 are connected in series. A second capacitor C2, C3, and C4 and a third capacitor C5, C6, and C7 are connected in parallel on one side of each of the second diode D2 and the third diode D3. A parasitic inductance detection circuit is connected in parallel on the outside of the motor M. The parasitic inductance detection circuit includes a voltage detection circuit, an inductance sampling circuit, and a detection chip. By detecting the parasitic inductance of the circuit, the second capacitor C2, C3, C4 and the third capacitor C5, C6, C7 are selected. The inductor sampling circuit generates corresponding frequencies through the U1 timer. Utilizing the principle of three-point sine wave oscillation of the capacitor, the MCU counts and times these frequencies to confirm the parasitic inductance of the line.

2. The current spike suppression circuit under hot-plugging of a motor according to claim 1, characterized in that, The inductor sampling circuit uses the first chip U1 timer in conjunction with peripheral circuitry to form a monostable state and generate a pulse waveform.

3. The current spike suppression circuit under hot-plugging of a motor according to claim 1, characterized in that, The inductor sampling circuit performs extreme sampling on the first inductor L1, which is the inductor under test. The oscillation frequency of the output of the first inductor L1 is... Where C is the capacitance value of the 11th capacitor C11 and the 17th capacitor C17 connected in series, and the calculation formula is: The formula for calculating L is: L = 1 / 4π 2 fc.

4. The current spike suppression circuit under hot-plugging of a motor according to claim 1, characterized in that, A peak current detection circuit is connected in series between the motor M and the 24V drive power supply. The peak current detection circuit includes an operational amplifier circuit composed of a fifth resistor R5 and an operational amplifier. The operational amplifier circuit composed of the fifth resistor R5 and the operational amplifier is connected in series between the motor M and the 24V drive power supply.

5. The current spike suppression circuit under hot-plugging of a motor according to claim 4, characterized in that, The 24V driving power supply and the fifth resistor R5 are connected to the negative contact of the operational amplifier detection circuit, and the driving power supply V1, the fifth resistor R5 and the negative contact of the operational amplifier detection circuit are grounded.

6. The current spike suppression circuit under hot-plugging of a motor according to claim 5, characterized in that, A fifth resistor R5 is connected in series between the motor M and the 24V drive power supply.

7. The current spike suppression circuit under hot-plugging of a motor according to claim 6, characterized in that, The 24V driving power supply is connected in parallel with the motor M via a second diode D2, a third diode D3, second capacitors C2, C3, and C4, and third capacitors C5, C6, and C7.

8. The current spike suppression circuit under hot-plugging of a motor according to claim 6, characterized in that, The second diode D2 and the third diode D3 are connected in parallel with the first MOSFET Q1, and the second diode and the third diode are connected in series.

9. The current spike suppression circuit under hot-plugging of a motor according to claim 1, characterized in that, Both the second diode and the third diode have second capacitors C2, C3, C4 and third capacitors C5, C6, C7 connected in parallel, and the second capacitors C2, C3, C4 and the third capacitors C5, C6, C7 are connected in series.

10. A current spike suppression circuit for motor hot-plugging according to claim 9, characterized in that, The second diode is connected in series with the second capacitors C2, C3, and C4 via a DIP switch.

11. The current spike suppression circuit under hot-plugging of a motor according to claim 9, characterized in that, The third diode is connected in series with the third capacitors C5, C6, and C7 via a DIP switch.

12. The current spike suppression circuit under hot-plugging of a motor according to claim 9, characterized in that, The positive contact of the current acquisition circuit is connected in series with a fifth resistor R5, which is connected to the motor M.

13. The current spike suppression circuit under hot-plugging of a motor according to claim 12, characterized in that, The fifth resistor R5 is connected in series with the motor M, and the fifth resistor R5 is grounded.

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