Display panel

Abstract

There is provided a display panel including: a base layer; a pixel defining film over the base layer and defining a light emitting opening; a partition wall over the pixel defining film, defining a partition wall opening corresponding to the light emitting opening, and having a first partition wall layer including a first conductive material, a partition wall insulating layer over the first partition wall layer and including an insulating material, and a second partition wall layer over the partition wall insulating layer and including a second conductive material; and a light emitting element in the light emitting opening and the partition wall opening, and including an anode, a light emitting pattern, and a cathode, the cathode contacting the partition wall.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2023-0170244, filed on November 30, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display panel with improved display quality and methods for displaying the same. Background Technology

[0004] Display devices that provide images to users (such as televisions, monitors, smartphones, and tablet computers) include display panels that display images. Various display panels, such as liquid crystal display panels, organic light-emitting diode display panels, electrowetting display panels, and electrophoretic display panels, have been developed as display panels.

[0005] An organic light-emitting display panel may include an anode, a cathode, and a light-emitting pattern. The light-emitting pattern may be separate for each light-emitting area, and the cathode may provide a common voltage to each light-emitting area. Utility Model Content

[0006] This disclosure provides a display panel with improved display quality and a method for manufacturing the display panel, which provides light-emitting elements without using a metal mask.

[0007] One or more embodiments of this disclosure provide a display panel, the display panel comprising: a base layer; a pixel defining film above the base layer and defining a light-emitting opening; a partition wall above the pixel defining film, defining a partition wall opening corresponding to the light-emitting opening, and having a first partition wall layer including a first conductive material, a partition wall insulating layer above the first partition wall layer and including an insulating material, and a second partition wall layer above the partition wall insulating layer and including a second conductive material; and a light-emitting element in the light-emitting opening and the partition wall opening, and including an anode, a light-emitting pattern, and a cathode, the cathode contacting the partition wall.

[0008] The partition wall opening may include: a first region defined by an inner surface of a first partition wall layer; and a second region defined by an inner surface of a partition wall insulating layer and an inner surface of a second partition wall layer, wherein the width of the first region in one direction is greater than the width of the second region in one direction.

[0009] The display panel may also include a lower inorganic encapsulation pattern that covers the light-emitting elements and is spaced apart from the top surface of the partition wall.

[0010] A separation area can be defined between the lower inorganic encapsulation pattern and the separation wall, wherein a thickness of the separation area is substantially equal to a thickness of the cathode.

[0011] The display panel can further include a cathode dummy layer in a portion of the separation area and including a same material as the cathode.

[0012] The separation area can be empty.

[0013] The thickness of the separation area can be about 200 angstroms or less.

[0014] The display panel can further include a capping pattern over the cathode, wherein the thickness of the separation area corresponds to a sum of a thickness of the cathode and a thickness of the capping pattern.

[0015] The second separation wall layer can include at least one of titanium (Ti), molybdenum (Mo), and tungsten (W).

[0016] The second separation wall layer can include a material having a melting point of about 970 degrees or more.

[0017] In one or more embodiments of the disclosure, a method of manufacturing a display panel includes: providing an initial display panel including a base layer and a pixel definition film over the base layer; forming an initial separation wall on the pixel definition film, the initial separation wall having a first initial separation wall layer including a first conductive material, an initial separation wall insulating layer including an insulating material, and a second initial separation wall layer including a second conductive material; forming a separation wall defining a separation wall opening from the initial separation wall; etching the pixel definition film to form a light emission opening overlapping the separation wall opening; forming a light emission pattern in the light emission opening and a light emission pattern dummy layer on the separation wall including a same material as the light emission pattern; and applying heat to the separation wall to remove the light emission pattern dummy layer.

[0018] The separation wall can include: a first separation wall layer including a first conductive material; a separation wall insulating layer over the first separation wall layer and including an insulating material; and a second separation wall layer over the separation wall insulating layer and including a second conductive material.

[0019] Forming the separation wall defining the separation wall opening from the initial separation wall can include: first etching the first initial separation wall layer, the initial separation wall insulating layer, and the second initial separation wall layer; and second etching the first initial separation wall layer.

[0020] The separation wall opening can include: a first area defined by an inner side surface of the first separation wall layer; and a second area defined by an inner side surface of the separation wall insulating layer and an inner side surface of the second separation wall layer, wherein a width in one direction of the first area is greater than a width in one direction of the second area.​

[0021] Applying heat to remove the light emitting pattern dummy layer can include applying a voltage to the second separation wall layer to cause Joule heating.

[0022] The method can further include forming a cathode in the light emitting opening and the separation wall opening; and forming a cathode dummy layer on the separation wall including a same material as the cathode.

[0023] The method can further include forming a lower inorganic encapsulation pattern on the cathode, wherein the cathode dummy layer is between the separation wall and the lower inorganic encapsulation pattern.

[0024] The method can further include removing at least a portion of the cathode dummy layer.

[0025] The method can further include forming a capping pattern in the separation wall opening; and forming a capping pattern dummy layer on the separation wall including a same material as the capping pattern.

[0026] Forming the initial separation wall can include depositing a second initial separation wall layer including a material having a property of a melting point of about 970 degrees or more. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the drawings:

[0028] FIG. 1A is a perspective view of a display apparatus according to one or more embodiments of the present disclosure;

[0029] FIG. 1B is an exploded perspective view of a display apparatus according to one or more embodiments of the present disclosure;

[0030] FIG. 2 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0031] FIG. 3 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] FIG. 4 is an enlarged plan view of a portion of a display area of a display panel according to one or more embodiments of the present disclosure;

[0033] FIG. 5A is a cross-sectional view taken along line I-I' of FIG. 3 ;

[0034] FIG. 5B is a cross-sectional view taken along line I-I' of FIG. 5AA magnified view of region AA' in the image;

[0035] FIG. 6 It is along FIG. 4 A sectional view taken from line II-II' in the middle;

[0036] FIG. 7A through FIG. 7L These are cross-sectional views illustrating some of the operations of a method for manufacturing a display panel according to one or more embodiments of the present disclosure; and

[0037] FIG. 8 It is along FIG. 3 The sectional view taken by line I-I' in the middle. Detailed Implementation

[0038] Some aspects of this disclosure and methods of implementing it can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for those skilled in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, designations, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0039] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments described herein. The use of "may," "may," or "may not" in describing embodiments corresponds to one or more embodiments of this disclosure.

[0040] In light of the overall content of this disclosure, those skilled in the art will understand that this disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of this disclosure, each of the features of the embodiments of this disclosure may be combined with each other in part or in whole, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented in conjunction with each other, unless otherwise stated or implied.

[0041] In the drawings, the relative dimensions of elements, layers, and regions shown in the figures can be exaggerated for clarity and / or descriptive purposes. In other words, since the dimensions and the thicknesses of the elements in the drawings are arbitrarily shown for ease of description, the present disclosure is not limited thereto. Also, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of adjacent regions. As such, unless specifically stated otherwise, the presence of cross-hatching or shading in a drawing generally represents a boundary of an adjacent region. In addition, the use of “about” or “approximately” in connection with a reference to a specific quantity, measurement, or other representation of a value is intended to account for variations associated with measurement uncertainty and inherent inaccuracies in measurements that are unavoidable in a manufacturing setting.

[0042] Various implementations are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures of implementations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the particular structural and functional configurations of the implementations disclosed herein are not to be interpreted as limiting but are merely illustrative of the implementations consistent with the present disclosure. Thus, the implementations disclosed herein are not to be interpreted as being limited to the illustrated shapes of elements, layers and regions, but are to include deviations in shapes that result, for example, from manufacturing.

[0043] For example, an implant region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurs.

[0044] Spatially relative terms, such as “under”, “below”, “lower”, “side”, “lower side”, “bottom”, “bottom side”, “on”, “higher”, “upper”, “top”, “top side” (e.g., as in “top side wall”), and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being “on” a second part, this means that the first part is disposed on the upper side or lower side of the second part, without being limited to the upper side of the second part based on a gravitational direction.

[0045] Furthermore, the phrase "in plan view" means when viewing the subject portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic section taken through a vertical cut of the subject portion from the side. The term "overlap" or "overlapped" means that a first object can be above or below a second object, or to the side of the second object, and vice versa. Additionally, the term "overlap" can include stacking, facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art. The expression "not overlap" can include the meaning of "spaced apart from each other" or "offset from each other" or "separated from each other" as well as any other suitable equivalent as will be appreciated and understood by one of ordinary skill in the art. The terms "face" and "facing" can mean that a first object can be directly opposite or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although still facing each other.

[0046] It will be understood that when an element, layer, region or component is referred to as being "on" or "connected to" or "coupled to" or "connected or coupled (operatively or communicatively) to" another element, layer, region or component, it can be directly on, connected to, or coupled to the other element, layer, region or component, or it can be indirectly on, connected to, or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components can exist. In addition, it can collectively mean directly or indirectly coupled or connected and integrally or non-integrally coupled or connected. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region or component, or one or more intervening layers, regions or components can exist. The one or more intervening components can include switches, resistors, capacitors, etc. In describing implementations, expressions of "connection" indicate electrical connection unless explicitly described as direct connection, and "direct connection / directly coupled" or "directly on" refer to one component directly connected or coupled to another component, or directly on another component, without intervening components.

[0047] Also, in this Specification, when a portion of a layer, film, region, plate, etc. is formed on another portion, the direction of formation is not limited to an upward direction, but includes formation of the portion on a side surface or in a downward direction. Conversely, when a portion of a layer, film, region, plate, etc. is formed "under" another portion, this includes not only the case where the portion is "directly under" the other portion, but also the case where there is yet another portion between the portion and the other portion. At the same time, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to" and "directly adjacent to," can be interpreted similarly. It will be understood that, when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements or layers can also be present.

[0048] For purposes of this disclosure, expressions such as "at least one of... " or "one or more of... " when preceding a list of two or more items, modify the entire list of items and do not modify the individual items of the list. For example, "at least one of X, Y, and Z" and "one or more of a group consisting of X, Y, and Z" can be interpreted as X alone, Y alone, Z alone, two or more of X, Y, and Z in any combination (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation of the above examples. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" means "and / or" and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of...," "one or more of...," "a plurality of...," "one of...," and other similar phrases preceding a list of two or more items, modify the entire list of items and do not modify the individual items of the list. When the statement "C to D" is used, it means C or greater and D or less, unless otherwise stated.

[0049] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“a first component,”“a first region,”“a first layer,” or“a first section” described below could be termed a“second element,”“a second component,”“a second region,”“a second layer,” or“a second section,” without departing from the spirit and scope of the present disclosure. An element described as“first” need not necessarily be“primary” or“important” and can be“secondary” or“insignificant” in use. The terms“first,”“second,” etc. can also be used herein to distinguish different categories or groups of elements. For the sake of simplicity, the terms“first,”“second,” etc. can be used herein to designate the“first category (or first group)” and the“second category (or second group),” respectively, as recited in the claims.

[0050] In examples, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0051] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“has,”“having,”“includes” and“including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0053] As used herein, the terms "substantially," "about," "approximately," and the like are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of +5% / -5% of the recited value. In view of the discussion above, "about" or "approximately," as used herein, includes the recited value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of "may" when describing embodiments of the present disclosure means that one or more embodiments of the present disclosure "can" or "might," but not necessarily, include the referenced feature.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] FIG. 1A is a perspective view of a display apparatus DD according to one or more embodiments of the present disclosure. FIG. 1B is an exploded perspective view of a display apparatus DD according to one or more embodiments of the present disclosure.

[0056] In one or more embodiments, the display apparatus DD can be a large electronic apparatus such as a television, a monitor, or an outdoor billboard. Also, the display apparatus DD can be a small or medium electronic apparatus such as a personal computer, a notebook computer, a personal digital assistant, a vehicle navigation unit, a game machine, a smart phone, a tablet computer, and a camera. However, the above-described apparatuses are examples, and the display apparatus DD can also be used as another display apparatus unless it deviates from the present disclosure. FIG. 1A and FIG. 1B A smart phone is illustrated as an example of the display apparatus DD.

[0057] Referring to FIG. 1A and FIG. 1B The display apparatus DD can display an image IM on a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM can include not only a dynamic image but also a static image. FIG. 1AA clock window and an application icon are shown as examples of the image IM. A display surface FS on which the image IM is displayed can correspond to a front surface of the display device DD.

[0058] A front surface (or top surface) and a rear surface (or bottom surface) of each member are defined based on a direction in which the image IM is displayed. The front surface and the rear surface can be opposite to each other in a third direction DR3, and a normal direction of each of the front surface and the rear surface can be parallel to the third direction DR3. Meanwhile, directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts, and can be changed to other directions. The term "on a plane" used herein can mean a state when viewed in the third direction DR3.

[0059] The display device DD can include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU can be coupled to each other to constitute an outer appearance of the display device DD.

[0060] The window WP can include an optically transparent insulating material. For example, the window WP can include glass or plastic. A front surface of the window WP can define a display surface FS of the display device DD. The display surface FS can include a transmissive area TA and a bezel area BZA. The transmissive area TA can be an optically transparent area. For example, the transmissive area TA can have a visible light transmittance of about 90% or more.

[0061] The bezel area BZA can be an area having a relatively low light transmittance compared to the transmissive area TA. The bezel area BZA can define a shape of the transmissive area TA. The bezel area BZA can be adjacent to the transmissive area TA and surround the transmissive area TA. However, this is shown as an example, and the bezel area BZA of the window WP can be omitted. The window WP can include at least one functional layer of an anti-fingerprint layer, a hard coat layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0062] The display module DM can be located below the window WP. The display module DM can be a component that substantially generates the image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and is visible to the outside of a user through the transmissive area TA.

[0063] The display module DM can include a display area DA and a non-display area NDA. The display area DA can be an area that is activated in response to an electrical signal. The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an area covered by the bezel area BZA and can not be visible from the outside.

[0064] The housing HAU can be connected to the window WP. The housing HAU can be coupled to the window WP to provide an internal space (e.g., a predetermined internal space). The display module DM can be accommodated in the internal space.

[0065] The housing HAU can include a material having relatively high rigidity. For example, the housing HAU can include a plurality of frames and / or plates, each of which includes glass, plastic, or metal, or is made of a combination thereof. The housing HAU can stably protect components of the display device DD accommodated in the internal space from external impact.

[0066] FIG. 2 is a cross-sectional view of a display module DM according to one or more embodiments of the disclosure.

[0067] Referring to FIG. 2 , the display module DM can include a display panel DP and an input sensor INS. In one or more embodiments, the display device DD (see FIG. 1A ) according to one or more embodiments of the disclosure can further include a protective member located on a bottom surface of the display panel DP, or an anti-reflection member and / or a window member located on a top surface of the input sensor INS.

[0068] The display panel DP can be a light-emitting display panel. However, this is an example, and the display panel DP is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. A light-emitting layer in the organic light-emitting display panel can include an organic light-emitting material. A light-emitting layer in the inorganic light-emitting display panel can include a quantum dot, a quantum rod, or a micro LED. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0069] The display panel DP can include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE located on the base layer BL (as used herein, "located on" can mean "above"). The input sensor INS can be directly located on the thin film encapsulation layer TFE. In the disclosure, "component A is directly located on component B" means that an adhesive layer is not located between component A and component B.

[0070] The base layer BL can include at least one plastic film. The base layer BL can be a flexible substrate, and can include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc. The same / similar display area DA and non-display area NDA as described with reference to FIG. 1B The display area DA and the non-display area NDA can be defined in the base layer BL.

[0071] The circuit element layer DP-CL can include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, a driving circuit of a pixel, and the like.

[0072] The display element layer DP-OLED can include a partition wall and a light emitting element. The light emitting element can include an anode, an intermediate layer, and a cathode.

[0073] The thin film encapsulation layer TFE can be a plurality of thin films. Some of the thin films can improve optical efficiency, and some of the thin films can protect the organic light emitting diode.

[0074] The input sensor INS obtains coordinate information of an external input. The input sensor INS can have a multi-layer structure. The input sensor INS can include a conductive layer having a single layer or a multi-layer structure. In addition, the input sensor INS can include an insulating layer having a single layer or a multi-layer structure. The input sensor INS can detect an external input by using a capacitive method. However, this is an example, and one or more embodiments of the disclosure are not limited thereto. For example, in one or more embodiments, the input sensor INS can detect an external input by using an electromagnetic induction method or a pressure detection method. In one or more other embodiments of the disclosure, the input sensor INS can be omitted.

[0075] FIG. 3 is a plan view of a display panel DP according to one or more embodiments of the disclosure.

[0076] Referring to FIG. 3 , a display area DA and a non-display area NDA surrounding the display area DA can be defined in the display panel DP. The display panel DP can include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP can include a driving circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA can be divided according to whether the pixels PX are positioned therein. The pixels PX can be located in the display area DA. The driving circuit GDC and the pad portion PLD can be located in the non-display area NDA.

[0077] The pixels PX can be arranged in a first direction DR1 and a second direction DR2. The pixels PX can include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0078] The signal lines SGL can include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL can be connected to a corresponding pixel among the pixels PX, and each of the data lines DL can be connected to a corresponding pixel among the pixels PX. The power lines PL can be electrically connected to the pixels PX. The control signal lines CSL can be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0079] The driving circuit GDC can include a gate driving circuit. The gate driving circuit can generate a gate signal, and can sequentially output the generated gate signal to the gate lines GL. The gate driving circuit can also output another control signal to the pixel driving circuit.

[0080] The pad portion PLD can be a portion to which the flexible circuit board is connected. The pad portion PLD can include pixel pads D-PD, and the pixel pads D-PD can be pads for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD can be connected to a corresponding signal line among the signal lines SGL. The pixel pads D-PD can be connected to corresponding pixels PX through the signal lines SGL, respectively. In addition, one of the pixel pads D-PD can be connected to the driving circuit GDC.

[0081] In addition, the pad portion PLD can further include an input pad. The input pad can be a pad for connecting the flexible circuit board to the input sensor INS (see FIG. 2 ). However, one or more embodiments of the present disclosure are not limited thereto, and the input pad can be located in the input sensor INS (see FIG. 2 ) to be connected to a circuit board separate from the pixel pads D-PD. Alternatively, the input sensor INS (see FIG. 2 ) can be omitted, and the pad portion PLD can not further include the input pad.

[0082] FIG. 4 is a plan view of a portion of the display area DA of the display panel DP (see FIG. 2 ) according to one or more embodiments of the present disclosure. FIG. 4 shows a plan of the display module DM (see FIG. 1B ) when viewed on the display surface IS (see FIG. 1B ) of the display module DM, and shows an arrangement of the light emitting areas PXA-R, PXA-G, and PXA-B.

[0083] Reference is made to FIG. 4The display area DA can include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and a peripheral area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can correspond to areas from which light provided from the light emitting element is emitted, respectively. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can be divided according to respective colors of light emitted toward the outside of the display module DM (see FIG. 1) in the first direction DR1. FIG. 2

[0084] The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can provide light having first to third colors different from each other, respectively. For example, the light having the first color can be red light, the light having the second color can be green light, and the light having the third color can be blue light. However, examples of the light having the first to third colors are not necessarily limited to the foregoing examples.

[0085] Each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can be defined as an area in which a top surface of an anode is exposed by a light emitting opening which will be described later. The peripheral area NPXA can set a boundary of each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B, and can reduce or prevent color mixing between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0086] Each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can be disposed in a plurality to have an arrangement shape (e.g., a predetermined arrangement shape), and can be repeatedly located in the display area DA. For example, the first light emitting area PXA-R and the third light emitting area PXA-B can be alternately arranged in the first direction DR1 to constitute a "first group". The second light emitting area PXA-G can be arranged in the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" can be disposed in a plurality, and the "first group" and the "second group" can be alternately arranged in the second direction DR2.

[0087] One second light emitting area PXA-G can be spaced apart from one first light emitting area PXA-R or one third light emitting area PXA-B in a fourth direction DR4. The fourth direction DR4 can be defined as a direction between the first direction DR1 and the second direction DR2.

[0088] FIG. 4 ​Examples of the arrangement shape or pattern of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B are shown. However, one or more embodiments of the present disclosure are not limited thereto, and the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can be arranged in various shapes. In one or more embodiments, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have shapes as shown in FIGS. 1A to 1C. FIG. 4 is a registered trademark of Samsung Display Co., Ltd. of Korea. Alternatively, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have a stripe arrangement shape or a diamond (e.g., Diamond ) arrangement shape (Diamond is a registered trademark of Samsung Display Co., Ltd. of Korea.

[0089] Each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have various shapes in a plane. For example, each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have a shape such as a polygonal shape, a circular shape, or an elliptical shape. As an example, FIG. 4 Examples in which the first light emitting area PXA-R and the third light emitting area PXA-B each have a square (or diamond) shape and the second light emitting area PXA-G has an octagonal shape in a plane are shown.

[0090] In a plane, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have the same shape, or at least some of them can have shapes different from each other. As an example, FIG. 4 Examples in which the first light emitting area PXA-R and the third light emitting area PXA-B have the same shape in a plane and the second light emitting area PXA-G has a shape different from the first light emitting area PXA-R and the third light emitting area PXA-B are shown.

[0091] ​​At least some of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have different surface areas in a plane. In one or more embodiments, the surface area of the first light emitting area PXA-R that emits red light can be greater than the surface area of the second light emitting area PXA-G that emits green light, and can be less than the surface area of the third light emitting area PXA-B that emits blue light. However, the size relationship between the surface areas of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B is not limited thereto according to the color of the emitted light, and can vary according to the design of the display module DM (see FIG. 2 ). However, one or more embodiments of the disclosure are not limited thereto, and in a plane, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can have the same surface area.

[0092] The shape, surface area, arrangement, etc. of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B of the display module DM (see FIG. 2 ) according to one or more embodiments of the disclosure can be variously designed according to the color of the emitted light or the size or configuration of the display module DM (see FIG. 2 ), and are not limited to one or more embodiments corresponding to FIG. 4 .

[0093] FIG. 5A is a cross-sectional view of the display panel DP taken along the line I-I' in FIG. 3 . FIG. 5B is a magnified view of the area AA' in FIG. 5A . In one or more embodiments described with reference to FIG. 5A and FIG. 5B , components referred to in FIG. 2 are referred to, and components denoted by the same reference numerals or signs are not described. FIG. 5A shows a magnified view of one light emitting area PXA in the display area DA (see FIG. 4 ), and FIG. 5A the light emitting area PXA in FIG. 4 may correspond to any one of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B in

[0094] With reference to FIG. 5A and FIG. 5B , the display panel DP can include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0095] The display panel DP can include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by a photolithography process and an etching process. The semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed by these processes.

[0096] The circuit element layer DP-CL can be located on the base layer BL. The circuit element layer DP-CL can include a buffer layer BFL, a transistor TR1, a signal transmission area SCL, first to fifth insulating layers 10, 20, 30, 40, and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0097] The buffer layer BFL can be located on the base layer BL. The buffer layer BFL can improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL can include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be alternately stacked.

[0098] The semiconductor pattern can be located on the buffer layer BFL. The semiconductor pattern can include polysilicon. However, one or more embodiments of the present disclosure are not limited thereto, and the semiconductor pattern can also include amorphous silicon or metal oxide. FIG. 5A Only a portion of the semiconductor pattern is shown as an example, and the semiconductor pattern can be further located in a plurality of light emitting areas PXA-R, PXA-G, and PXA-B (see FIG. 4 ). The semiconductor pattern can be arranged across the plurality of light emitting areas PXA-R, PXA-G, and PXA-B according to a corresponding rule. The semiconductor pattern can have different electrical properties according to whether it is doped. The semiconductor pattern can include a first region having a high doping concentration and a second region having a low doping concentration. The first region can be doped with an n-type dopant or a p-type dopant. The p-type transistor can include the first region doped with the p-type dopant.

[0099] The first region has a higher conductivity than the second region and substantially functions as an electrode or a signal line. The second region can substantially correspond to an active part (or a channel) of the transistor. In other words, one portion of the semiconductor pattern can be an active part of the transistor, another portion thereof can be a source or a drain of the transistor, and still another portion thereof can be a conductive region.

[0100] The source S, the active part A, and the drain D of the transistor TR1 can be provided from the semiconductor pattern. FIG. 5AA portion of the signal transmission area SCL provided from the semiconductor pattern is shown. In one or more embodiments, the signal transmission area SCL can be connected to the drain D of the transistor TR1 on a plane.

[0101] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can be located on the buffer layer BFL. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can be an inorganic layer or an organic layer.

[0102] The first insulating layer 10 can be located on the buffer layer BFL. The first insulating layer 10 can cover the source S, the active part A, and the drain D of the transistor TR1 and the signal transmission area SCL located on the buffer layer BFL. The gate G of the transistor TR1 can be located on the first insulating layer 10. The second insulating layer 20 can be located on the first insulating layer 10 to cover the gate G. The electrode EE can be located on the second insulating layer 20. The third insulating layer 30 can be located on the second insulating layer 20 to cover the electrode EE.

[0103] The first connection electrode CNE1 can be located on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal transmission area SCL by a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 can be located on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 can be an organic layer.

[0104] The second connection electrode CNE2 can be located on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 by a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 can be located on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 can be an organic layer.

[0105] The display element layer DP-OLED can be located on the circuit element layer DP-CL. The display element layer DP-OLED can include the light emitting element ED, the sacrificial pattern SP, the pixel definition film PDL, the partition wall PW, and the dummy layer DDL.

[0106] The light emitting element ED can include an anode AE (or a first electrode), a light emitting pattern EP, and 2 (or a second electrode). The light emitting element ED can be located in a light emitting opening OP-E and a partition wall opening OP-P, which will be described later.

[0107] The anode AE can be located on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 passing through and defined in the fifth insulating layer 50. Accordingly, the anode AE can be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and can be electrically connected to a corresponding circuit element. The anode AE can have a single-layer structure or a multi-layer structure. The anode AE can include a plurality of layers including ITO or Ag. For example, the anode AE can include a layer including ITO (hereinafter, referred to as a lower ITO layer), a layer located on the lower ITO layer and including Ag (hereinafter, referred to as an Ag layer), and a layer located on the Ag layer and including ITO (hereinafter, referred to as an upper ITO layer).

[0108] The sacrifice pattern SP can be located between the anode AE and the pixel definition film PDL. A sacrifice opening OP-S exposing a portion of a top surface of the anode AE can be defined (or included) in the sacrifice pattern SP. The sacrifice opening OP-S can overlap with a light emission opening OP-E which will be described later.

[0109] The pixel definition film PDL can be located on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emission opening OP-E can be defined (or included) in the pixel definition film PDL. The light emission opening OP-E can correspond to the anode AE, and the pixel definition film PDL can expose at least a portion of the anode AE through the light emission opening OP-E.

[0110] Further, in a cross-section, the light emission opening OP-E can correspond to the sacrifice opening OP-S of the sacrifice pattern SP. A top surface of the anode AE can be spaced apart from the pixel definition film PDL with the sacrifice pattern SP therebetween, and thus, the anode AE can be protected from damage in a process of forming the light emission opening OP-E.

[0111] In a plan view, a surface area of the light emission opening OP-E can be smaller than a surface area of the sacrifice opening OP-S. That is, an inner side surface of the pixel definition film PDL defining the light emission opening OP-E can be closer to a center of the anode AE (e.g., in a plan view) than an inner side surface of the sacrifice pattern SP defining the sacrifice opening OP-S. However, one or more embodiments of the present disclosure are not limited thereto, and the inner side surface of the sacrifice pattern SP defining the sacrifice opening OP-S can be substantially aligned with the inner side surface of the pixel definition film PDL defining the light emission opening OP-E. Here, the light emission area PXA can be considered as an area of the anode AE exposed from a corresponding light emission opening OP-E.

[0112] The pixel definition film PDL can include an inorganic insulating material. For example, the pixel definition film PDL can include silicon nitride (SiN x ). The pixel definition film PDL can be located between the anode AE and the partition wall PW to block electrical connection between the anode AE and the partition wall PW.

[0113] The emission pattern EP can be located on the anode AE. The emission pattern EP can include an emission layer including an emission material. The emission pattern EP can further include a hole injection layer and a hole transport layer located between the anode AE and the emission layer, and can further include an electron transport layer and an electron injection layer located on the emission layer. The emission pattern EP can be referred to as an "organic layer" or an "intermediate layer".

[0114] The emission pattern EP can be patterned by a tip portion defined in the partition wall PW. Details will be described later when describing a method of manufacturing a display panel. The emission pattern EP can be located inside the sacrificial opening OP-S and the emission opening OP-E. However, this is shown by way of example, and the emission pattern EP can be located inside at least one of the sacrificial opening OP-S, the emission opening OP-E, and the partition wall opening OP-P. The emission pattern EP can cover a top surface of a portion of the pixel definition film PDL.

[0115] The cathode CE can be located on the emission pattern EP. The cathode CE can be patterned by a tip portion defined in the partition wall PW. At least a portion of the cathode CE can be located in the partition wall opening OP-P, and a portion of the cathode layer patterned by the tip portion can provide a dummy layer DDL. The dummy layer DDL can include the same material as the cathode CE, and can be located in a portion of a separation area SA which will be described later with reference to FIG. 6. In this case, the dummy layer DDL can be referred to as a cathode dummy layer DDL. FIG. 5B FIG. 5A An example in which the cathode CE is located in the emission opening OP-E and the partition wall opening OP-P is shown. However, one or more embodiments of the present disclosure are not limited thereto. For example, the cathode CE can be located only in the partition wall opening OP-P.

[0116] The cathode CE can extend along an inner side surface of the first partition wall layer L1, and an end portion of the cathode CE can contact the first partition wall layer L1. FIG. 5A An example in which the cathode CE contacts the inner side surface of the first partition wall layer L1 and the inner side surface of the pixel definition film PDL is shown. However, one or more embodiments of the present disclosure are not limited thereto. For example, the cathode CE can contact only the inner side surface of the first partition wall layer L1.

[0117] ​The cathode CE can have an electrical conductivity. The cathode CE can be made of various materials such as a metal, a transparent conductive oxide (TCO), or a conductive polymer material, as long as the cathode CE can have an electrical conductivity. For example, the cathode CE can include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0118] The separation wall PW can be located on the pixel definition film PDL. A separation wall opening OP-P can be defined in the separation wall PW. The separation wall opening OP-P can overlap the light emission opening OP-E and can expose at least a portion of the anode AE.

[0119] The separation wall PW can include a plurality of layers sequentially stacked. For example, the separation wall PW can include a first separation wall layer L1, a separation wall insulating layer IL, and a second separation wall layer L2. The first separation wall layer L1 can be located on the pixel definition film PDL, the separation wall insulating layer IL can be located on the first separation wall layer L1, and the second separation wall layer L2 can be located on the separation wall insulating layer IL. As FIG. 5A As shown in FIG. 1B, a thickness of the first separation wall layer L1 can be greater than a thickness of each of the separation wall insulating layer IL and the second separation wall layer L2. However, one or more embodiments of the present disclosure are not limited thereto.

[0120] Each of the first separation wall layer L1 and the second separation wall layer L2 can include an electrically conductive material. For example, the electrically conductive material can include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal can include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), tungsten (W), or an alloy. The transparent conductive oxide can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. The materials of the first separation wall layer L1 and the second separation wall layer L2 are examples and are not limited to the above examples.

[0121] For example, the second separation wall layer L2 can include a material having a property of a melting point of about 970 degrees or more. In one or more embodiments, the second separation wall layer L2 can include at least one of titanium (Ti), molybdenum (Mo), and tungsten (W). When manufacturing the display panel, a voltage can be applied to the second separation wall layer L2 to remove a light emission pattern dummy layer formed in parallel or substantially simultaneously with deposition of the light emission pattern EP. For example, a voltage can be applied to the second separation wall layer L2 to cause Joule heating. Details will be described with reference to FIG. 7A through FIG. 7L

[0122] ​The separation wall insulating layer IL can include an insulating material. The separation wall insulating layer IL can be located between the first separation wall layer L1 and the second separation wall layer L2 to block an electrical connection between the first separation wall layer L1 and the second separation wall layer L2. For example, when including the separation wall insulating layer IL including an insulating material, a current flowing to the first separation wall layer L1 can be reduced or prevented when a voltage is applied to the second separation wall layer L2 and thus a current flows through the second separation wall layer L2.

[0123] In a cross-section, the separation wall PW can have an undercut shape. At least one of the plurality of layers of the separation wall PW can be recessed from the other layers, and thus, the separation wall PW can include a tip portion. For example, the first separation wall layer L1 can have an undercut shape with respect to each of the separation wall insulating layer IL and the second separation wall layer L2. The separation wall insulating layer IL and the second separation wall layer L2 can protrude from the first separation wall layer L1 toward the light emission opening OP-E to provide the tip portion. A portion of each of the separation wall insulating layer IL and the second separation wall layer L2 protruding from the first separation wall layer L1 toward the light emission area PXA can be defined as the tip portion in the separation wall PW. That is, each of the inner side surface of the separation wall insulating layer IL and the inner side surface of the second separation wall layer L2 can be closer to the center of the anode AE (for example, in a plan view) than the inner side surface of the first separation wall layer L1.

[0124] The separation wall opening OP-P of the separation wall PW can include a first area A1 and a second area A2. The first area A1 can be defined by the inner side surface of the first separation wall layer L1, and the second area A2 can be defined by the inner side surface of the separation wall insulating layer IL and the inner side surface of the second separation wall layer L2. A width in one direction (for example, in the first direction DR1 or the second direction DR2, or in a plan view) of the first area A1 can be greater than a width in one direction (for example, the first direction DR1 or the second direction DR2) of the second area A2.

[0125] FIG. 5A An example in which each of the inner side surface of the first separation wall layer L1, the inner side surface of the separation wall insulating layer IL, and the inner side surface of the second separation wall layer L2 is perpendicular to the top surface of the pixel definition film PDL is shown. However, one or more embodiments of the present disclosure are not limited thereto. For example, the separation wall PW can have a tapered shape, or can have a reverse tapered shape.

[0126] The separation wall PW can receive a driving voltage, and thus, the cathode CE can be electrically connected to the separation wall PW to receive the driving voltage.

[0127] The thin-film encapsulation layer (TFE) can be located on the display element layer of the DP-OLED. The TFE can include a lower inorganic encapsulation pattern (LIL), an organic encapsulation film (OL), and an upper inorganic encapsulation film (UIL).

[0128] The lower inorganic package pattern LIL can correspond to (overlapping) the light-emitting opening OP-E. The lower inorganic package pattern LIL can cover the light-emitting element ED. A portion of the lower inorganic package pattern LIL can be disposed in the partition wall opening OP-P, and another portion of the lower inorganic package pattern LIL can be disposed on the partition wall PW. In cross-section, the other portion of the lower inorganic package pattern LIL can be spaced apart from the top surface U_PW of the partition wall PW.

[0129] like FIG. 5B As shown, the separation region SA can be defined between the lower inorganic package pattern LIL and the spacer wall PW. The separation region SA can have a height (e.g., thickness) H_SA corresponding to the height (e.g., thickness) of the cathode CE. That is, the height H_SA of the separation region SA can be substantially the same as the thickness of the cathode CE located in the spacer wall opening OP-P, or substantially the same as the thickness of the dummy layer DDL disposed within the separation region SA. In one or more embodiments, the height H_SA of the separation region SA can be about 200 angstroms. Or smaller.

[0130] FIG. 5A An example is shown in which the cathode dummy layer DDL is located in the separation region SA. However, in one or more other embodiments, the separation region SA may be empty. That is, the cathode dummy layer DDL may be omitted from the separation region SA. In this case, the entire cathode dummy layer DDL can be removed by wet etching.

[0131] The organic encapsulation film OL can be located on the lower inorganic encapsulation pattern LIL. The organic encapsulation film OL can cover the lower inorganic encapsulation pattern LIL and can provide a flat top surface. The upper inorganic encapsulation film UIL can be located on the organic encapsulation film OL. The lower inorganic encapsulation pattern LIL, the common inorganic film, and the upper inorganic encapsulation film UIL can protect the DP-OLED display element layer from moisture / oxygen, and the organic encapsulation film OL can protect the DP-OLED display element layer from foreign matter such as dust particles.

[0132] FIG. 6 It is along FIG. 4 The sectional view taken from line II-II' in the middle. FIG. 6 An enlarged view of a first luminescent region PXA-R, a second luminescent region PXA-G, and a third luminescent region PXA-B is shown. FIG. 5AThe same / similar description of one light emitting area PXA in the above description can be applied to each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B in the display panel DP. FIG. 6 The same / similar description of one light emitting area PXA in the above description can be applied to each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B in the display panel DP. FIG. 5A The same / similar description of one light emitting area PXA in the above description can be applied to each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B in the display panel DP. FIG. 6 .

[0133] Referring to FIG. 6 , the display panel DP can include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED can include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel definition layer PDL, a partition wall PW, and a dummy layer DDL.

[0134] The light emitting elements ED1, ED2, and ED3 can include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 that emit light having colors different from each other, respectively. Each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be provided in plural, but for convenience of explanation, is referred to as a singular form hereinafter.

[0135] The first light emitting element ED1 can include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 can include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 can include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 can be provided as a plurality of patterns. In one or more embodiments, the first light emitting pattern EP1 can provide light having a red color, the second light emitting pattern EP2 can provide light having a green color, and the third light emitting pattern EP3 can provide light having a blue color.

[0136] The first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E can be defined in the pixel definition layer PDL. The first light emitting opening OP1-E can expose at least a portion of the first anode AE1. The second light emitting opening OP2-E can expose at least a portion of the second anode AE2. The third light emitting opening OP3-E can expose at least a portion of the third anode AE3.

[0137] The first light emission area PXA-R can be defined as an area of a top surface of the first anode AE1 exposed by the first light emission opening OP1-E. The second light emission area PXA-G can be defined as an area of a top surface of the second anode AE2 exposed by the second light emission opening OP2-E. The third light emission area PXA-B can be defined as an area of a top surface of the third anode AE3 exposed by the third light emission opening OP3-E.

[0138] The sacrifice patterns SP1, SP2, and SP3 can include a first sacrifice pattern SP1, a second sacrifice pattern SP2, and a third sacrifice pattern SP3. The first sacrifice pattern SP1, the second sacrifice pattern SP2, and the third sacrifice pattern SP3 can be located on top surfaces of the first anode AE1, the second anode AE2, and the third anode AE3, respectively. First, second, and third sacrifice openings OP1-S, OP2-S, and OP3-S overlapping the first, second, and third light emission openings OP1-E, OP2-E, and OP3-E, respectively, can be defined in the first, second, and third sacrifice patterns SP1, SP2, and SP3, respectively.

[0139] First, second, and third partition wall openings OP1-P, OP2-P, and OP3-P overlapping the first, second, and third light emission openings OP1-E, OP2-E, and OP3-E, respectively, can be defined in the partition wall PW.

[0140] The first, second, and third light emission patterns EP1, EP2, and EP3 and the first, second, and third cathodes CE1, CE2, and CE3 can be physically separated from each other by the partition wall insulating layer IL and the second partition wall layer L2 providing the tip portion, and can be disposed in the light emission openings OP1-E, OP2-E, and OP3-E and the partition wall openings OP1-P, OP2-P, and OP3-P. That is, the light emission elements ED1, ED2, and ED3 can be located in the partition wall openings OP1-P, OP2-P, and OP3-P and the light emission openings OP1-E, OP2-E, and OP3-E. For example, the first light emission element ED1 can be located in the first partition wall opening OP1-P and the first light emission opening OP1-E, the second light emission element ED2 can be located in the second partition wall opening OP2-P and the second light emission opening OP2-E, and the third light emission element ED3 can be located in the third partition wall opening OP3-P and the third light emission opening OP3-E.

[0141] According to one or more embodiments of the present disclosure, the plurality of first light emission patterns EP1 can be deposited by being patterned into the pixel units by the tip portion defined in the partition wall PW. That is, the first light emission patterns EP1 can be commonly formed using the opening mask, but can also be appropriately separated into the pixel units by the partition wall PW.

[0142] On the other hand, when the first light emitting pattern EP1 is patterned using a fine metal mask (FMM), a support spacer protruding from the conductive partition wall can be generally provided to support the fine metal mask. Also, since the fine metal mask is spaced apart from the base surface subjected to patterning by the height of the partition wall and the spacer, achieving high resolution can be limited. Also, when the fine metal mask contacts the spacer, foreign matter can be left on the spacer, or after the process of patterning the first light emitting pattern EP1, the spacer can be damaged due to the penetration of the fine metal mask. Thus, a defective display panel can be generated therefrom.

[0143] Since the partition wall PW is included, physical separation between the light emitting elements ED1, ED2, and ED3 can be properly achieved. Thus, driving error or current leakage between the adjacent light emitting areas PXA-R, PXA-G, and PXA-B can be reduced or prevented, and the light emitting elements ED1, ED2, and ED3 can be capable of being driven independently of each other.

[0144] For example, since the plurality of first light emitting patterns EP1 are patterned without a mask that contacts internal components in the display area DA (see FIG. 1B ), a defect rate can be reduced to provide a display panel DP with improved process reliability. Since patterning is possible even when a separate support spacer protruding from the partition wall PW is not provided, the respective surface areas of the light emitting areas PXA-R, PXA-G, and PXA-B can be minimized to provide a display panel DP that is properly achieved with high resolution.

[0145] Also, since the manufacturing of a mask having a large surface area is omitted in the manufacturing of the display panel DP having a large surface area, process costs can be reduced, and the display panel DP can be free from defects that can occur in a mask having a large surface area. Thus, a display panel DP with improved process reliability can be provided. The same / similar description of the plurality of first light emitting patterns EP1 can be applicable to the plurality of second light emitting patterns EP2 and third light emitting patterns EP3.

[0146] The thin film encapsulation layer TFE can include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0147] The lower inorganic encapsulation pattern LIL can include a first lower inorganic encapsulation pattern LIL1 covering the first light emitting element ED1, a second lower inorganic encapsulation pattern LIL2 covering the second light emitting element ED2, and a third lower inorganic encapsulation pattern LIL3 covering the third light emitting element ED3. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 can overlap the first light emission opening OP1-E, the second light emission opening OP2-E, and the third light emission opening OP3-E, respectively. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 can be disposed in the form of a pattern spaced apart from each other.

[0148] A portion of the first lower inorganic encapsulation pattern LIL1 can be defined in the partition wall opening OP-P, and another portion of the first lower inorganic encapsulation pattern LIL1 can be defined on the partition wall PW. On a cross-section, the other portion of the first lower inorganic encapsulation pattern LIL1 defined on the partition wall PW can be spaced apart from a top surface of the partition wall PW.

[0149] A portion of the second lower inorganic encapsulation pattern LIL2 can be defined in the partition wall opening OP-P, and another portion of the second lower inorganic encapsulation pattern LIL2 can be defined on the partition wall PW. On a cross-section, the other portion of the second lower inorganic encapsulation pattern LIL2 defined on the partition wall PW can be spaced apart from a top surface of the partition wall PW.

[0150] A portion of the third lower inorganic encapsulation pattern LIL3 can be defined in the partition wall opening OP-P, and another portion of the third lower inorganic encapsulation pattern LIL3 can be defined on the partition wall PW. On a cross-section, the other portion of the third lower inorganic encapsulation pattern LIL3 defined on the partition wall PW can be spaced apart from a top surface of the partition wall PW.

[0151] A separation area SA can be defined between each of the first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 and the partition wall PW. A height (e.g., a thickness) of the separation area SA can correspond to (e.g., can be substantially equal to) a height (e.g., a thickness) of the cathode CE.

[0152] In general, the height of the separation area corresponds to a sum of the thickness of the cathode and the thickness of the light emission pattern, and when the height of the separation area is large, over-etching (e.g., loss of a side surface portion) of the lower inorganic encapsulation pattern can occur in the manufacturing of the display panel.

[0153] REFERENCE FIG. 5A through FIG. 6The height H_SA of the separation area SA can correspond to the height of the cathode CE, and the height H_SA of the separation area SA can be relatively small. Since the height H_SA of the separation area SA is significantly smaller than the deposition thickness of the light emitting pattern EP (e.g., about 2000 angstroms to about 3000 angstroms), a subsequent light emitting pattern can not be located in the separation area SA. For example, with respect to the separation area SA corresponding to the first light emitting pattern EP1, the second light emitting pattern EP2 and the third light emitting pattern EP3 can not be located in the separation area SA corresponding to the first light emitting pattern EP1 during deposition of the second light emitting pattern EP2 and the third light emitting pattern EP3. Accordingly, in the manufacturing of the display panel, over-etching of the lower inorganic encapsulation pattern can be reduced or removed, and display panel defects due to water vapor permeation can be improved.

[0154] FIG. 7A through FIG. 7L are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. Identical / similar components to those described with reference to FIGS. 1 to 6 will be represented by identical / similar reference numerals or signs and will be described by omitting redundant descriptions. FIG. 6 FIG. 7A through FIG. 7L .

[0155] A method of manufacturing a display panel according to one or more embodiments of the present disclosure can include providing an initial display panel including a base layer and a pixel definition film located on the base layer, can include forming an initial separation wall having a first initial separation wall layer including a conductive material, an initial separation wall insulation layer including an insulating material, and a second initial separation wall layer including a conductive material on the pixel definition film, can include forming a separation wall having a separation wall opening from the initial separation wall, can include etching the pixel definition film to form a light emitting opening overlapping the separation wall opening, can include forming a light emitting pattern in the light emitting opening and a light emitting pattern dummy layer including the same material as the light emitting pattern on the separation wall, and can include applying heat to the separation wall to remove the light emitting pattern dummy layer.

[0156] Hereinafter, a method for forming one light emitting element ED and for forming a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL covering the light emitting element ED will be described with reference to FIG. 7A through FIG. 7L The display panel DP formed by the method described with reference to FIG. 7A through FIG. 7L may correspond to the display panel DP in FIG. 5A .

[0157] Reference will now be made to FIG. 7A ​A method of manufacturing a display panel according to one or more embodiments of the disclosure can include providing an initial display panel DP-I. The initial display panel DP-I can include a base layer BL, a circuit element layer DP-CL, an anode AE, an initial sacrificial pattern SP-I, and a pixel definition film PDL.

[0158] The circuit element layer DP-CL can be formed by a typical process for manufacturing a circuit element by forming an insulating layer, a semiconductor layer, and a conductive layer through a method such as coating or deposition, and then selectively patterning the insulating layer, the semiconductor layer, and the conductive layer to form a semiconductor pattern, a conductive pattern, a signal line, etc. through a photolithography process and an etching process.

[0159] The anode AE and the initial sacrificial pattern SP-I can be formed through the same patterning process. The pixel definition film PDL can be located on the base layer BL. The pixel definition film PDL can cover both the anode AE and the initial sacrificial pattern SP-I.

[0160] Further, a method of manufacturing a display panel according to one or more embodiments of the disclosure can include forming an initial partition wall PW-I on the pixel definition film PDL. The initial partition wall PW-I can include a first initial partition wall layer L1-I, an initial partition wall insulating layer IL-I, and a second initial partition wall layer L2-I.

[0161] The first initial partition wall layer L1-I, the initial partition wall insulating layer IL-I, and the second initial partition wall layer L2-I can be formed through a process of depositing a conductive material. The first initial partition wall layer L1-I can be deposited on the pixel definition film PDL, the initial partition wall insulating layer IL-I can be deposited on the first initial partition wall layer L1-I, and the second initial partition wall layer L2-I can be deposited on the initial partition wall insulating layer IL-I.

[0162] Each of the first and second initial partition wall layers L1-I and L2-I can include an electrically conductive material. For example, the electrically conductive material can include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal can include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), tungsten (W), or an alloy. The transparent conductive oxide can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. For example, the second initial partition wall layer L2-I can include a material having a property of a melting point of about 970 degrees or more. In one or more embodiments, the second initial partition wall layer L2-I can include at least one of titanium (Ti), molybdenum (Mo), and tungsten (W). The materials of the first and second initial partition wall layers L1-I and L2-I are examples, and are not limited to the above-described examples.

[0163] The initial partition wall insulating layer IL-I can include an insulating material. The initial partition wall insulating layer IL-I can be located between the first and second initial partition wall layers L1-I and L2-I to block an electrical connection between the first and second initial partition wall layers L1-I and L2-I.

[0164] Thereafter, referring to FIG. 7B , the method of manufacturing a display panel according to one or more embodiments of the disclosure can include forming a first photoresist layer PR1 on the initial partition wall PW-I. The first photoresist layer PR1 can be formed by forming an initial photoresist layer on the initial partition wall PW-I and then patterning the initial photoresist layer by using a photomask. A photo opening OP-PR can be formed in the first photoresist layer PR1 by a patterning process. The photo opening OP-PR can overlap the anode AE.

[0165] Thereafter, referring to FIG. 7C and FIG. 7D , the method of manufacturing a display panel according to one or more embodiments of the disclosure can include forming a partition wall PW having a partition wall opening OP-P from the initial partition wall PW-I (see FIG. 7B ). Forming the partition wall PW can include a first etching of the first and second initial partition wall layers L1-I and L2-I and a second etching of the first initial partition wall layer L1-I.

[0166] First, as FIG. 7CAs shown, in the first etching of the first initial separator layer L1-I, the initial separator insulating layer IL-I, and the second initial separator layer L2-I, the first initial separator layer L1-I, the initial separator insulating layer IL-I, and the second initial separator layer L2-I can be dry-etched using the first photoresist layer PR1 as a mask. The portion of the initial separator PW-I that does not overlap with the first photoresist layer PR1 can be etched away. The initial separator opening OP-PI can be formed in the portion that overlaps with the photoresist opening OP-PR and is removed.

[0167] The first dry etching process can be performed in an etching environment in which the etching selectivity of the first initial partition wall layer L1-I, the initial partition wall insulating layer IL-I, and the second initial partition wall layer L2-I is substantially the same. Therefore, the inner surfaces of the first initial partition wall layer L1-I, the inner surfaces of the initial partition wall insulating layer IL-I, and the inner surfaces of the second initial partition wall layer L2-I that define the initial partition wall opening OP-PI can be substantially aligned with each other.

[0168] Then, as FIG. 7D As shown, in the first initial partition wall layer L1-I (see...) FIG. 7C In the second etching, the first initial partition layer L1-I can be wet-etched using the first photoresist layer PR1 as a mask. Therefore, a portion of the first initial partition layer L1-I can be etched to form a partition opening OP-P. The partition opening OP-P can be formed to overlap with the anode AE.

[0169] The partition wall opening OP-P of the partition wall PW may include a first region A1 and a second region A2. The first region A1 may be defined by the inner surface of the first partition wall layer L1, and the second region A2 may be defined by the inner surface of the partition wall insulating layer IL and the inner surface of the second partition wall layer L2. The width of the first region A1 in one direction (e.g., in the direction perpendicular to the third direction DR3, or in a plan view) may be greater than the width of the second region A2 in one direction (e.g., in the direction perpendicular to the third direction DR3, or in a plan view).

[0170] The first initial partition wall layer L1-I can be located therein (see FIG. 7C ), initial separator wall insulation layer IL-I (see FIG. 7C ) and the second initial partition wall layer L2-I (see FIG. 7EThe second wet etching process in one or more embodiments of the disclosure is performed in an etching environment in which the etching selectivity difference between the first initial separation wall layer L1-I and each of the initial separation wall insulating layer IL-I and the second initial separation wall layer L2-I is relatively large. Accordingly, in a cross section, the inner side surface of the separation wall PW defining the separation wall opening OP-P can have an undercut shape. For example, since the etching rate of the first initial separation wall layer L1-I is higher than the etching rate of each of the initial separation wall insulating layer IL-I and the second initial separation wall layer L2-I with respect to the etchant, the first initial separation wall layer L1-I can be etched mainly. Accordingly, the inner side surface of the first separation wall layer L1 can be formed to be recessed inward from each of the inner side surface of the separation wall insulating layer IL and the inner side surface of the second separation wall layer L2. A tip portion can be formed in the separation wall PW through the portion of each of the separation wall insulating layer IL and the second separation wall layer L2 protruding from the first separation wall layer L1.

[0171] Hereinafter, with reference to FIG. 7F , the method of manufacturing a display panel according to one or more embodiments of the disclosure can include etching the pixel definition film PDL to form a light emission opening OP-E overlapping the separation wall opening OP-P.

[0172] In etching the pixel definition film PDL, the pixel definition film PDL can be dry-etched by using the first photoresist layer PR1 and the separation wall PW (e.g., the second separation wall layer L2) as a mask. The portion of the pixel definition film PDL not overlapping the first photoresist layer PR1 and the separation wall PW can be etched to be removed. Accordingly, the light emission opening OP-E overlapping the separation wall opening OP-P can be formed in the pixel definition film PDL.

[0173] Hereinafter, with reference to FIG. 7E , the method of manufacturing a display panel according to one or more embodiments of the disclosure can include etching the initial sacrificial pattern SP-I (see FIG. 7G ) to form a sacrificial pattern SP having a sacrificial opening OP-S overlapping the light emission opening OP-E.

[0174] In etching the initial sacrificial pattern SP-I, the initial sacrificial pattern SP-I can be wet-etched by using the first photoresist layer PR1 and the separation wall PW (e.g., the second separation wall layer L2) as a mask. The portion of the initial sacrificial pattern SP-I not overlapping the first photoresist layer PR1 and the separation wall PW can be etched to be removed. Accordingly, the sacrificial pattern SP can be formed from the initial sacrificial pattern SP-I.

[0175] The etching of the sacrificial pattern SP can be performed in an etching environment in which a difference in etching selectivity between the sacrificial pattern SP and the anode AE is large, and thus the anode AE can not be etched together with the sacrificial pattern SP. That is, the sacrificial pattern SP having a higher etching rate than the anode AE can be located between the pixel definition film PDL and the anode AE so that the anode AE is not etched together with it and is not damaged during etching.

[0176] Thereafter, referring to FIG. 7F , the method of manufacturing a display panel can include forming a light emitting pattern EP in the light emitting opening OP-E and forming a light emitting pattern dummy layer D_EP on the partition wall PW after removing the first photoresist layer PR1 (see FIG. 7H ).

[0177] Forming the light emitting pattern EP can include a process of depositing a light emitting layer. For example, forming the light emitting pattern EP can include performing thermal evaporation on the light emitting layer. The light emitting layer can be separated by the tip portion formed on the partition wall PW to be deposited within the partition wall opening OP-P and on the partition wall PW. The light emitting layer formed in the partition wall opening OP-P can form the light emitting pattern EP, and the light emitting layer formed on the partition wall PW can form the light emitting pattern dummy layer D_EP. That is, the light emitting pattern EP can be formed on the anode AE to overlap the partition wall opening OP-P, and the light emitting pattern EP can be formed while covering the anode AE and the pixel definition film PDL.

[0178] The light emitting pattern dummy layer D_EP formed during forming the light emitting pattern EP can include an organic material. For example, the light emitting pattern dummy layer D_EP can include the same material as the light emitting pattern EP. The light emitting pattern dummy layer D_EP can be formed in parallel or substantially simultaneously with the light emitting pattern EP through one process, and then can be separated from the light emitting pattern EP due to the undercut shape of the partition wall PW.

[0179] Thereafter, referring to FIG. 7I , the method of manufacturing a display panel according to one or more embodiments of the present disclosure can include applying heat to the partition wall PW to remove the light emitting pattern dummy layer D_EP.

[0180] When heat is applied to the partition wall PW to remove the light emitting pattern dummy layer D_EP, a voltage PE can be applied to the second partition wall layer L2 to cause Joule heating. Due to the Joule heating, the light emitting pattern dummy layer D_EP located on the second partition wall layer L2 can be removed. Since the light emitting pattern dummy layer D_EP includes an organic material, the light emitting pattern dummy layer D_EP can evaporate at a temperature of about 250 degrees to about 350 degrees, and the second partition wall layer L2 can not be evaporated due to being made of a metal having a high melting point. According to one or more embodiments of the present disclosure, since a process for the light emitting pattern dummy layer D_EP by Joule heating can be appropriately used only by applying a voltage, the process can be appropriately performed.

[0181] In the above process, a partition wall insulating layer IL can be located between the first partition wall layer L1 and the second partition wall layer L2 to block an electrical connection between the first partition wall layer L1 and the second partition wall layer L2. That is, when the voltage PE is applied to the second partition wall layer L2 and thus a current flows through the second partition wall layer L2, the current flowing to the first partition wall layer L1 can be reduced or prevented. Thus, heat caused by Joule heating can not be transferred to the first partition wall layer L1.

[0182] Thereafter, referring to FIG. 7H A method of manufacturing a display panel can include forming a cathode CE in the light emitting opening OP-E and the partition wall opening OP-P and forming a cathode dummy layer D_CE including the same material as the cathode CE on the partition wall PW.

[0183] Forming the cathode CE can include a process of depositing a cathode layer. For example, forming the cathode CE can include sputtering the cathode layer. The cathode layer can be separated by a tip portion formed on the partition wall PW to be deposited inside the partition wall opening OP-P and on the partition wall PW. The cathode layer formed in the partition wall opening OP-P can form the cathode CE, and the cathode layer formed on the partition wall PW can form the cathode dummy layer D_CE. That is, the cathode CE can be formed on the light emitting pattern EP to overlap the partition wall opening OP-P, and the cathode CE can be formed while covering the light emitting pattern EP. Further, the cathode CE can be formed to contact an inner side surface of the partition wall PW to extend along the inner side surface of the partition wall PW.

[0184] The cathode dummy layer D_CE formed together when the cathode CE is formed can include a conductive material. For example, the cathode dummy layer D_CE can include the same material as the cathode CE. The cathode dummy layer D_CE can be formed in parallel or substantially simultaneously with the cathode CE by one process, and then can be separated from the cathode CE due to an undercut shape of the partition wall PW. When the light emitting pattern dummy layer D_EP (see FIG. 7JThe dummy cathode layer D_CE can be directly positioned on the partition wall PW when removed in the previous process.

[0185] The anode AE, the light emitting pattern EP, and the cathode CE can be sequentially stacked in the third direction DR3. The anode AE, the light emitting pattern EP, and the cathode CE can form the light emitting element ED.

[0186] Thereafter, referring to FIG. 7K and FIG. 7J , the method of manufacturing a display panel according to one or more embodiments of the present disclosure can include forming a lower inorganic encapsulation pattern LIL on the cathode CE. Forming the lower inorganic encapsulation pattern LIL can include depositing a lower inorganic encapsulation layer LIL-I and removing a portion of the lower inorganic encapsulation layer LIL-I that does not overlap the light emitting element ED. Depositing the lower inorganic encapsulation layer LIL-I will be described with reference to FIG. 7K and removing the portion of the lower inorganic encapsulation layer LIL-I that does not overlap the light emitting element ED will be described with reference to FIG. 7J .

[0187] First, referring to FIG. 7K , forming the lower inorganic encapsulation pattern LIL can include depositing the lower inorganic encapsulation layer LIL-I. In one or more embodiments, the lower inorganic encapsulation layer LIL-I can be formed by a chemical vapor deposition (CVD) process. The lower inorganic encapsulation layer LIL-I can be formed to cover the cathode CE and the partition wall PW.

[0188] Then, a second photoresist layer PR2 can be formed on the lower inorganic encapsulation layer LIL-I. In forming the second photoresist layer PR2, an initial photoresist layer can be formed, and then the initial photoresist layer can be patterned using a photomask to form the second photoresist layer PR2. The second photoresist layer PR2 can be formed in a pattern corresponding to the light emitting element ED by a patterning process.

[0189] Thereafter, referring to FIG. 7J , forming the lower inorganic encapsulation pattern LIL can include removing a portion of the lower inorganic encapsulation layer LIL-I (see FIG. 5A ) that does not overlap the light emitting element ED.

[0190] In removing the portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the light emitting element ED, the second photoresist layer PR2 can be used as a mask for dry etching the lower inorganic encapsulation layer LIL-I. The portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the second photoresist layer PR2 can be removed, and the portion of the lower inorganic encapsulation layer LIL-I that is not etched to thereby remain can form a lower inorganic encapsulation pattern LIL. The portion of the lower inorganic encapsulation pattern LIL that is etched and formed can be formed in the separation wall opening OP-P, and another portion of the lower inorganic encapsulation pattern LIL can be formed on the separation wall PW. In a cross-section, the other portion of the lower inorganic encapsulation pattern LIL can be spaced apart from a top surface U_PW (see FIG. 7L ) of the separation wall PW.

[0191] Then, referring to FIG. 7K , the method of manufacturing a display panel according to one or more embodiments of the present disclosure can include, after removing the second photoresist layer PR2 (see FIG. 6 ), removing a portion or all of the dummy cathode layer D_CE, and forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the display panel DP.

[0192] In removing the portion or all of the dummy cathode layer D_CE, the dummy cathode layer D_CE can be removed by wet etching. The organic encapsulation film OL can be formed by applying an organic material through an inkjet process, but one or more embodiments of the present disclosure are not limited thereto. The organic encapsulation film OL can provide a planarized top surface. Thereafter, an inorganic material can be deposited to form the upper inorganic encapsulation film UIL. Accordingly, the display panel DP including the base layer BL, the circuit element layer DP-CL, the display element layer DP-OLED, and the thin film encapsulation layer TFE can be formed.

[0193] Further, between forming the lower inorganic encapsulation pattern LIL and completing the display panel DP, forming separation wall openings OP1-P, OP2-P, and OP3-P (see FIG. 6 ) and light emitting openings OP1-E, OP2-E, and OP3-E (see FIG. 6 ) in the separation wall PW and the pixel definition film PDL, which correspond to light emitting regions having different colors, respectively, forming light emitting elements ED1, ED2, and ED3 (see FIG. 6 ) that respectively provide light of different colors, and forming lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 (see FIG. 6 ) that cover the light emitting elements ED1, ED2, and ED3 (see FIG. 7A through FIG. 7K). Forming the partition wall openings OP1-P, OP2-P, and OP3-P and the light emitting openings OP1-E, OP2-E, and OP3-E, forming the light emitting elements ED1, ED2, and ED3, and forming the lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 can be substantially the same as described with reference to FIG. 6 . Thus, the display panel DP shown in FIG. 1A can be formed. FIG. 8 The display panel DP shown in FIG. 1A can include the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 corresponding to the plurality of light emitting regions PXA-R, PXA-G, and PXA-B, respectively, and the first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 corresponding to the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, respectively.

[0194] FIG. 3 is a cross-sectional view taken along the line I-I' in FIG. 8 . The cross-sectional view in FIG. 1A corresponds to the cross-sectional view in FIG. 1B, and FIG. 5A The cross-sectional view in FIG. 1A corresponds to the cross-sectional view in FIG. 1B, and FIG. 8 The cross-sectional view in FIG. 1A corresponds to the cross-sectional view in FIG. 1B, and FIG. 7L One or more other embodiments of the present disclosure are illustrated. Components identical / similar to those described with reference to FIGS. 1 to FIG. 8 will be described by omitting redundant descriptions. FIG. 8 .

[0195] With reference to FIG. 1A, FIG. 5A The display panel DPa can include the base layer BL, the circuit element layer DP-CL, the display element layer DP-OLEDa, and the thin film encapsulation layer TFE. The display element layer DP-OLEDa can include the light emitting element ED, the capping pattern CP, the sacrificial pattern SP, the pixel definition layer PDL, the partition wall PW, and the dummy layer DDLa.

[0196] In comparison with the display element layer DP-OLED in FIG. 8 , the display element layer DP-OLEDa in FIG. 8 may further include the capping pattern CP. The capping pattern CP can be located in the partition wall opening OP-P, and can be located on the cathode CE. The capping pattern CP can be patterned by the tip portion defined in the partition wall PW.

[0197] The portion of the capping pattern layer patterned by the tip portion can provide the capping pattern dummy layer D_CP on the partition wall PW. The capping pattern dummy layer D_CP can include the same material as the capping pattern CP, and can be disposed on the cathode dummy layer D_CE. The cathode dummy layer D_CE and the capping pattern dummy layer D_CP can provide the dummy layer DDLa.

[0198] The separation area SAa can be defined between the lower inorganic encapsulation pattern LIL and the partition wall PW. The dummy layer DDLa can be located in a portion of the separation area SAa. That is, the cathode dummy layer D_CE and the cap pattern dummy layer D_CP can be located in the separation area SAa. The height (e.g., thickness) H_SAa of the separation area SAa can correspond to the sum of the height (e.g., thickness) of the cathode CE and the height (e.g., thickness) of the cap pattern CP. That is, the height H_SAa of the separation area SAa can be substantially the same as the thickness of the dummy layer DDLa provided within the separation area SAa.

[0199] Manufacturing FIG. 7I The method of manufacturing the display panel DPa in the reference FIG. 7J and FIG. 8 may further include forming the cap pattern CP in the partition wall opening OP-P and forming a cap pattern dummy layer D_CP including the same material as the cap pattern CP on the partition wall PW between the operations described in the reference

[0200] ​ An example in which the dummy layer DDLa is located in the separation area SAa is illustrated. However, in one or more other embodiments, the separation area SAa can be empty. In this case, the entire dummy layer DDLa can be removed by wet etching.

[0201] As described above, a separation area can be defined between the lower inorganic encapsulation pattern and the partition wall. The height of the separation area can correspond to the height of the cathode, and the height of the separation area can be relatively small. Since the height of the separation area is significantly smaller than the deposition thickness (about 2000 angstroms to about 3000 angstroms) of the light emitting pattern, the subsequent light emitting pattern can not be located in the separation area. Accordingly, in manufacturing the display panel, over-etching of the lower inorganic encapsulation pattern can be reduced or removed, and display panel defects due to water vapor permeation can be improved.

[0202] Although embodiments of the disclosure have been described, it is understood that the disclosure should not be limited to these embodiments but various changes and modifications can be made by one ordinarily skilled in the art within the spirit and scope of the disclosure as claimed. Accordingly, the technical scope of the disclosure is not limited to what is described in the detailed description of the specification but should be determined by the claims along with their functional equivalents.

Claims

1. A display panel, characterized by, The display panel includes: a base layer; a pixel definition film over the base layer and defining a light emission opening; a separation wall over the pixel definition film, defining a separation wall opening corresponding to the light emission opening, and including: a first separation wall layer including a first conductive material; a separation wall insulating layer over the first separation wall layer and including an insulating material; and a second separation wall layer over the separation wall insulating layer and including a second conductive material; and a light emitting element in the light emission opening and the separation wall opening and including an anode, a light emission pattern, and a cathode, the cathode contacting the separation wall.

2. The display panel of claim 1, wherein, The separation wall opening includes: a first region defined by an inner side surface of the first separation wall layer; and a second region defined by an inner side surface of the separation wall insulating layer and an inner side surface of the second separation wall layer, wherein a width in one direction of the first region is greater than a width in the one direction of the second region.

3. The display panel of claim 1, wherein, The display panel further includes a lower inorganic encapsulation pattern covering the light emitting element and spaced apart from a top surface of the separation wall.

4. The display panel of claim 3, wherein, A separation region is defined between the lower inorganic encapsulation pattern and the separation wall, and wherein a thickness of the separation region is equal to a thickness of the cathode.

5. The display panel of claim 4, wherein, The display panel further includes a cathode dummy layer in a portion of the separation region and including a same material as the cathode.

6. The display panel of claim 4, wherein, The separation region is empty.

7. The display panel of claim 4, wherein, The thickness of the separation region is 200 angstroms or less.

8. The display panel of claim 4, wherein, The display panel further includes a capping pattern over the cathode, wherein the thickness of the separation region corresponds to a sum of the thickness of the cathode and a thickness of the capping pattern.

9. The display panel of claim 1, wherein, The second separation wall layer includes at least one of titanium, molybdenum, and tungsten.

10. The display panel of claim 1, wherein, The second separation wall layer includes a material having a melting point of 970 degrees or higher. The second separation wall layer includes a material having a melting point of 970 degrees or higher.

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