PCIe jig

Abstract

The utility model relates to the field of testing, and discloses a PCIe jig. The PCIe jig comprises at least two sub-jigs and a peripheral component, each sub-jig comprises a circuit board, and the circuit board comprises a connecting interface which is used for being electrically connected with equipment to be tested; the connection interface comprises m signal detection interfaces; the circuit board comprises a detection links and b auxiliary links, and the a detection links and the b auxiliary links are connected with the m signal detection interfaces in a one-to-one correspondence manner; wherein a, b and m are all positive integers, and m = a + b. The PCIe jig provided by the embodiment of the utility model is used for reducing the size of the jig so as to enable the jig to adapt to the signal test of the to-be-tested equipment under the limitation of the whole machine environment space.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a PCIe jig. BACKGROUND

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, widely used to connect various peripherals such as graphics cards, network adapters, storage controllers, etc. The quality of PCIe slots directly affects the performance and stability of these peripherals. Therefore, when producing, maintaining or upgrading servers, it is very important to ensure that the PCIe slots are functioning properly.

[0003] PCIe jigs are specially designed tools used to test the functionality and electrical performance of PCIe slots without directly inserting PCIe devices into the circuit board. It usually contains analog load, signal integrity test circuit, power management module, etc., which can fully evaluate the performance of PCIe slots.

[0004] However, due to the problem of space limitation in the whole machine environment, the current PCIe jig cannot adapt to the signal test of PCIe slots in the whole machine environment. CONTENT OF THE INVENTION

[0005] The present application discloses a PCIe jig for reducing the size of the jig to adapt the jig to the signal test of the device under test in the whole machine environment space limitation.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] A PCIe jig, comprising: at least two sub-jigs;

[0008] Each of the sub-jigs comprises a circuit board, the circuit board comprising a connection interface for electrical connection with the device under test; the connection interface comprising m signal detection interfaces;

[0009] The circuit board comprises a detection link and b auxiliary links, the a detection links and the b auxiliary links are connected one by one with the m signal detection interfaces; wherein a, b, m are positive integers, and m=a+b.

[0010] The PCIe jig provided by the embodiments of the present application completes signal detection of all channels of the device under test through multiple sub-jigs. Specifically, each sub-jig completes detection of part of the signal channels of the device under test. For example, the device under test has m signal channels, the PCIe jig includes two sub-jigs, the first sub-jig has a detection link for detecting a signal channel in the m signal channels of the device under test, and the second sub-jig has a detection link for detecting a signal channel in the m signal channels of the device under test. In order to ensure the normal connection of the detection channel signal, each sub-jig also has an auxiliary link, for example, the first sub-jig has b auxiliary links for grounding the m-a signal channels of the device under test, and the second sub-jig has a auxiliary links for grounding the m-b signal channels of the device under test. During actual detection, the connection interface of the first sub-jig can be first electrically connected with the device under test to complete detection of the a signal channels of the device under test, and then the connection interface of the first sub-jig is disconnected from the device under test, and the connection interface of the second sub-jig is electrically connected with the device under test to complete detection of the b signal channels of the device under test.

[0011] Therefore, the PCIe jig provided by the embodiments of the present application splits the signal channels of the device under test into multiple groups for separate detection, and uses a sub-jig to detect only one group, so that the detection link on each sub-jig is reduced, thereby achieving the purpose of reducing the size of the jig. The small-size sub-jig can adapt to the signal test of the device under test under the space limitation of the whole machine environment.

[0012] In some embodiments, the detection link includes an input connector, a first wire, an output connector and a second wire; the circuit board includes a first face and a second face arranged oppositely; the input connector and the first wire are arranged on the first face, and the output connector and the second wire are arranged on the second face;

[0013] The signal detection interface connected with the detection link includes two detection terminals, and the two detection terminals are arranged on the first face and the second face, respectively;

[0014] The input connector is electrically connected with the detection terminal on the first face through the first wire, and the output connector is electrically connected with the detection terminal on the second face through the second wire.

[0015] The input end connector and the first trace in each detection link of the sub-jig are arranged on the first surface of the circuit board, and the output end connector and the second trace are arranged on the second surface of the circuit board. The first trace and the detection terminal on the first surface are electrically connected, and the second trace and the detection terminal on the second surface are electrically connected. Arranging the input end connector and the output end connector on the two opposite surfaces of the circuit board can improve the utilization rate of the limited area of the jig.

[0016] In some embodiments, the input end connector and / or the output end connector is an SMP connector. The SMP connector (SubMiniature Push-on / Pull-off Connector) is a high-frequency coaxial connector, and the SMP connector is small in size and light in weight, and is suitable for space-limited applications.

[0017] In some embodiments, a plurality of input end connectors are arranged in a fan shape around the connection interface on the first surface;

[0018] a plurality of output end connectors are arranged in a fan shape around the connection interface on the second surface.

[0019] All input end connectors in the sub-jig adopt a fan-shaped layout, so that the lengths of all first traces are relatively average, which is more conducive to equal-length drawing of the first traces while maximizing the space utilization. Similarly, all output end connectors adopt a fan-shaped layout, so that the lengths of all second traces are relatively average, which is more conducive to equal-length drawing of the second traces while maximizing the space utilization.

[0020] In some embodiments, the distance from the input end connector to the first edge of the circuit board is not equal to the distance from the output end connector to the first edge of the circuit board; wherein the first edge is the edge of the circuit board close to the connection interface. It can be understood that the fan-shaped radius of the input end connector distributed in the fan shape on the first surface is not equal to the fan-shaped radius of the output end connector distributed in the fan shape on the second surface. For example, the fan-shaped radius of the input end connector is greater than the fan-shaped radius of the output end connector; or, the fan-shaped radius of the output end connector is greater than the fan-shaped radius of the input end connector. The orthographic projection of the input end connector on the circuit board and the orthographic projection of the output end connector on the circuit board do not overlap, which facilitates the arrangement of the connectors and facilitates disassembly during the test process.

[0021] In some embodiments, the first trace and the second trace are both single-ended signal traces. In a limited space, the single-ended trace design is relatively simple and easy to wire.

[0022] In some embodiments, the auxiliary link includes a first termination resistor and a second termination resistor; the first termination resistor is fixedly arranged on the first surface, and the second termination resistor is fixedly arranged on the second surface;

[0023] In the one-to-one correspondence connection between the auxiliary link and the signal detection interface, the first termination resistor is electrically connected with the detection terminal on the first surface, and the second termination resistor is electrically connected with the detection terminal on the second surface.

[0024] The PCIe jig provided by the embodiment of the application is used for terminating the signal channel through end resistor which is not used in the connection interface of the sub-jig, so as to ensure the normal connection of other channel signals.

[0025] In some embodiments, the connection interface is a gold finger. The sub-jig can be electrically connected with the device to be detected through the gold finger on the circuit board. Taking the PCIe slot as an example, the circuit board is inserted into the PCIe slot through the gold finger. The gold finger has the advantages of reliable electrical contact, strong durability, good electrical conductivity, easy processing, strong compatibility, and convenient maintenance and replacement.

[0026] In some embodiments, the circuit board further comprises a ground hole located on a side of the gold finger away from the first trace or the second trace in the detection link. The ground hole is arranged on the side of the gold finger away from the wire outlet end, so as to avoid the risk of process manufacturing.

[0027] In some embodiments, the circuit board comprises a first signal layer, a second signal layer, and a ground layer located between the first signal layer and the second signal layer; the first trace is arranged on the first signal layer, and the second trace is arranged on the second signal layer; and the ground layer is four layers. The six-layer board design is adopted for the layers of the jig, the signal lines are arranged on the upper and lower layers, and the middle four layers are ground, so as to reduce the cost as much as possible under the condition that the traces have complete reference ground. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Structure diagram of the first jig in the PCIe jig provided by the embodiment of the application Figure 1 ;

[0029] Figure 2 Structure diagram of the first jig in the PCIe jig provided by the embodiment of the application Figure 2 ;

[0030] Figure 3 Structure diagram of the second jig in the PCIe jig provided by the embodiment of the application Figure 1 ;

[0031] Figure 4 Structure diagram of the second jig in the PCIe jig provided by the embodiment of the application Figure 2 ;

[0032] Figure 5 For Figure 2 Enlarged view of C in FIG. 7

[0033] Figure 6 A schematic diagram of a layer structure of a circuit board in a PCIe jig is provided for the embodiments of the present application.

[0034] Icon: 1-circuit board; 2-connection interface; 3-detection link; 4-assistant link; 10-ground hole; 11-first signal layer; 12-second signal layer; 13-ground layer; 1A-first surface; 1B-second surface; 31-input connector; 32-first trace; 33-output connector; 34-second trace; 21-signal pin; 41-first termination resistance; 42-second termination resistance; 43-third trace; 44-fourth trace. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; the "and / or" in the text only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0036] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" is two or more than two.

[0037] PCIe interface provides different channel quantity and bandwidth support, mainly PCIe x1, PCIe x4, PCIe x8 and PCIe X16, etc. Common specifications. The purpose of the PCIe jig is to cooperate with the interface, and the specification and the interface specification are synchronized. PCIe jigs are used to verify the functions and performance of PCIe devices, including transmission speed, data integrity, electrical characteristics, etc. They are also used to evaluate the stability and reliability of PCIe devices under different working conditions. Currently, PCIe slots have become the main expansion slots on the motherboard, and PCIe jigs are a special tool for testing and verifying the performance and functions of PCIe devices.

[0038] As Figures 1 to 5 shown, the embodiment of the present application provides a PCIe jig, comprising: at least two sub-jigs;

[0039] Each sub-jig comprises a circuit board 1, which comprises a connection interface 2 for electrical connection with a device under test; the connection interface 2 comprises m signal detection interfaces;

[0040] The circuit board 1 comprises a detection link 3 and an auxiliary link 4, and the a detection links 3 and the b auxiliary links 4 are connected one by one with the m signal detection interfaces; wherein a, b, and m are positive integers, and m = a + b.

[0041] The PCIe jig provided by the embodiment of the present application completes the signal detection of all channels of the device under test through multiple sub-jigs. Specifically, each sub-jig completes the detection of part of the signal channels of the device under test. For example, the device under test has m signal channels, the PCIe jig comprises two sub-jigs, the first sub-jig has a detection link 3 for detecting a signal channel in the m signal channels of the device under test, and the second sub-jig has b detection links 3 for detecting b signal channels in the m signal channels of the device under test. In order to ensure the normal connection of the detection channel signal, each sub-jig also has an auxiliary link 4, such as the first sub-jig having b auxiliary links 4 for grounding the m-a signal channels in the device under test. For example, the second sub-jig has a auxiliary link 4 for grounding the m-b signal channels in the device under test. During actual detection, the connection interface 2 of the first sub-jig can be first electrically connected with the device under test to complete the detection of the a signal channels in the device under test; then the connection interface 2 of the first sub-jig is disconnected from the device under test, and the connection interface 2 of the second sub-jig is electrically connected with the device under test to complete the detection of the b signal channels in the device under test.

[0042] Therefore, the PCIe jig provided by the embodiment of the present application splits the signal channels of the device under test into multiple groups for separate detection, and uses a sub-jig to detect only one group, so that the detection links 3 on each sub-jig are reduced, thereby achieving the purpose of reducing the size of the jig. The small-size sub-jig can adapt to the signal test of the device under test under the space limitation of the whole machine environment.

[0043] In some embodiments, the PCIe jig is connected with a PCIe slot required to be tested, and a signal end on the PCIe jig is used to connect with a test instrument, wherein a receiving end corresponding to a signal required to be tested is connected with a signal generator, and a sending end corresponding to the signal required to be tested is connected with a high-speed oscilloscope, and the PCIe signal channels are tested in turn.

[0044] For the case of space limitation of internal structure in the whole machine environment, the PCIe jig provided by the embodiment of the application is adopted to complete the test of PCIe signals by cooperating with multiple separated small-sized sub-jigs. The PCIe jig provided by the embodiment of the application is based on the high-speed PCIe signal integrity of the PCIe slot in the whole machine in the special environment of the test server. At present, the X16 slot with the most PCIe channels is taken as an example. The size of the PCIe X16 jig is reduced by the separated method to meet the needs of the whole machine signal test.

[0045] According to the idea of splitting the channels of the complete PCIe X16, the 16 channels are divided into two groups. The first group is the first 8 channels such as lane0 to lane7, and the second group is the last 8 channels such as lane8 to lane15. The detection link 3 of the first x8 is manufactured on the first sub-jig, as shown in Figure 1 and Figure 2 The detection link 3 of the last x8 is manufactured on the second sub-jig, as shown in Figure 3 and Figure 4 Such specification division reduces the number of detection links 3 on each jig, which is beneficial to the miniaturization of the jig.

[0046] In order to enable the first sub-jig and the second sub-jig to be electrically connected with the PCIe slot, the connection interface 2 on the circuit board 1 of each sub-jig is of x16 specification. In order to ensure that the signals of the first x8 are normally connected when the first sub-jig is inserted into the PCIe slot, the interface corresponding to the last x8 on the first sub-jig is connected with an auxiliary link 4, as shown in Figure 1 and Figure 2 Similarly, in order to ensure that the signals of the last x8 are normally connected when the second sub-jig is inserted into the PCIe slot, the interface corresponding to the first x8 on the second sub-jig is connected with an auxiliary link 4, as shown in Figure 3 and Figure 4 .

[0047] One detection link 3 corresponds to one signal channel. One auxiliary link 4 corresponds to one signal channel. In some embodiments, the PCIe jig provided by the embodiment of the application includes two sub-jigs, each of which has 8 detection links 3 and 8 auxiliary links 4, respectively, corresponding to 16 signal channels of the interface of the device to be detected. In other embodiments, the PCIe jig provided by the embodiment of the application includes four sub-jigs, each of which has 4 detection links 3 and 4 auxiliary links 4, respectively, corresponding to 16 signal channels of the interface of the device to be detected. In other embodiments, the PCIe jig provided by the embodiment of the application includes eight sub-jigs, each of which has 2 detection links 3 and 2 auxiliary links 4, respectively, corresponding to 16 signal channels of the interface of the device to be detected.

[0048] It can be understood that the PCIe jig provided by the embodiments of the present application is not limited to the above-mentioned several channel separation specifications, and different forms of channel separation specifications can be selected to further realize the planning of the device to meet the miniaturization demand of the jig.

[0049] In some embodiments, as shown in Figures 1 to 4 The detection link 3 includes an input end connector 31, a first wire 32, an output end connector 33 and a second wire 34; the circuit board 1 includes a first face A and a second face 1B arranged oppositely; the input end connector 31 and the first wire 32 are arranged on the first face A, and the output end connector 33 and the second wire 34 are arranged on the second face 1B.

[0050] The signal detection interface connected with the detection link 3 includes two detection terminals, and the two detection terminals are arranged on the first face A and the second face 1B, respectively.

[0051] The input end connector 31 of the detection link 3 and the first wire 32 are electrically connected with the detection terminal on the first face A, and the output end connector 33 and the second wire 34 are electrically connected with the detection terminal on the second face 1B.

[0052] The input end connector 31 and the first wire 32 of each detection link 3 of the sub-jig are arranged on the first face A of the circuit board 1, and the output end connector 33 and the second wire 34 are arranged on the second face 1B of the circuit board 1. The first wire 32 is electrically connected with the detection terminal on the first face A, and the second wire 34 is electrically connected with the detection terminal on the second face 1B. Arranging the input end connector 31 and the output end connector 33 on the two opposite faces of the circuit board 1 can improve the utilization rate of the limited area of the jig.

[0053] As shown in Figure 1 and Figure 2 The sub-jig includes eight detection links 3 and eight auxiliary links 4, which are used to detect the first x8 signal channels of the PCIe slot. Each detection link 3 includes an input end connector 31, a first wire 32, an output end connector 33 and a second wire 34. The first wire 32 connects the input end connector 31 and a detection terminal of the connection interface 2, and the second wire 34 connects another detection terminal of the output end connector 33. The sub-jig replaces the original detection link 3 with the auxiliary link 4 connected with the rear x8 signal channels, so that the number of connectors on the jig is reduced, and the length of the corresponding wire can also be reduced.

[0054] As shown in Figure 3 and Figure 4As shown, the sub-fixture includes eight detection links 3 and eight auxiliary links 4 for detecting the x8 signal channels behind the PCIe slot. Each detection link 3 includes an input connector 31, a first trace 32, an output connector 33, and a second trace 34. The first trace 32 connects the input connector 31 to a detection terminal of the connection interface 2, and the second trace 34 connects to another detection terminal of the output connector 33. The sub-fixture replaces the original detection links 3 with auxiliary links 4 connected to the previous x8 signal channels, thus reducing the number of connectors on the fixture and correspondingly shortening the trace length.

[0055] The PCIe fixture provided in this application embodiment uses a channel separation design, which helps to reduce the number of components required in each sub-fixture, thereby facilitating fixture miniaturization.

[0056] In some embodiments, the input connector 31 and / or the output connector 33 are SMP connectors. An SMP connector is a high-frequency coaxial connector; it is small in size and lightweight, making it suitable for space-constrained applications.

[0057] The PCIe fixture provided in this application uses SMP connectors for wiring connections. Compared to SMA connectors (SubMiniature Type A connectors), SMP connectors are easier to disassemble during testing, occupy less space on the fixture, improve the utilization rate of the limited area on the fixture, and further reduce the size of the PCIe fixture.

[0058] In some embodiments, a number of input connectors 31 are arranged in a fan shape around the connection interface 2 on the first surface A;

[0059] The b output connectors 33 are arranged in a fan shape around the connection interface 2 on the second side 1B. The fan-shaped arrangement of the connectors allows for a reasonable spatial layout and miniaturization, while also facilitating the drawing of signal lines with equal lengths.

[0060] like Figures 1 to 4 As shown, all input connectors 31 in the sub-jig adopt a fan-shaped layout, which makes the length of all first traces 32 more even, which is more conducive to drawing the first traces 32 with equal lengths while maximizing space utilization. Similarly, all output connectors 33 adopt a fan-shaped layout, which makes the length of all second traces 34 more even, which is more conducive to drawing the second traces 34 with equal lengths while maximizing space utilization.

[0061] In some embodiments, the distance from the input connector 31 to the first edge of the circuit board 1 is not equal to the distance from the output connector 33 to the first edge of the circuit board 1, wherein the first edge is the edge of the circuit board 1 close to the connection interface 2. It can be understood that the fan-shaped radius of the input connector 31 fan-shaped distributed on the first surface A is not equal to the fan-shaped radius of the output connector 33 fan-shaped distributed on the second surface 1B. For example, the fan-shaped radius of the input connector 31 is greater than the fan-shaped radius of the output connector 33; or, the fan-shaped radius of the output connector 33 is greater than the fan-shaped radius of the input connector 31. The orthographic projection of the input connector 31 on the circuit board 1 and the orthographic projection of the output connector 33 on the circuit board 1 do not overlap, which facilitates the layout of the connector and facilitates disassembly during the test process.

[0062] In some embodiments, the first trace 32 and the second trace 34 are both single-ended signal traces. Using single-ended signal traces instead of differential signal traces ensures that the single-ended signal impedance is controlled at 42.5Ω under the condition that the differential impedance is controlled at 85Ω, and the single-ended trace design is relatively simple and easy to wire in a limited space.

[0063] In some embodiments, the auxiliary link 4 includes a first termination resistor 41 and a second termination resistor 42; the first termination resistor 41 is fixedly arranged on the first surface A, and the second termination resistor 42 is fixedly arranged on the second surface 1B.

[0064] In the one-to-one corresponding connection of the auxiliary link 4 and the signal detection interface, the first termination resistor 41 is electrically connected with the detection terminal on the first surface A, and the second termination resistor 42 is electrically connected with the detection terminal on the second surface 1B.

[0065] As shown in Figures 1 to 4 , the PCIe jig provided by the embodiments of the present application terminates the signal channels not used by the connection interface 2 in the sub-jig through the termination resistors, so as to ensure the normal connection of other channel signals. For example, the resistance values of the first termination resistor 41 and the second termination resistor 42 are 50Ω.

[0066] The first termination resistor 41 is connected with the detection terminal on the first surface A through the third trace 43, and the second termination resistor 42 is connected with the detection terminal on the second surface 1B through the fourth trace 44. As shown in Figure 1 , the length of the first trace 32 is greater than the length of the third trace 43; as shown in Figure 2 , the length of the second trace 34 is greater than the length of the fourth trace 44.

[0067] In some embodiments, the connection interface 2 is a gold finger, and the corresponding detection terminal is a signal pin 21.

[0068] As shown in Figure 2 and Figure 5As shown, the connection interface 2 includes multiple pins arranged along the X direction. The input connector 31, output connector 33, first terminating resistor 41, and second terminating resistor 42 are all located above the pins, i.e., on the +Y side. The input connector 31 is connected to a signal pin 21 on the first surface A via the first trace 32. The output connector 33 is connected to a signal pin 21 on the second surface 1B via the second trace 34. The first terminating resistor 41 is connected to a signal pin 21 on the first surface A via the third trace 43. The second terminating resistor 42 is connected to a signal pin 21 on the second surface 1B via the fourth trace 44.

[0069] The sub-fixture can be electrically connected to the device under test via the gold fingers on circuit board 1. Taking a PCIe slot as an example, circuit board 1 is inserted into the PCIe slot via the gold fingers. Gold fingers have advantages such as reliable electrical contact, high durability, good conductivity, ease of processing, strong compatibility, and ease of maintenance and replacement.

[0070] In some embodiments, such as Figure 5 As shown, circuit board 1 also includes a ground hole 10, which is located on one side of the first trace 32 or the second trace 34 in the gold finger departure detection link 3. The ground hole 10 is located on the side of the gold finger away from the output end to avoid manufacturing risks.

[0071] Considering the close proximity of the pins on the jig's gold finger end, if a ground hole 10 is drilled at the output end of signal pin 21, the distance between ground hole 10 and the trace, as well as between ground holes 10 themselves, is too close, posing a manufacturing risk. For example... Figure 5 As shown, and refer to Figure 2 In this embodiment, the signal pin 21 on the sub-fixture does not have a ground hole 10 at its output end. The ground holes 10 are all located on the side of the pin away from the output end to ensure a safe process distance between ground holes 10 and between ground holes 10 and the trace. Here, the output end can be understood as the connection end of the signal line to the pin. The signal line includes the first trace 32 and the second trace 34.

[0072] In some embodiments, such as Figure 6 As shown, the circuit board 1 includes a first signal layer 11, a second signal layer 12, and a ground layer 13 located between the first signal layer 11 and the second signal layer 12; a first trace 32 is laid on the first signal layer 11, and a second trace 34 is laid on the second signal layer 12; the ground layer 13 has four layers.

[0073] like Figure 6 As shown, the circuit board 1 in the fixture adopts a six-layer board design, with signal lines routed on the top and bottom layers, and the middle four layers serving as ground, minimizing costs while ensuring a complete reference ground for the traces. For the board material, extremely low-loss materials such as NY6300S are selected to ensure the lowest possible signal attenuation while the signal lines are routed on the top layers.

[0074] The PCIe jig provided by the embodiments of the present application reduces the prompt module irrelevant to signal performance, such as indicator light, and only retains the module relevant to signal performance. The size of the sub-jig is reduced by nearly half in the Y direction compared with the size of the existing jig, as shown in the figure. For example, the final size of the sub-jig is 162.56mm*68mm. Figures 1 to 4

[0075] The PCIe jig provided by the embodiments of the present application can realize high-speed PCIe signal integrity test of PCIe X16 slot in some space-limited whole-machine environment, and the size of the PCIe jig is reduced by nearly half compared with the size of the PCIe Association standard CLB (Compliance Load Board) jig, thereby effectively improving the possibility of testing PCIe X16 slot signal of the jig in the whole-machine environment.

[0076] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.​

Claims

1. A PCIe fixture, characterized in that, include: At least two sub-jibs; Each of the sub-fixtures includes a circuit board, the circuit board including a connection interface for electrical connection with the device under test; the connection interface includes m signal detection interfaces; The circuit board includes a detection links and b auxiliary links, and the a detection links and the b auxiliary links are connected one-to-one with the m signal detection interfaces; where a, b, and m are all positive integers, and m = a + b.

2. The PCIe fixture according to claim 1, characterized in that, The detection link includes an input connector, a first trace, an output connector, and a second trace; the circuit board includes a first side and a second side arranged opposite to each other; the input connector and the first trace are both arranged on the first side, and the output connector and the second trace are both arranged on the second side; The signal detection interface connected to the detection link includes two detection terminals, which are respectively disposed on the first surface and the second surface; In the one-to-one connection of the detection link and the signal detection interface, the input connector is electrically connected to the detection terminal on the first side through the first trace, and the output connector is electrically connected to the detection terminal on the second side through the second trace.

3. The PCIe fixture according to claim 2, characterized in that, The input connector and / or the output connector are SMP connectors.

4. The PCIe fixture according to claim 2, characterized in that, The input connectors are arranged in a fan shape around the connection interface on the first surface; b of the output connectors are arranged in a fan shape around the connection interface on the second surface.

5. The PCIe fixture according to claim 4, characterized in that, The distance from the input connector to the first edge of the circuit board is not equal to the distance from the output connector to the first edge of the circuit board; The first edge is the edge of the circuit board near the connection interface.

6. The PCIe fixture according to claim 2, characterized in that, Both the first and second traces are single-ended signal traces.

7. The PCIe fixture according to claim 2, characterized in that, The auxiliary link includes a first terminating resistor and a second terminating resistor; the first terminating resistor is fixed to the first surface, and the second terminating resistor is fixed to the second surface; In the one-to-one connection of the auxiliary link and the signal detection interface, the first terminating resistor is electrically connected to the detection terminal on the first surface, and the second terminating resistor is electrically connected to the detection terminal on the second surface.

8. The PCIe fixture according to claim 2, characterized in that, The connection interface is a gold finger.

9. The PCIe fixture according to claim 8, characterized in that, The circuit board also includes a ground hole, which is located on the side of the gold finger away from the first or second trace in the detection link.

10. The PCIe fixture according to claim 2, characterized in that, The circuit board includes a first signal layer, a second signal layer, and a ground layer located between the first signal layer and the second signal layer; the first trace is routed on the first signal layer, and the second trace is routed on the second signal layer; the ground layer has four layers.

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