EFuse controller
Through state machine design and software-configurable registers, the eFuse controller achieves flexible read/write timing at different frequencies, solving the adaptability and reliability issues of existing eFuse controllers in different application scenarios, and enhancing data security and operational flexibility.
Patent Information
- Application Number
- CN202423213936.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2034-12-25
AI Technical Summary
Existing eFuse controllers are limited in their flexibility and reliability across different application scenarios, mainly due to fixed read/write timing and frequency adaptability issues, which affect their adaptability and performance across different SoC systems.
It adopts a state machine design, software-configurable registers, and multiple operating modes. Through programmable operation timing, it can adapt to read and write requirements at different frequencies, thereby enhancing security and flexibility.
It enables read/write timing of eFuse to adapt to different operating frequencies, improves data security and controller adaptability, expands operating modes, and enhances the flexibility and reliability of eFuse controller.
Smart Images
Figure CN223598227U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the technical field of semiconductor devices, especially relates to an eFuse controller. BACKGROUND
[0002] With the continuous development of integrated circuit technology, electronic fuse (eFuse) as a kind of key nonvolatile memory device, plays an increasingly important role in chip design.EFuse, the full name of electronic fuse, is a programmable electronic fuse, and is a kind of nonvolatile memory device for storing information and protecting chip.EFuse (eFuse) is mainly used for storing key configuration information, realizing hardware security characteristics and providing circuit protection functions.eFuse controller is used to manage and control eFuse device.
[0003] However, the eFuse controller design in the prior art has some technical problems, which limits the flexibility and reliability of eFuse in different application scenarios.
[0004] 1. Read-write timing fixedness problem: the read-write time of existing eFuse array is fixed, which limits its adaptability in different application scenarios to some extent. Since the read-write operation of eFuse array involves electron injection and thermal effect process, these operations need accurate time control, and the existing design fails to provide sufficient flexibility to adapt to different read-write requirements.
[0005] 2. Frequency adaptability problem: eFuse controller is usually connected with bus, and the frequency of bus may change due to different SoC systems. The existing controller fails to fully consider the read-write timing requirements under different frequency conditions, which may lead to the failure to meet the read-write timing requirements of eFuse under certain frequency, affecting the performance and reliability of the device. INVENTION CONTENTS
[0006] In order to solve the problems in the related art, the present application provides an eFuse electronic fuse controller, which can support multiple operation modes by adopting state machine design and software configurable register, has programmable operation timing and enhances safety.
[0007] The technical scheme is as follows:
[0008] An eFuse electronic fuse controller, comprising,
[0009] eFuse register module, for storing the operation mode and state information of eFuse;
[0010] an eFuse bus interface, configured to be communicatively connected with a bus, receive commands and data from the bus, and send to the eFuse register module;
[0011] an eFuse read-write module, configured to perform write or read operation on the eFuse register module, and
[0012] an eFuse timing encapsulation module, configured to encapsulate operation and timing signals generated by the eFuse read-write module into independent read timing, write timing and non-active state timing; the eFuse timing encapsulation module is communicatively connected with the eFuse physical module, and sends operation and timing signals generated by the eFuse read-write module to the eFuse physical module.
[0013] Further, the eFuse read-write module comprises,
[0014] an eFuse read module, configured to read current stored information from the eFuse register module;
[0015] an eFuse write module, configured to perform write operation on the eFuse register module.
[0016] Further, the eFuse register module comprises a control register, an access mode register and a timing state control register.
[0017] Further, the control register is configured to control start and stop of the eFuse register module.
[0018] Further, the access mode register is configured to configure eFuse operation mode and address data.
[0019] Further, in the eFuse controller read operation timing, the state machine comprises an idle state, a read mode state, an address update state and an address stable state.
[0020] Further, the eFuse controller is configured to control eFuse operation mode, and the eFuse operation mode comprises a programming mode, a read mode and a non-active mode.
[0021] The technical scheme at least has the following technical effects:
[0022] 1. According to the timing requirements of eFuse, at different working frequencies, the eFuse controller register is operated by software, the controller sends operation matching the eFuse read-write timing to perform eFuse read-write, which can adapt to different working frequencies and different eFuse.
[0023] 2. The data security is enhanced, and the security control register is used to prevent illegal reading.
[0024] 3. The operating mode is extended, including an inactive state mode, and the adaptability and flexibility of the controller are improved. BRIEF DESCRIPTION OF DRAWINGS
[0025] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.
[0026] Figure 1 A structure diagram of an eFuse controller provided for a preferred embodiment of the present application is shown in the figure.
[0027] Figure 2 A structure diagram of an eFuse controller provided for a preferred embodiment of the present application is shown in the figure.
[0028] Figure 3 An eFuse read operation diagram of the eFuse controller is shown in the figure.
[0029] Figure 4 An eFuse write operation diagram of the eFuse controller is shown in the figure.
[0030] Figure 5 A timing state machine flow chart of the eFuse controller is shown in the figure. DETAILED DESCRIPTION
[0031] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is presented in the context of the drawings, where the same numbers represent the same or similar elements throughout the several views. The implementations described in the following exemplary embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.
[0032] As shown in the accompanying Figure 1 The present application provides an eFuse controller, which is used for managing and controlling an eFuse device. The eFuse controller can accurately control the fusing process of the eFuse, and can also monitor the state of the eFuse. The function of the eFuse controller is to accurately control the timing signal of programming, to ensure that the eFuse is fused according to the design requirements, or to read out the current state of the eFuse.
[0033] As shown in the accompanying Figure 1 The component structure of the eFuse controller includes an eFuse register module, an eFuse bus interface, an eFuse read-write module, an eFuse timing encapsulation module, and an eFuse physical module.
[0034] The eFuse bus interface is responsible for communicating with the bus, receiving commands and data from the bus, configuring eFuse control registers, and transmitting eFuse status and data back.
[0035] The eFuse register module is used for writing to or reading from the eFuse register module.
[0036] The eFuse read / write module generates eFuse read / write operations and timing sequences based on the configuration of the control registers, and sends them to the eFuse physical module through the eFuse timing encapsulation module. The eFuse read / write module includes an eFuse read module and an eFuse write module; the eFuse read module reads currently stored information from the eFuse register module; the eFuse write module performs write operations on the eFuse register module. Preferably, the eFuse timing encapsulation module is an eFuse wrapper.
[0037] The eFuse timing encapsulation module communicates with the eFuse read module and the eFuse write module respectively, encapsulating the operations and timing signals generated by the eFuse read and write modules into independent read timing, write timing, and inactive state timing; the eFuse timing encapsulation module communicates with the eFuse physical module, sending the operations and timing generated by the eFuse read and write modules to the eFuse physical module.
[0038] like Figure 2 As shown, in a preferred embodiment of the eFuse controller, the eFuse module is an eFuse storage array with a capacity of 4Kbit. It should be noted that write operations are performed in units of bits, supporting the writing of 1 or more bits; read operations are performed in units of bytes, supporting the reading of 1 or more bytes. Furthermore, to prevent illegal reading of the eFuse memory contents, this embodiment incorporates a set of write-only registers. The values of these registers cannot be read by software, ensuring the security of the data within the eFuse.
[0039] In existing technologies, due to the relatively long read / write times of eFuse arrays, eFuse controllers are typically connected to the APB bus. While the read / write time of the eFuse array is fixed, the controller needs to meet the eFuse read / write requirements under different frequency conditions, depending on the SoC system and the APB bus frequency. In this embodiment, to ensure controller flexibility, software-configurable registers are used in the controller to set the eFuse read / write timing. The eFuse read / write state machine, based on different timing conditions and the software-set read / write timing, implements transitions between different stages of the read / write timing, and sends these transitions to a packager to be encapsulated into independent read timing, write timing, and inactive state timing.
[0040] The eFuse controller in the embodiment is a controller module for the eFuse memory of a 28nm process of a certain wafer foundry in China, and mainly completes the read and programming operations of the eFuse memory. The basic functions are as follows:
[0041] 1. Support eFuse memory capacity: 4Kbit;
[0042] 2. Support three memory operation modes of Inactive, Program and Read: the Program mode supports 1 or multi-bit operation; the Read mode supports 1 or multi-Byte operation; the default mode of the controller is the Inactive mode.
[0043] 3. Operation timing is programmable, meeting all timing requirements of the eFuse memory;
[0044] 4. Support the security function of prohibiting access to the eFuse memory by setting a write-only one-way register;
[0045] 5. In the DFT test mode, bypass the eFuse memory; both the programming and read operations have no FIFO; both the programming of 1 bit and the read of 1 Byte adopt the polling mode.
[0046] The eFuse controller IP is entirely designed by Verilog code and can be conveniently synthesized into a digital logic circuit.
[0047] The eFuse controller is used to control the eFuse operation mode and manage data. The eFuse has three operation modes, specifically: the Program mode, the Read mode and the Inactive mode. The selection of the three modes of the eFuse module is determined by the logic levels of the read selection information (RDEN) and the program selection (PGMEN).
[0048] The eFuse controller performs the eFuse operation according to the following timing, the eFuse Read timing (as shown in Figure 3 ), the eFuse Program timing (as shown in Figure 4 ) and the eFuse Inactive state.
[0049] The Inactive state of the eFuse refers to the state of neither being in the read mode nor in the write mode. In this mode, the states of the signals are as follows: AEN=L; RDEN=L; PGMEN=L; D[7:0] is in the undefined state.
[0050] eFuse controller port signals, as shown in Table 1,
[0051] Table 1 eFuse controller port signal description
[0052] Signal name Bit width Direction Description pck 1 I APB clock preset_n 1 I APB domain reset signal, active low psel 1 I APB select signal penable 1 I APB enable signal pwrite 1 I APB write signal paddr 32 I APB address signal pwdata 32 I APB write data prdata 32 O APB read data dft_test_mode_i 1 I Test mode signal
[0053] The eFuse controller of the present embodiment adopts a state machine design to describe the behavior of each stage of the eFuse controller timing in a clear manner, for implementing how to use the smallest possible cost for eFuse read and write timing. The requirements of the timing are divided into different states, and the transition conditions between the states are clearly defined. For example, in the eFuse read operation timing, the state machine can define an idle state, a read mode state, an address update state, and an address stable state, etc. Through such division, the flow of the working timing can be accurately controlled, and it is ensured that the eFuse timing is generated in the correct order and format. In the eFuse controller read operation timing, the state machine includes an idle state, a read mode state, an address update state, and an address stable state.
[0054] The timing state machine of the eFuse controller as shown in Figure 5
[0055] The key registers of the eFuse controller include a control register, an access mode register, and a timing state control register.
[0056] The control register controls the start and stop of the eFuse register module.
[0057] The access mode register configures the eFuse operation mode, address data, and is used to configure the mode, address, etc. of eFuse access.
[0058] The timing state control register configures the read and write timing of the eFuse, to match the timing during eFuse array read, write, and inactivity, and to ensure that the eFuse controller can send correct read and write timing to the eFuse array under different frequencies of chip operation. The key registers of the eFuse controller are shown in Table 2:
[0059] Table 2 eFuse key register list
[0060]
[0061] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
[0062] It is to be understood that the application is not limited to the precise construction herein disclosed and shown in the drawings, and that various changes can be made to the application without departing from the scope thereof. The scope of the application is limited only by the claims appended hereto.
Claims
1. An eFuse controller, comprising: The eFuse controller comprises: an eFuse register module for storing operation mode and state information of the eFuse; an eFuse bus interface for being communicatively connected with a bus, receiving commands and data from the bus, and sending to the eFuse register module; an eFuse read-write module for performing write or read operation on the eFuse register module; and an eFuse timing encapsulation module for encapsulating operation and timing signals generated by the eFuse read-write module into independent read timing, write timing and non-active state timing, and for sending the operation and timing signals generated by the eFuse read-write module to the eFuse physical module.
2. The eFuse controller of claim 1, wherein, The eFuse read-write module comprises: an eFuse read module for reading current stored information from the eFuse register module; an eFuse write module for performing write operation on the eFuse register module.
3. The eFuse controller of claim 1, wherein, The eFuse register module comprises a control register, an access mode register and a timing state control register.
4. The eFuse controller of claim 3, wherein, The timing state control register is used for configuring read-write timing of the eFuse, so as to match timing during eFuse array read, write and non-active.
5. The eFuse controller of claim 3, wherein, The control register is used for controlling start and stop of the eFuse register module.
6. The eFuse controller of claim 3, wherein, The access mode register is used for configuring eFuse operation mode and address data.
7. The eFuse controller of claim 1, wherein, In the eFuse controller read operation timing, the state machine comprises an idle state, a read mode state, an address update state and an address stable state.
8. The eFuse controller of claim 1, wherein, The eFuse controller is used for controlling operation mode of the eFuse, and the operation mode of the eFuse comprises a programming mode, a read mode and a non-active mode.