Chip stacking packaging structure

Abstract

The utility model provides a chip stacking packaging structure, which comprises a substrate, a silicon carrier plate, an HBM chip and an SOC chip, one side of the substrate is connected with the silicon carrier plate, the silicon carrier plate is provided with a plurality of electrical interconnection through holes, the HBM chip is stacked above the silicon carrier plate, the SOC chip is arranged above the HBM chip, the SOC chip is connected with the HBM chip, and the HBM chip is connected with the substrate through the electrical interconnection through holes; the back face of the SOC chip is arranged upwards, a liquid cooling channel is formed in the back face of the SOC chip, and cooling liquid passes through the liquid cooling channel to cool the SOC chip. According to the utility model, the SOC chip is arranged above the HBM chip, the structure is simple, heat can be conveniently conducted upwards, rapid and efficient heat dissipation is carried out through the liquid cooling channel on the back surface of the SOC chip, the problem of overheating of the SOC chip is avoided, the reliability of the SOC chip is improved, and the service life of the SOC chip is prolonged.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor packaging technology, and specifically relates to a chip stacking packaging structure. Background Technology

[0002] In modern electronic devices, System-on-a-Chip (SoC) and High-Bandwidth Memory (HBM) chips are widely used in various high-performance computing and artificial intelligence applications due to their high performance and efficient data processing capabilities. A SoC integrates an entire information processing system onto a single chip, while a HBM is a new type of CPU / GPU memory chip. Current stacked packaging structures typically involve stacking HBM chips on top of the SoC chip.

[0003] While the functionality and performance of these chips continue to improve, they generate a significant amount of heat during high-load operation. Most of this heat originates from the operation of the SOC chip itself. Because the SOC chip is located in the middle of the package, heat cannot dissipate quickly enough and is prone to buildup, posing a significant challenge to the chip's reliability and lifespan. Therefore, effective heat dissipation has become a crucial issue in the field of thermal management systems.

[0004] Existing heat dissipation solutions primarily rely on fan cooling, where a fan is mounted above the chip to remove heat from its surface using airflow. While this method was sufficient for heat dissipation in the early stages, it has become inadequate as SOC chip performance and power consumption have increased. This traditional method is less efficient, failing to quickly remove large amounts of heat from the chip surface, which can easily lead to overheating and negatively impact chip performance and lifespan.

[0005] Existing heat dissipation solutions also include liquid cooling channels, which require setting up liquid cooling channels in the middle of the entire package, i.e., on the back of the SOC chip. Such packaging structures are complex, have high process requirements, and are costly.

[0006] Therefore, there is an urgent need for a chip stacking packaging structure that can improve heat dissipation performance. Utility Model Content

[0007] The purpose of this invention is to provide a chip stacking packaging structure. By placing the SOC chip on top of the HBM chip and setting a liquid cooling channel on the back of the SOC chip, the structure is simple, can efficiently dissipate heat, improve heat dissipation efficiency, and meet heat dissipation requirements.

[0008] To achieve the above objectives, this utility model provides a chip stacking packaging structure, comprising: a substrate, a silicon carrier, an HBM chip, and a SOC chip. One side of the substrate is connected to the silicon carrier, and the silicon carrier has multiple electrical interconnect vias. The HBM chips are stacked on top of the silicon carrier, and the SOC chip is disposed on top of the HBM chips. The SOC chip and the HBM chips are connected, and the HBM chip is connected to the substrate through the electrical interconnect vias. The back side of the SOC chip faces upward, and a liquid cooling channel is provided on the back side of the SOC chip for coolant to pass through, thereby dissipating heat from the SOC chip.

[0009] Preferably, the liquid cooling channel includes a coolant inlet, a distribution channel, multiple microchannels, a confluence channel, and a coolant outlet. The coolant inlet is connected to the distribution channel and the multiple microchannels, and the coolant outlet is connected to the confluence channel and the multiple microchannels.

[0010] Preferably, the chip stacked packaging structure further includes a molding compound layer disposed on the substrate and covering the liquid cooling channel, the SOC chip, the HBM chip, and the silicon substrate. The coolant inlet and coolant outlet of the liquid cooling channel pass through the molding compound layer.

[0011] Preferably, the substrate edge is provided with annular heat sinks.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] On the one hand, placing the SOC chip above the HBM chip simplifies the structure and facilitates heat conduction upwards. The heat is then dissipated quickly and efficiently through the liquid cooling channel on the back of the SOC chip, avoiding overheating and improving the reliability and lifespan of the SOC chip.

[0014] On the other hand, the size of the liquid cooling channel can be flexibly adjusted according to SOC chips with different power and performance, which improves the versatility and flexibility of the product, as well as the reliability and stability of the package.

[0015] Furthermore, the liquid-cooled microchannel design significantly reduces energy consumption, offering advantages in terms of environmental friendliness and energy saving. Simultaneously, the liquid-cooled microchannel design results in low noise during operation of the heat dissipation system, minimizing its impact on the operating environment. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the chip stacking and packaging structure in this utility model;

[0017] Figure 2 This is a top view of the chip stacking and packaging structure in this utility model;

[0018] Figure 3This is a schematic diagram of the liquid cooling channel in this utility model.

[0019] Reference numerals: 1. Substrate; 2. Silicon substrate; 201. Electrical interconnect via; 3. HBM chip; 4. SOC chip; 401. Conductive bump; 5. Liquid cooling channel; 6. Molding layer; 7. Coolant inlet; 8. Coolant outlet; 9. Annular heat sink; 10. Diverter channel; 11. Multiple microchannels; 12. Converging channel; 13. Bottom filler. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0021] like Figure 1 and Figure 2 As shown, this application discloses a chip stacking packaging structure, which includes: a substrate 1, a silicon carrier 2, an HBM chip 3, and a SOC chip 4.

[0022] The silicon substrate 2 is a silicon wafer on which multiple independent electrical interconnect vias 201 are formed. The silicon substrate 2 is placed between the chip and the substrate 1, and the conductive bumps of the auxiliary chip and the circuit layer of the substrate 1 are electrically connected in the vertical direction.

[0023] In this invention, the SOC chip 4 has conductive bumps 401 on the front side and liquid cooling channels 5 on the back side, with the back side of the SOC chip 4 facing upwards.

[0024] The SOC chip 4 is positioned above the HBM chip 3, and the conductive bumps 401 on the front of the SOC chip 4 are connected to the top of the HBM chip 3. The HBM chip 3 is connected to the circuit layer of the substrate 1 through electrical interconnect vias 201 on the silicon carrier 2. A liquid cooling channel 5 allows coolant to pass through, dissipating heat from the SOC chip 4.

[0025] In this invention, the SOC chip 4 is placed above the HBM chip 3, which is simple in structure and facilitates the upward conduction of heat generated during chip operation. The heat is then quickly and efficiently dissipated through the liquid cooling channel 5 on the back of the SOC chip 4, avoiding the problem of overheating of the SOC chip 4 and improving the reliability and lifespan of the SOC chip 4.

[0026] The silicon carrier 2 and the substrate 1 are connected by solder balls, and then filled with bottom filler 13 to enhance the mechanical strength and stability of the chip packaging structure.

[0027] The chip stacked packaging structure also includes a molding compound 6, which is disposed on the substrate 1 and covers the liquid cooling channel 5, the SOC chip 4, the HBM chip 3, and the silicon carrier 2. The coolant inlet 7 and coolant outlet 8 of the liquid cooling channel 5 pass through the molding compound 6 and are connected to external cooling pipes (not shown in the figure).

[0028] A ring-shaped heat sink 9 is provided around the edge of the substrate 1. The ring-shaped heat sink 9 is fixed to the edge of the substrate 1 with adhesive. When the encapsulation structure is working, some of the heat generated will be conducted to the substrate 1, and the heat on the substrate 1 can be conducted away through the ring-shaped heat sink 9.

[0029] In this invention, the liquid cooling channel 5 can be either a transverse channel or a longitudinal channel. Liquid cooling channel 5 structures in other directions, without departing from the concept of this invention, should also fall within the scope of protection of this invention. This invention will be described using a transverse channel as an example.

[0030] Specific examples Figure 3 As shown, the liquid cooling channel 5 includes a coolant inlet 7, a distribution channel 10, multiple microchannels 11, a confluence channel 12, and a coolant outlet 8. The coolant inlet 7 is connected to the multiple microchannels 11 via the distribution channel 10, and the coolant outlet 8 is connected to the multiple microchannels 11 via the confluence channel 12. When the package structure requires heat dissipation, the external cooling pipeline is activated. The coolant enters the distribution channel 10 from the coolant inlet 7 and then flows into the multiple microchannels 11; afterwards, it flows out through the confluence channel 12 to the coolant outlet 8. The multiple microchannels 11 allow for rapid and efficient heat dissipation from the SOC chip. Simultaneously, the liquid-cooled microchannels 11 result in low noise during operation, minimizing environmental impact. Furthermore, the liquid-cooled microchannels 11 significantly reduce energy consumption, offering advantages in environmental protection and energy saving.

[0031] The liquid cooling channel 5 is located on the back of the SOC chip 4, and its size can be flexibly adjusted according to the different power and performance of the SOC chip 4. The number of microchannels 11 can also be increased or decreased, which improves the versatility and flexibility of the product, as well as the reliability and stability of the package. In the existing technology, the SOC chip 4 is located in the middle of the entire package structure. Adjusting the size of the liquid cooling channel 5 would inevitably increase the process difficulty, increase costs, and reduce efficiency.

[0032] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A chip stacking packaging structure, characterized in that, The system includes a substrate, a silicon carrier, an HBM chip, and a SOC chip. The substrate is connected to the silicon carrier on one side and has multiple electrical interconnect vias. The HBM chips are stacked on top of the silicon carrier, and the SOC chip is disposed on top of the HBM chips. The SOC chip and the HBM chips are connected, and the HBM chip is connected to the substrate through the electrical interconnect vias. The back side of the SOC chip faces upward, and a liquid cooling channel is provided on the back side of the SOC chip for cooling liquid to pass through and dissipate heat from the SOC chip.

2. The chip stacking packaging structure according to claim 1, characterized in that, The liquid cooling channel includes a coolant inlet, a distribution channel, multiple microchannels, a confluence channel, and a coolant outlet. The coolant inlet is connected to the distribution channel and multiple microchannels, and the coolant outlet is connected to the confluence channel and multiple microchannels.

3. The chip stacking packaging structure according to claim 2, characterized in that, It also includes a molding compound layer, which is disposed on the substrate and covers the liquid cooling channel, the SOC chip, the HBM chip and the silicon substrate. The coolant inlet and coolant outlet of the liquid cooling channel pass through the molding compound layer.

4. The chip stacking packaging structure according to claim 3, characterized in that, The substrate has an annular heat sink at its edge.

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