Signal transmission circuit, QEP module and micro-processing chip

Abstract

The embodiment of the utility model provides a signal transmission circuit, a QEP module and a micro-processing chip. A first input end of a first comparison module receives a first signal, a second input end of the first comparison module receives a first reference voltage, a positive side power supply end of the first comparison module is externally connected with a second reference voltage, and a negative side power supply end of the first comparison module is externally connected with a third reference voltage; the first input end of the second comparison module is electrically connected with the output end of the first comparison module, and the second input end is externally connected with a first reference voltage; the positive-side power supply end is externally connected with a first power supply, and the negative-side power supply end is electrically connected with the grounding end; the first input end of the third comparison module receives the first signal, the second input end is electrically connected with the output end of the first comparison module, the positive-side power end is externally connected with a second power supply, and the negative-side power end is electrically connected with the grounding end; the first comparison module generates a second signal based on the first signal and a first reference voltage. The second comparison module generates a first output signal based on the second signal and a first reference voltage. The third comparison module generates a second output signal based on the second signal and the first signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a signal transmission circuit, a QEP module and a micro-processing chip. BACKGROUND

[0002] An encoder is a sensor that can convert physical motion into electrical signal output, and is usually used to measure information such as position, speed, direction and acceleration of a rotor. The encoder is usually composed of a photoelectric sensor and a logic circuit, and can measure the state of the motor in a non-contact manner and output it as a digital signal. Encoder counting is the counting of the encoder output signal and the conversion of the same into a digital signal, which is used to measure the accuracy of the motor position, angle or speed. Encoder counting has been widely used in industrial production, robots, electric vehicles and other fields. By counting the output of the encoder, the position, angle or speed of the motor can be accurately measured, and the running state of the motor can be controlled, thereby realizing automatic control and precise positioning.

[0003] In some technologies, the instruction input form of the encoder is mainly divided into pulse signals and direction information or double pulse signals. For example, when inputting double pulse signals, the increase or decrease of counting and the rotation direction can be determined according to the high and low levels of the two pulse signals and the rising or falling of the active edge, as shown in Figure 1 For example, in Figure 1 , when counting on TI1 and TI2, when the TI1FP1 signal is a rising edge and the relative signal TI2FP2 signal is a high level state, it is counted downward. If the TI2FP2 signal is a rising edge and the relative signal TI1FP1 signal is a high level state, it is counted upward.

[0004] In the above counting process, the pulse counting information and direction information of the double pulse signals can be determined, and usually two signal lines are needed to transmit the double pulse signals. In some cases where the external pin resources are scarce or in some miniaturized scenarios, such as micro-joints or micro-robots, this method is not applicable. UTILITY MODEL CONTENT

[0005] Therefore, the present application provides a signal transmission circuit, a QEP module and a micro-processing chip to solve the problem that two pulse signals are needed to realize pulse counting and direction information determination in the prior art.

[0006] In a first aspect, the embodiments of the present application provide a signal transmission circuit, comprising: a first comparison module, a second comparison module and a third comparison module; wherein a first input end of the first comparison module is configured to receive a first signal, a second input end of the first comparison module is configured to be externally connected to a first reference voltage, a positive power supply end of the first comparison module is configured to be externally connected to a second reference voltage, and a negative power supply end of the first comparison module is configured to be externally connected to a third reference voltage; the first reference voltage, the second reference voltage and the third reference voltage are all different;

[0007] A first input end of the second comparison module is electrically connected to an output end of the first comparison module, and a second input end of the second comparison module is configured to be externally connected to the first reference voltage; a positive power supply end of the second comparison module is configured to be externally connected to a first power supply, and a negative power supply end of the second comparison module is electrically connected to a ground end;

[0008] A first input end of the third comparison module is configured to receive the first signal, and a second input end of the third comparison module is electrically connected to the output end of the first comparison module; a positive power supply end of the third comparison module is configured to be externally connected to a second power supply, and a negative power supply end of the third comparison module is electrically connected to the ground end;

[0009] The first comparison module is configured to generate a second signal based on the first signal and the first reference voltage;

[0010] The second comparison module is configured to generate a first output signal based on the second signal and the first reference voltage;

[0011] The third comparison module is configured to generate a second output signal based on the second signal and the first signal; the first output signal and the second output signal are different in phase.

[0012] Meanwhile, the first output signal and the second output signal both pass through two groups of level comparators, and the delay relative to a given signal is basically consistent, so that the phase delay phenomenon of the two signals can be avoided.

[0013] In a possible implementation manner of the first aspect, the signal transmission circuit further comprises: a first resistor, a second resistor and a third resistor;

[0014] One end of the first resistor is electrically connected to the positive power supply end of the first comparison module, and the other end of the first resistor is electrically connected to the output end of the first comparison module;

[0015] One end of the second resistor is electrically connected to the positive power supply end of the second comparison module, and the other end of the second resistor is electrically connected to the output end of the second comparison module;

[0016] One end of the third resistor is electrically connected to a positive power supply end of the third comparison module, and the other end of the third resistor is electrically connected to an output end of the third comparison module.

[0017] In a possible implementation manner of the first aspect, the voltage value of the first signal is different from the voltage values of the first reference voltage, the second reference voltage and the third reference voltage.

[0018] In a possible implementation manner of the first aspect, the first signal includes at least two of a first level signal, a second level signal, a third level signal and a fourth level signal, and the first level signal, the second level signal, the third level signal and the fourth level signal are different from each other.

[0019] In a possible implementation manner of the first aspect, the voltage value of the first power supply is the same as the voltage value of the second power supply.

[0020] In a possible implementation manner of the first aspect, the encoder interface counting circuit is further configured to:

[0021] The output end of the second comparison module is electrically connected to a first end of the encoder interface counting circuit, and the output end of the third comparison module is electrically connected to a second end of the encoder interface counting circuit.

[0022] The encoder interface counting circuit is configured to count pulse signals and / or determine the direction of pulse signals according to a first output signal output by the second comparison module and a second output signal output by the third comparison module.

[0023] In a possible implementation manner of the first aspect, the encoder interface counting circuit includes: the filter and edge detector, an encoder interface, a pre-frequency divider, a counter.

[0024] The first end of the filter and edge detector is electrically connected to the output end of the second comparison module, and the second end of the filter and edge detector is electrically connected to the output end of the third comparison module.

[0025] The first interface of the encoder interface is electrically connected to the first output end of the filter and edge detector, and the second interface of the encoder interface is electrically connected to the second output end of the filter and edge detector; the input end of the pre-frequency divider is electrically connected to the output end of the encoder interface, and the output end of the pre-frequency divider is electrically connected to the input end of the counter.

[0026] The filter and edge detector are configured to filter an input signal and capture the edge position of the input signal.

[0027] The encoder interface is configured to control a counting clock of the counter through the pre-divider and control counting of the counter according to the first output signal and the second output signal.

[0028] In a second aspect, the embodiments of the present application provide a QEP module, comprising the signal transmission circuit according to any one of the first aspect.

[0029] In a possible implementation manner of the second aspect, the QEP module further comprises a programmable input unit, a quadrature encoder unit and a position counting control unit, wherein

[0030] The first end of the programmable input unit is electrically connected with the first output end of the signal transmission circuit, the second end of the programmable input unit is electrically connected with the second output end of the signal transmission circuit, the output end of the programmable input unit is electrically connected with the input end of the quadrature encoder unit, and the output end of the quadrature encoder unit is electrically connected with the position counting control unit.

[0031] The programmable input unit is configured to receive the first output signal and the second output signal output by the signal transmission circuit, and convert the first output signal and the second output signal into a first encoded signal and a second encoded signal, and transmit the first encoded signal and the second encoded signal to the quadrature encoder unit.

[0032] The quadrature encoder unit is configured to determine the sequence between the first encoded signal and the second encoded signal, and determine the rotation direction of the encoder and control the counting of the position counting control unit according to the sequence between the first encoded signal and the second encoded signal.

[0033] In a third aspect, the embodiments of the present application provide a micro processing chip, comprising the signal transmission circuit according to any one of the first aspect, or comprising the QEP module according to any one of the second aspect.

[0034] The scheme provided in the embodiment of the application is used, the signal transmission circuit includes a first comparison module, a second comparison module and a third comparison module. The first input end of the first comparison module is used to receive a first signal, the second input end of the first comparison module is used to externally connect a first reference voltage, the positive side power supply end of the first comparison module is used to externally connect a second reference voltage, and the negative side power supply end of the first comparison module is used to externally connect a third reference voltage. The first reference voltage, the second reference voltage and the third reference voltage are all different. The first input end of the second comparison module is electrically connected with the output end of the first comparison module, and the second input end of the second comparison module is used to externally connect the first reference voltage. The positive side power supply end of the second comparison module is used to externally connect a first power supply, and the negative side power supply end of the first comparison module is electrically connected with a ground end. The first input end of the third comparison module is used to receive the first signal, and the second input end of the third comparison module is electrically connected with the output end of the first comparison module. The positive side power supply end of the third comparison module is used to externally connect a second power supply, and the negative side power supply end of the first comparison module is electrically connected with the ground end. The first comparison module is used to generate a second signal based on the first signal and the first reference voltage. The second comparison module is used to generate a first output signal based on the second signal and the first reference voltage. The third comparison module is used to generate a second output signal based on the second signal and the first signal. The phases of the first output signal and the second output signal are different. In this way, in the embodiment of the application, only the first signal can be received, and the received first signal is converted into the first output signal and the second output signal through the first comparison module, the second comparison module and the third comparison module, so that pulse counting and direction information determination are performed according to the first output signal and the second output signal. That is, the first signal is received through one signal line, which can save the signal line input by the instruction end, and can realize the function of transmitting two-way information through one-way signal transmission, so that the application scenarios of pulse counting and direction information determination are more extensive. Moreover, the first signal is decomposed into the first output signal and the second output signal through the first comparison module, the second comparison module and the third comparison module, which can reduce the possibility of relative delay between the first output signal and the second output signal, and improve the accuracy of pulse counting and direction information determination. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0036] Figure 1 A scene schematic diagram of pulse signal counting in the prior art;

[0037] Figure 2 A structure schematic diagram of a signal transmission circuit provided in the embodiment of the application;

[0038] Figure 3 Another structural schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 6;

[0039] Figure 4 Another structural schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 6;

[0040] Figure 5 Another structural schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 6;

[0041] Figure 6 A scene schematic view of a first signal provided by an embodiment of the present application is shown in FIG. 7;

[0042] Figure 7a A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0043] Figure 7b A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0044] Figure 7c A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0045] Figure 7d A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0046] Figure 8a A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0047] Figure 8b A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0048] Figure 8c A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0049] Figure 8d A scene schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 8;

[0050] Figure 9 Another structural schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 6;

[0051] Figure 10 Another structural schematic view of a signal transmission circuit provided by an embodiment of the present application is shown in FIG. 6;

[0052] Figure 11a A scene schematic diagram of two phase relations of a first output signal and a second output signal provided for an embodiment of the present application is provided.

[0053] Figure 11b Another scene schematic diagram of two phase relations of a first output signal and a second output signal provided for an embodiment of the present application is provided.

[0054] Figure 12 A scene schematic diagram of relations between two encoder rotation directions and a first output signal and a second output signal provided for an embodiment of the present application is provided.

[0055] Figure 13 A structure schematic diagram of a QEP module provided for an embodiment of the present application is provided.

[0056] Figure 14 A structure schematic diagram of a micro processing chip provided for an embodiment of the present application is provided.

[0057] Figure 15 Another structure schematic diagram of a micro processing chip provided for an embodiment of the present application is provided. DETAILED DESCRIPTION

[0058] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0059] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0060] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0061] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0062] In related technologies, encoder instruction input mainly takes the form of pulse signals and direction information, or dual-pulse signals. For example, when inputting dual-pulse signals, the increment / decrement of the count and the rotation direction can be determined based on the high and low levels of the two pulse signals and the rising or falling of the effective edges. (Refer to...) Figure 1 As shown. For example, in Figure 1 In the counting process, when counting on TI1 and TI2, if the TI1FP1 signal is rising and the relative signal TI2FP2 is high, then the counting is down. If the TI2FP2 signal is rising and the relative signal TI1FP1 is high, then the counting is up.

[0063] During the aforementioned counting process, pulse counting information and direction information of the dual-channel pulse signals can be determined, typically requiring two signal lines to transmit the dual-channel pulse signals. This method is not suitable in situations where external pin resources are limited or in miniaturized scenarios, such as micro-joints or micro-robots.

[0064] To solve the above problems, the embodiment of the present application provides a signal transmission circuit, a QEP module and a micro processing chip. The signal transmission circuit comprises a first comparison module, a second comparison module and a third comparison module. The first input end of the first comparison module is used for receiving a first signal, the second input end of the first comparison module is used for externally connecting a first reference voltage, the positive side power supply end of the first comparison module is used for externally connecting a second reference voltage, and the negative side power supply end of the first comparison module is used for externally connecting a third reference voltage. The first reference voltage, the second reference voltage and the third reference voltage are all different. The first input end of the second comparison module is electrically connected with the output end of the first comparison module, and the second input end of the second comparison module is used for externally connecting the first reference voltage. The positive side power supply end of the second comparison module is used for externally connecting a first power supply, and the negative side power supply end of the first comparison module is electrically connected with a ground end. The first input end of the third comparison module is used for receiving the first signal, and the second input end of the third comparison module is electrically connected with the output end of the first comparison module. The positive side power supply end of the third comparison module is used for externally connecting a second power supply, and the negative side power supply end of the first comparison module is electrically connected with the ground end. The first comparison module is used for generating a second signal based on the first signal and the first reference voltage. The second comparison module is used for generating a first output signal based on the second signal and the first reference voltage. The third comparison module is used for generating a second output signal based on the second signal and the first signal. The phases of the first output signal and the second output signal are different. In this way, in the embodiment of the present application, only the first signal can be received, and the received first signal can be converted into the first output signal and the second output signal through the first comparison module, the second comparison module and the third comparison module, so as to perform pulse counting and direction information determination according to the first output signal and the second output signal. That is, the first signal is received through one signal line, which can save the signal line input by the instruction end, and can realize the function of transmitting two-way information through one-way signal transmission, so that the application scenarios of pulse counting and direction information determination are more extensive. Moreover, the first signal is decomposed into the first output signal and the second output signal through the first comparison module, the second comparison module and the third comparison module, which can reduce the possibility of relative delay between the first output signal and the second output signal, and improve the accuracy of pulse counting and direction information determination. The following will be described in detail.

[0065] Referring to Figure 2 , a structure diagram of a signal transmission circuit provided by the embodiment of the present application is shown. As Figure 2 shown, the above signal transmission circuit comprises a first comparison module 11, a second comparison module 12 and a third comparison module 13.

[0066] The first input end of the first comparison module 11 is configured to receive the first signal, the second input end of the first comparison module 11 is configured to be connected with the first reference voltage, the positive power supply end of the first comparison module 11 is configured to be connected with the second reference voltage, and the negative power supply end of the first comparison module 11 is configured to be connected with the third reference voltage. The first reference voltage, the second reference voltage and the third reference voltage are different.

[0067] The first input end of the second comparison module 12 is electrically connected with the output end of the first comparison module 11, and the second input end of the second comparison module 12 is configured to be connected with the first reference voltage. The positive power supply end of the second comparison module 12 is configured to be connected with the first power supply, and the negative power supply end of the second comparison module 12 is electrically connected with the ground end.

[0068] The first input end of the third comparison module 13 is configured to receive the first signal, and the second input end of the third comparison module 13 is electrically connected with the output end of the first comparison module 11. The positive power supply end of the third comparison module 13 is configured to be connected with the second power supply, and the negative power supply end of the third comparison module 13 is electrically connected with the ground end.

[0069] The first comparison module 11 is configured to generate a second signal based on the first signal and the first reference voltage.

[0070] The second comparison module 12 is configured to generate a first output signal based on the second signal and the first reference voltage.

[0071] The third comparison module 13 is configured to generate a second output signal based on the second signal and the first signal. The phases of the first output signal and the second output signal are different.

[0072] In the embodiment of the present application, the signal transmission circuit includes the first comparison module 11, the second comparison module 12 and the third comparison module 13. The first input end of the first comparison module 11 is configured to receive the first signal. The first signal is the instruction signal transmitted by the external circuit. The second input end of the first comparison module 11 is configured to receive the first reference voltage, the positive power supply end of the first comparison module 11 is connected with the second reference voltage, and the negative power supply end of the first comparison module 11 is connected with the third reference voltage. In this way, the first comparison module 11 can compare the first signal with the first reference voltage and output the corresponding signal according to the comparison result. For example, when the first input end of the first comparison module 11 is the positive input end and the second input end is the inverting input end, when the voltage of the first signal is greater than the first reference voltage, the second reference voltage signal at the positive power supply end can be output as the second signal. When the voltage of the first signal is less than the first reference voltage, the third reference voltage signal output at the negative power supply end can be output as the second signal.

[0073] The first input end of the second comparison module 12 is electrically connected with the output end of the first comparison module 11, the second input end of the second comparison module 12 receives the first reference voltage, the positive power supply end of the second comparison module 12 is connected with the first power supply, and the negative power supply end of the second comparison module 12 is connected with the ground end. In this way, the second comparison module 12 can compare the second signal received by the first input end of the second comparison module 12 with the first reference voltage received by the second input end of the second comparison module 12, and output a corresponding signal according to the comparison result. For example, when the first input end of the second comparison module 12 is the positive input end of the second comparison module 12 and the second input end of the second comparison module 12 is the inverting input end of the second comparison module 12, the second comparison module 12 can compare the received second signal with the first reference voltage, and output the voltage signal of the first power supply connected with the positive power supply end of the second comparison module 12 as the first output signal when the voltage of the second signal is greater than the first reference voltage. The reference ground signal of the ground end connected with the negative power supply end of the second comparison module 12 is output as the first output signal when the voltage of the second signal is less than the first reference voltage.

[0074] The first input end of the third comparison module 13 receives the first signal, the second input end of the third comparison module 13 is electrically connected with the output end of the first comparison module 11, the positive power supply end of the third comparison module 13 is connected with the second power supply, and the negative power supply end of the third comparison module 13 is connected with the ground end. In this way, the third comparison module 13 can compare the first signal received by the first input end of the third comparison module 13 with the second signal received by the second input end of the third comparison module 13, and output a corresponding signal according to the comparison result. For example, when the first input end of the third comparison module 13 is the positive input end of the third comparison module 13 and the second input end of the third comparison module 13 is the inverting input end of the third comparison module 13, the third comparison module 13 can compare the received first signal with the second signal, and output the voltage signal of the second power supply connected with the positive power supply end of the third comparison module 13 as the second output signal when the voltage of the first signal is greater than the voltage of the second signal. The reference ground signal of the ground end connected with the negative power supply end of the third comparison module 13 is output as the second output signal when the first signal is less than the second signal.

[0075] In this way, the signal transmission circuit can convert the first signal into the first output signal and the second output signal. Moreover, by setting the levels of the signals at different moments in the first signal, the phases of the obtained first output signal and second output signal are different, so that the pulse counting and the determination of the direction information can be performed through the first output signal and the second output signal.

[0076] In some embodiments, the first comparison module 11, the second comparison module 12 and the third comparison module 13 described above can be comparators, as shown in FIG. Figure 3 ​

[0077] In some embodiments, the first input terminals of the first comparison module 11, the second comparison module 12, and the third comparison module 13 are all positive input terminals, and the second input terminals are all inverting input terminals.

[0078] As one possible implementation, to improve the reliability of signal transmission circuits, such as Figure 4 As shown, the signal transmission circuit further includes a first resistor 14, a second resistor 15, and a third resistor 16. One end of the first resistor 14 is electrically connected to the positive power supply terminal of the first comparison module 11. The other end of the first resistor 14 is electrically connected to the output terminal of the first comparison module 11. One end of the second resistor 15 is electrically connected to the positive power supply terminal of the second comparison module 12, and the other end of the second resistor 15 is electrically connected to the output terminal of the second comparison module 12. One end of the third resistor 16 is electrically connected to the positive power supply terminal of the third comparison module 13, and the other end of the third resistor 16 is electrically connected to the output terminal of the third comparison module 13.

[0079] Thus, when the voltage of the first signal received at the first input terminal of the first comparison module 11 is greater than the first reference voltage received at the second input terminal, the voltage of the first resistor 14 can be output as the second signal, that is, the second reference voltage signal can be output as the second signal. When the voltage of the first signal received at the first input terminal of the first comparison module 11 is less than the first reference voltage received at the second input terminal, the third reference voltage signal at the negative power supply terminal can be output as the second signal. When the voltage of the second signal received at the first input terminal of the second comparison module 12 is greater than the first reference voltage received at the second input terminal, the voltage of the second resistor 15 can be output as the first output signal, that is, the voltage signal of the first power supply can be output as the first output signal. When the voltage of the second signal received at the first input terminal of the second comparison module 12 is less than the first reference voltage received at the second input terminal, the reference ground signal at the negative power supply terminal can be output as the first output signal. Similarly, when the voltage of the first signal received at the first input terminal of the third comparison module 13 is greater than the second signal received at the second input terminal, the voltage of the third resistor 16 can be output as the second output signal, that is, the voltage signal of the second power supply can be output as the second output signal. When the voltage of the first signal received at the first input terminal of the third comparison module 13 is less than the voltage of the second signal received at the second input terminal, the reference ground signal at the negative power supply terminal can be output as the second output signal.

[0080] As one possible implementation, in order to output a first output signal and a second output signal with different phases, the voltage value of the first signal is different from the voltage values ​​of the first reference voltage, the second reference voltage, and the third reference voltage.

[0081] As a possible implementation, in order to output the first output signal and the second output signal with different phases, the first signal includes at least two of the first level signal, the second level signal, the third level signal and the fourth level signal, and the first level signal, the second level signal, the third level signal and the fourth level signal are different from each other. That is, the first signal can be a signal composed of at least two level signals of the first level signal, the second level signal, the third level signal and the fourth level signal. At this time, the voltage values of the first signal at at least two time points are different. For example, at a first time point, the first signal is the first level signal, and at a second time point, the first signal is switched to the second level signal.

[0082] In some embodiments, the first signal includes the first level signal, the second level signal, the third level signal and the fourth level signal. For example, the voltage value of the first level signal is represented by V1, the voltage value of the second level signal is represented by V2, the voltage value of the third level signal is represented by V3, the voltage value of the fourth level signal is represented by V4, the voltage value of the first reference voltage is represented by Va, the voltage value of the second reference voltage is represented by Vb, and the voltage value of the third reference voltage is represented by Vc. The values of V1, V2, V3 and V4 are different from each other, and the values of V1, V2, V3 and V4 are also different from the values of Va, Vb and Vc.

[0083] As a possible implementation, in order to facilitate implementation, the voltage value of the first power supply is the same as the voltage value of the second power supply.

[0084] For example, assuming that the first comparison module 11, the second comparison module 12 and the third comparison module 13 are all comparators, in Figure 5 , they are represented by Q1, Q2 and Q3 respectively, as shown in Figure 5 . For ease of illustration, in this example, the first input terminal of the first comparison module 11, the second comparison module 12 and the third comparison module 13 is taken as a positive input terminal, and the second input terminal is taken as a negative input terminal. The first resistor 14, the second resistor 15 and the third resistor 16 are represented by R1, R2 and R3 respectively in Figure 5 . The first signal includes the first level signal, the second level signal, the third level signal and the fourth level signal. The voltage value of the first level signal is represented by V1, the voltage value of the second level signal is represented by V2, the voltage value of the third level signal is represented by V3, the voltage value of the fourth level signal is represented by V4, the voltage value of the first reference voltage is represented by Va, the voltage value of the second reference voltage is represented by Vb, and the voltage value of the third reference voltage is represented by Vc. Among them, the size relationship between V1, V2, V3, V4, Va, Vb and Vc can be V1>Vb>V2>Va>V3>Vc>V4, as shown in Figure 6The first signal received by the first comparator Q1 in one period includes the first level signal, the second level signal, the fourth level signal and the third level signal. As shown in FIG. 2, the first input terminal of the first comparator Q1 can be node A, and the voltage signal at node A can be the first level signal, as shown in FIG. 2. Figure 7a As shown in FIG. 2, the second input terminal of the first comparator Q1 receives the first reference voltage Va, and when the first input terminal receives the first level signal, the voltage value V1 of the first level signal at the first input terminal is greater than Va, and the output terminal of the first comparator Q1 outputs the voltage signal at the first resistor R1. That is, during the period when the first signal is the first level signal, the first comparator Q1 can output the second reference voltage Vb as the second signal. As shown in FIG. 2, the point at which the output terminal of the first comparator Q1 is electrically connected to the first input terminal of the second comparator Q2 and the second input terminal of the third comparator Q3 can be node B, and the electrical signal at node B is the second signal output by the first comparator Q1, as shown in FIG. 2. Figure 7b

[0085] When the first input terminal of the first comparator Q1 receives the second level signal, the voltage value V2 of the second level signal at the first input terminal is greater than Va, and the output terminal of the first comparator Q1 outputs the voltage signal at the first resistor R1. That is, during the period when the first signal is the second level signal, the first comparator Q1 can output the second reference voltage Vb as the second signal, and the electrical signal at node B is the second reference voltage Vb, as shown in FIG. 2. Figure 7b

[0086] When the first input terminal of the first comparator Q1 receives the fourth level signal, the voltage value V4 of the fourth level signal at the first input terminal is less than Va, and the output terminal of the first comparator Q1 outputs the voltage signal at the negative power supply terminal, that is, the third level signal Vc. That is, during the period when the first signal is the fourth level signal, the first comparator Q1 can output the third reference voltage Vc as the second signal, and the electrical signal at node B is the third reference voltage Vc, as shown in FIG. 2. Figure 7b

[0087] When the first input terminal of the first comparator Q1 receives the fourth level signal, the voltage value V4 of the fourth level signal at the first input terminal is less than Va, and the output terminal of the first comparator Q1 outputs the voltage signal at the negative power supply terminal, that is, the third level signal Vc. That is, during the period when the first signal is the fourth level signal, the first comparator Q1 can output the third reference voltage Vc as the second signal, and the electrical signal at node B is the third reference voltage Vc, as shown in FIG. 2. Figure 7b

[0088] ​​​​The first input terminal of the second comparator Q2 is electrically connected with the output terminal of the first comparator Q1. During the second signal outputted by the first comparator Q1 is the second reference voltage Vb, the second input terminal of the second comparator Q2 receives the first reference voltage Va, at this time, the second comparator Q2 can compare the first reference voltage Va with the second reference voltage Vb, since the second reference voltage Vb is greater than the first reference voltage Va, at this time, the second comparator Q2 can output the voltage signal at the second resistor R3 as the first output signal during the first comparator Q1 outputs the second reference voltage Vb, that is, output the voltage signal of the first power supply, refer to Figure 7c as shown.

[0089] When the second signal outputted by the first comparator Q1 is the third reference voltage Vc, the second input terminal of the second comparator Q2 receives the first reference voltage Va, at this time, the second comparator Q2 can compare the first reference voltage Va with the third reference voltage Vc, since the third reference voltage Vc is less than the first reference voltage Va, at this time, the second comparator Q2 can output the reference ground signal received by the negative power supply terminal of the second comparator Q2 as the first output signal during the first comparator Q1 outputs the third reference voltage Vc, that is, output the reference ground signal, refer to Figure 7c as shown. In this example, the first power supply and the second power supply are both 3.3v (volt) power supply, and the reference ground signal is 0v voltage signal.

[0090] Similarly, the second input terminal of the third comparator Q3 is electrically connected with the output terminal of the first comparator Q1, and the first input terminal of the third comparator Q3 receives the first signal. Therefore, during the first comparator Q1 outputs the second reference voltage Vb, if the first signal is the first level signal V1, the third comparator Q3 can compare the first level signal V1 with the second reference voltage Vb, since the voltage value of the first level signal V1 is greater than the second reference voltage Vb, the third comparator Q3 can output the voltage signal at the third resistor R3 as the second output signal. That is, during the first comparator Q1 outputs the second reference voltage Vb and the first signal is the first level signal V1, the third comparator Q3 outputs the voltage signal of the second power supply, refer to Figure 7d as shown.

[0091] During the first comparator Q1 outputs the second reference voltage Vb, if the first signal is switched to the second level signal V2, the third comparator Q3 can compare the second level signal V2 with the second reference voltage Vb, since the voltage value of the second level signal V2 is less than the second reference voltage Vb, the third comparator Q3 can output the reference ground signal of the negative power supply terminal as the second output signal. That is, during the first comparator Q1 outputs the second reference voltage Vb and the first signal is switched to the second level signal V2, the third comparator Q3 outputs the reference ground signal, refer to Figure 7d as shown.

[0092] During the period when the first comparator Q1 outputs the third reference voltage Vc, if the first signal switches to the fourth level signal V4, the third comparator Q3 can compare the fourth level signal V4 with the third reference voltage Vc. Since the voltage value of the fourth level signal V4 is less than the third reference voltage Vc, the third comparator Q3 can output the reference ground signal of the negative side power supply end as the second output signal. That is, during the period when the first comparator Q1 outputs the third reference voltage Vc and the first signal switches to the fourth level signal V4, the third comparator Q3 outputs the reference ground signal, as shown in FIG. 4. Figure 7d

[0093] During the period when the first comparator Q1 outputs the third reference voltage Vc, if the first signal switches to the third level signal V3, the third comparator Q3 can compare the third level signal V3 with the third reference voltage Vc. Since the voltage value of the third level signal V3 is greater than the third reference voltage Vc, the third comparator Q3 can output the voltage signal at the third resistor R3 as the second output signal. That is, during the period when the first comparator Q1 outputs the third reference voltage Vc and the first signal is the third level signal V3, the third comparator Q3 outputs the voltage signal of the second power supply, as shown in FIG. 5. Figure 7d

[0094] In this way, by means of the above-mentioned signal transmission circuit, the first signal can be decomposed into the dual pulse signals of the first output signal and the second output signal, wherein the phase of the second output signal is ahead of the phase of the first output signal by half a period, so that the pulse counting and the determination of the direction information can be performed according to the first output signal and the second output signal output by the signal transmission circuit. Moreover, only one signal line is needed to receive the first signal, which reduces the complexity of the pulse counting and the determination of the direction information, and the interface space.

[0095] In other embodiments, the phase of the first output signal needs to be ahead of the phase of the second output signal by half a period. At this time, only the level signal contained in the first signal needs to be adjusted. For example, when the first signal received by the first comparator Q1 in one period includes the second level signal, the first level signal, the third level signal and the fourth level signal, the electrical signal at the node A can be as shown in FIG. 6. Figure 8a

[0096] The first comparator Q1 can compare the first signal received by the first input end with the first reference voltage Va received by the second input end and output the second signal. At this time, the output second signal can be as shown in FIG. 7. Wherein, the process that the first comparator Q1 compares the first signal with the first reference voltage Va and outputs the second signal can refer to the above-mentioned process, which will not be described here again. Figure 8b

[0097] ​​​​The first input terminal of the second comparator Q2 is electrically connected with the output terminal of the first comparator Q1, and the second input terminal of the second comparator Q2 receives the first reference voltage Va. The second comparator Q2 can compare the second signal received by the first input terminal with the first reference voltage Va received by the second input terminal, and output a first output signal. At this time, the output first output signal can refer to Figure 8c As shown in FIG. 6. Wherein, the process that the second comparator Q2 compares the second signal with the first reference voltage Va and outputs the first output signal can refer to the above process, which will not be repeated here.

[0098] Similarly, the second input terminal of the third comparator Q3 is electrically connected with the output terminal of the first comparator Q1, and the first input terminal of the third comparator Q3 receives the first signal. The third comparator Q3 can compare the second signal received by the second input terminal with the first signal received by the first input terminal, and output a second output signal. At this time, the output second output signal can refer to Figure 8d As shown in FIG. 7. Wherein, the process that the third comparator Q3 compares the second signal with the first signal and outputs the second output signal can refer to the above process, which will not be repeated here.

[0099] In this way, through the above signal transmission circuit, the first signal can be decomposed into the dual pulse signals of the first output signal and the second output signal, wherein the phase of the second output signal lags behind the phase of the first output signal by half a period.

[0100] That is, in the embodiment of the present application, the order of each voltage level can be adjusted by the 1-way instruction signal, that is, the first signal, so as to generate two kinds of dual pulse signals in advance or lag state, so that the subsequent processor module can determine the pulse count and direction information according to the first output signal and the second output signal output by the signal transmission circuit. At the same time, the first output signal and the second output signal are output by two groups of comparators, and the delay relative to the first signal is basically the same, which can avoid the relative delay phenomenon of two signals. In this way, the first signal transmitted externally can be received through one signal line, and one signal line of the instruction end input can be saved.

[0101] As a possible implementation manner, the above signal transmission circuit, as shown in Figure 9 Further comprises an encoder interface counting circuit 17.

[0102] The output terminal of the second comparison module 12 is electrically connected with the first end of the encoder interface counting circuit 17, and the output terminal of the third comparison module 13 is electrically connected with the second end of the encoder interface counting circuit 17.

[0103] The encoder interface counting circuit 17 is configured to count the pulse signals and / or determine the direction of the pulse signals according to the first output signal output by the second comparison module 12 and the second output signal output by the third comparison module 13.

[0104] In the embodiments of the present application, the signal transmission circuit further comprises an encoder interface counting circuit 17. A first end of the encoder interface counting circuit 17 is electrically connected to an output end of the second comparison module 12 in the signal transmission circuit, and a second end of the encoder interface counting circuit 17 is electrically connected to an output end of the third comparison module 13 in the signal transmission circuit. In this way, the signal transmission circuit can transmit the first output signal and the second output signal to the encoder interface counting circuit 17. The encoder interface counting circuit 17 can count the pulses and determine the direction according to the received first output signal and second output signal. In some embodiments, the encoder interface counting circuit 17 can count the pulses and determine the direction according to the high-low level relationship of the first output signal and the second output signal.

[0105] In some embodiments, as shown in FIG. 1, the encoder interface counting circuit 17 comprises a filter and edge detector 171, an encoder interface 172, a pre-divider 173, and a counter 174. Figure 10

[0106] The first end of the filter and edge detector 171 is electrically connected to the output end of the second comparison module 12, and the second end of the filter and edge detector 171 is electrically connected to the output end of the third comparison module 13.

[0107] The first interface of the encoder interface 172 is electrically connected to the first output end of the filter and edge detector 171, and the second interface of the encoder interface 172 is electrically connected to the second output end of the filter and edge detector 171. The input end of the pre-divider 173 is electrically connected to the output end of the encoder interface 172, and the output end of the pre-divider 173 is electrically connected to the input end of the counter 174.

[0108] The filter and edge detector 171 is configured to filter the input signal and capture the edge position of the input signal.

[0109] The encoder interface 172 is configured to control the counting clock of the counter 174 through the pre-divider 173, and control the counting of the counter 174 according to the first output signal and the second output signal.

[0110] ​In the embodiment of the present application, the encoder interface counting circuit 17 comprises a filter and edge detector 171, an encoder interface 172, a pre-divider 173, and a counter 174. The first end of the filter and edge detector 171 is electrically connected to the output end of the second comparison module 12 in the signal transmission circuit, and the second end of the filter and edge detector 171 is electrically connected to the output end of the third comparison module 13 in the signal transmission circuit. In this way, the signal transmission circuit can transmit the first output signal to the first end of the filter and edge detector 171 through the output end of the second comparison module 12, and transmit the second output signal to the second end of the filter and edge detector 171 through the output end of the third comparison module 13. The filter and edge detector 171 can filter the received first output signal and second output signal to filter out the interference signals, capture the edge positions of the filtered first output signal and second output signal, and determine the polarity of the first output signal and the second output signal, for example, whether it is a high-level signal or a low-level signal, so as to determine the rotation direction of the encoder. The relationship between the counting direction of the encoder interface counting circuit 17 and the signals received by the encoder interface circuit can be referred to the figure. Figure 1 In the embodiment of the present application, one of the first output signal output by the second comparison module 12 in the signal transmission circuit and the second output signal output by the third comparison module 13 in the signal transmission circuit is the A-phase signal corresponding to the encoder interface counting circuit, and the other is the B-phase signal in the encoder interface counting circuit. As shown in the figure, Figure 11a If the A-phase signal changes first and the B-phase signal changes later, the encoder rotates forward, and the counter needs to be incremented. As shown in the figure, Figure 11b If the B-phase signal changes first and the A-phase signal changes later, the encoder rotates reversely, and the counter needs to be decremented. For the convenience of description, in the embodiment of the present application, the first output signal output by the second comparison module 12 in the signal transmission circuit is taken as the A-phase signal corresponding to the encoder interface counting circuit, and the second output signal output by the third comparison module 13 in the signal transmission circuit is taken as the B-phase signal in the encoder interface counting circuit for illustration.

[0111] The filter and edge detector 171 can detect the polarity of the B-phase signal when the A-phase signal edge is detected, and the polarity of the A-phase signal when the B-phase signal edge is detected, so as to determine the rotation direction of the encoder. As shown in the figure, when the rising edge of the A-phase signal is a low-level signal, that is, when the rising edge of the first output signal is a low-level signal and the rising edge of the second output signal is a low-level signal, it can be determined that the encoder rotates forward, and the counter needs to be incremented at this time. Figure 12

[0112] When the falling edge of the A-phase signal is a high-level signal, that is, when the falling edge of the first output signal is a high-level signal and the falling edge of the second output signal is a high-level signal, it can be determined that the encoder rotates forward, and the counter needs to be incremented at this time.​

[0113] When the rising edge of the B phase signal and the A phase signal is high, that is, the rising edge of the second output signal and the first output signal is high, it can be determined that the encoder is rotating forward, and the counter needs to be added at this time.

[0114] When the falling edge of the B phase signal and the A phase signal is low, that is, the falling edge of the second output signal and the first output signal is low, it can be determined that the encoder is rotating forward, and the counter needs to be added at this time.

[0115] When the rising edge of the A phase signal and the B phase signal is high, that is, the rising edge of the first output signal and the second output signal is high, it can be determined that the encoder is rotating backward, and the counter needs to be reduced at this time.

[0116] When the falling edge of the A phase signal and the B phase signal is low, that is, the falling edge of the first output signal and the second output signal is low, it can be determined that the encoder is rotating backward, and the counter needs to be reduced at this time.

[0117] When the rising edge of the B phase signal and the A phase signal is low, that is, the rising edge of the second output signal and the first output signal is low, it can be determined that the encoder is rotating backward, and the counter needs to be reduced at this time.

[0118] When the falling edge of the B phase signal and the A phase signal is high, that is, the falling edge of the second output signal and the first output signal is high, it can be determined that the encoder is rotating backward, and the counter needs to be reduced at this time.

[0119] The first interface of the encoder interface 172 is electrically connected with the first output end of the filter and edge detector 171, and the second interface of the encoder interface 172 is electrically connected with the second output end of the filter and edge detector 171. The input end of the pre-divider 173 is electrically connected with the output end of the encoder interface 172, and the output end of the pre-divider 173 is electrically connected with the input end of the counter 174. In this way, the encoder interface 172 can obtain the first output signal and the second output signal, that is, the A phase signal and the B phase signal, according to the first interface and the second interface, determine the rotation direction of the encoder by detecting the polarity and the edge position between the A phase signal and the B phase signal, and then determine whether the counter 174 needs to be added or reduced. Moreover, the encoder interface 172 can control the counting clock of the counter 174 by controlling the pre-divider 173, so as to meet the counting requirements of different frequencies.

[0120] It should be noted that, since the filter and edge detector 171 receives two output signals, i.e., the first output signal and the second output signal, the filter and edge detector 171 can perform filtering and edge detection processing on each output signal. At this time, the filter and edge detector 171 can include two sub-modules to perform filtering and edge detection processing on the first output signal and the second output signal, respectively.

[0121] In this way, in the embodiment of the present application, the signal transmission circuit can receive one instruction signal, i.e., the first signal, and decompose the first signal into two first output signals and second output signals of different phases. The phase difference between the first output signal and the second output signal is 90 degrees. In this way, the encoder interface counting circuit 17 can perform pulse counting and determination of the rotation direction of the encoder according to the first output signal and the second output signal. In the embodiment of the present application, only one instruction signal needs to be received to realize pulse counting and determination of the rotation direction of the encoder, which reduces the number of received instruction signals, thereby reducing the signal line and input pin for transmitting the instruction signal, and improving the possibility of applying pulse counting and determination of the rotation direction of the encoder to a miniature circuit.

[0122] The embodiment of the present application also provides a QEP (Quadrature Encoder Pulse) module, which includes the signal transmission circuit 1301 described in the above embodiment.

[0123] Reference Figure 13 As shown in the figure, the QEP module further includes a programmable input unit 1302, a quadrature encoder unit 1303, and a position counting control unit 1304. Wherein,

[0124] The first end of the programmable input unit 1302 is electrically connected to the first output end of the signal transmission circuit 1301, the second end of the programmable input unit 1302 is electrically connected to the second output end of the signal transmission circuit 1301, the output end of the programmable input unit 1302 is electrically connected to the input end of the quadrature encoder unit 1303, and the output end of the quadrature encoder unit 1303 is electrically connected to the position counting control unit 1304.

[0125] The programmable input unit 1302 is used to receive the first output signal and the second output signal output by the signal transmission circuit 1301, and convert the first output signal and the second output signal into a first encoded signal and a second encoded signal, and transmit the first encoded signal and the second encoded signal to the quadrature encoder unit 1303.

[0126] The orthogonal encoder unit 1303 is configured to determine the sequence of the first encoded signal and the second encoded signal, and determine the rotation direction of the encoder and control the counting of the position counting control unit 1304 according to the sequence of the first encoded signal and the second encoded signal.

[0127] In the embodiment of the present application, the QEP module further includes a programmable input unit 1302, an orthogonal encoder unit 1303, and a position counting control unit 1304. The first end of the programmable input unit 1302 is electrically connected to the first output end of the signal transmission circuit 1301, and the second end of the programmable input unit 1302 is electrically connected to the second output end of the signal transmission circuit 1301, so that the programmable input unit 1302 can receive the first output signal and the second output signal output by the signal transmission circuit 1301. In addition, the programmable input unit 1302 is connected to the encoder, for example, connected to the optical encoder. The programmable input unit 1302 can obtain the index signal EQEPI and the gating input EQEPS of the encoder. In this way, the programmable input unit 1302 can determine the first encoded signal EQEPA IN and the second encoded signal EQEPB IN corresponding to the first output signal, the second output signal, the index signal EQEPI and the gating input EQEPS. In some embodiments, the programmable input unit 1302 can also generate signals such as EQEPI IN, EQEPI OUT, EQEPS OE, EQEPS IN, EQEPS OUT, and EQEPA OE. The output end of the programmable input unit 1302 is electrically connected to the input end of the orthogonal encoder unit 1303, so that the programmable input unit 1302 can transmit the generated signals to the orthogonal encoder unit 1303.

[0128] The orthogonal encoder unit 1303 is configured to receive the first encoded signal and the second encoded signal, and determine the sequence of the first encoded signal and the second encoded signal according to the first encoded signal and the second encoded signal, and determine the rotation direction QDIR of the encoder and control the counting of the position counting control unit 1304 according to the sequence of the first encoded signal and the second encoded signal.

[0129] That is, the quadrature encoder unit 1303 can provide the position counting control unit 1304 with a counting clock QCLK by detecting the edges of the first and second encoded signals. The quadrature encoder unit 1303 can determine the order of the two input signals, i.e., the order of the first and second encoded signals, and determine the rotation direction of the encoder, i.e., the counting direction QDIR, to determine the increment and decrement of the position counting control unit 1304. It should be noted that when the motor rotor connected to the optical encoder rotates to any position on the circular plane, there will be a specific position count value corresponding thereto, and the motor position state can be obtained by calculation.

[0130] In some embodiments, the position counting control unit 1304 includes a position counter and a position count register. The position counter is used for counting. The position count register is used for storing the counting result of the position counter.

[0131] In some embodiments, the QEP module further includes a quadrature capture unit 1305 and a time base unit 1306. The quadrature capture unit is electrically connected to the position counting control unit 1304. The quadrature capture unit 1305 is used to measure the motor speed according to the quadrature clock QCLK generated by the rising edge / descending edge of the two input clocks when the motor speed is less than the minimum threshold.

[0132] The time base unit 1306 is connected to the position counting control unit 1304 and the system clock. The time base unit 1306 is used to calculate the speed according to the periodic interrupts generated by the system clock.

[0133] In some embodiments, the QEP module further includes:

[0134] The position measurement module is used to reset the position counter in the position counting control unit 1304 to 0 when the index signal QEPI is in forward motion when the QEP module is working in the position event, reset position count mode. When the index signal QEPI is in reverse motion, the position counter is reset to the value in the position count register in the position counting control unit 1304, and the rotor mechanical angle is determined according to the position count value of the position counter and the resolution line number of the optical encoder.

[0135] The motor speed measurement module is used to measure the speed by the M method when the motor speed is greater than the maximum speed threshold. When the motor speed is less than the minimum speed threshold, the speed is measured by the T method. When the motor speed is greater than or equal to the minimum speed threshold and less than or equal to the maximum speed threshold, the speed is measured by the M / T combined method.

[0136] When the motor speed is greater than the maximum speed threshold, the time unit inside the time base unit 1306 is used as the time base.

[0137] When the motor speed is less than the minimum speed threshold, the edge detection unit 1305 is used to measure the time between a certain number of position count pulses, i.e. the timer period, to measure the time between two position events.

[0138] When the motor speed is greater than or equal to the minimum speed threshold and less than or equal to the maximum speed threshold, the speed is in the process of smooth transition from low to high.

[0139] When the resolution of the optical encoder is X, the value in the position count register is 4X-1, and when the motor rotor rotates 360°, the count value in the position count unit changes linearly from 0 to 4X-1, so the position count value QPOSCNT proportional to the rotor position can be directly obtained from the position count register, and the rotor mechanical angle can be calculated as: θ=QPOSCNT / 4X.

[0140] According to the actual situation, the mechanical angle will change due to different installation processes of the motor rotor or different choices of the reference coordinate system, so an angle offset θ ex is introduced in the above formula to correct the angle, and a new rotor mechanical angle calculation formula is obtained.

[0141] The position measurement unit is used to determine the rotor mechanical angle by using the formula .

[0142] Where θ is the rotor mechanical angle, QPOSCNT is the position count value of the position counter, X is the resolution of the optical encoder, and θ ex is the angle offset.

[0143] The motor speed measurement module specifically includes:

[0144] The first motor speed measurement unit is used to determine the motor speed by using the formula .

[0145] The second motor speed measurement unit is used to determine the motor speed by using the formula .

[0146] The third motor speed measurement unit is used to determine the motor speed by using the formula S c =axS t +bxS m .

[0147] Where S m is the motor speed when the motor speed is greater than the maximum speed threshold, and S t is the motor speed when the motor speed is less than the minimum speed threshold.S is the motor speed when the motor speed is less than the minimum speed threshold c Q is the motor speed when the motor speed is greater than or equal to the minimum speed threshold and less than or equal to the maximum speed threshold P F is the value in the position count register s D is the measurement frequency P C is the reciprocal of the position pulse division number s Q is the system clock c a and b are weight coefficients, a+b=1, and a and b are the values in the position count register QCPRDLAT S H and S L are the maximum speed threshold and the minimum speed threshold, respectively.

[0148] In specific implementations, the utility model further provides a micro processing chip. The micro processing chip comprises the signal transmission circuit described in the above embodiments, as shown in Figure 14 Or, the micro processing chip comprises the QEP module described in the above embodiments, as shown in Figure 15

[0149] The micro processing chip may be, for example, an MCU (Microcontroller Unit), a DSP (Digital Signal Processing), an MPU (Microprocessor Unit), a micro CPU (Central Processing Unit), or other micro central control chips or system-on-chip chips that can process digital signals, analog signals, or perform signal control functions, instruction processing, and operation functions. Of course, the micro processing chip may also be other types of devices, and the present application does not limit this.

[0150] Corresponding to the above embodiments, the present application further provides an electronic device comprising the signal transmission circuit or the QEP module or the micro processing chip described in the above embodiments.

[0151] Those skilled in the art can clearly understand that the technology in the embodiments of the utility model can be realized by means of software and necessary general hardware platforms. Based on such understanding, the technical solutions in the embodiments of the utility model can be embodied in the form of a software product, which can be stored in a storage medium such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the utility model.

[0152] ​The same or similar parts between various embodiments in the specification can be referred to each other. Especially, for the device embodiments and the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A signal transmission circuit, characterized by comprising: Comprise: A first comparison module, a second comparison module and a third comparison module; wherein, The first input end of the first comparison module is used for receiving a first signal, the second input end of the first comparison module is used for connecting a first reference voltage, the positive side power supply end of the first comparison module is used for connecting a second reference voltage, and the negative side power supply end of the first comparison module is used for connecting a third reference voltage; the first reference voltage, the second reference voltage and the third reference voltage are all different; The first input end of the second comparison module is electrically connected with the output end of the first comparison module, and the second input end of the second comparison module is used for connecting the first reference voltage; the positive side power supply end of the second comparison module is used for connecting a first power supply, and the negative side power supply end of the second comparison module is electrically connected with a ground end; The first input end of the third comparison module is used for receiving a first signal, and the second input end of the third comparison module is electrically connected with the output end of the first comparison module; the positive side power supply end of the third comparison module is used for connecting a second power supply, and the negative side power supply end of the third comparison module is electrically connected with a ground end; The first comparison module is used for generating a second signal based on the first signal and the first reference voltage; The second comparison module is used for generating a first output signal based on the second signal and the first reference voltage; The third comparison module is used for generating a second output signal based on the second signal and the first signal; the phases of the first output signal and the second output signal are different.

2. The circuit of claim 1, wherein, Further comprise: A first resistor, a second resistor and a third resistor; One end of the first resistor is electrically connected with the positive side power supply end of the first comparison module, and the other end of the first resistor is electrically connected with the output end of the first comparison module; One end of the second resistor is electrically connected with the positive side power supply end of the second comparison module, and the other end of the second resistor is electrically connected with the output end of the second comparison module; One end of the third resistor is electrically connected with the positive side power supply end of the third comparison module, and the other end of the third resistor is electrically connected with the output end of the third comparison module.

3. The circuit of claim 1, wherein, The voltage value of the first signal is different from the voltage values of the first reference voltage, the second reference voltage and the third reference voltage.

4. The circuit of claim 3, wherein, The first signal comprises at least two of a first level signal, a second level signal, a third level signal and a fourth level signal, and the first level signal, the second level signal, the third level signal and the fourth level signal are all different.

5. The circuit of claim 1, wherein, The voltage value of the first power supply is the same as the voltage value of the second power supply.

6. The circuit of claim 1, wherein Further comprise: An encoder interface counting circuit; The output end of the second comparison module is electrically connected with the first end of the encoder interface counting circuit, and the output end of the third comparison module is electrically connected with the second end of the encoder interface counting circuit; The encoder interface counting circuit is used for counting pulse signals and / or judging the direction of pulse signals according to the first output signal output by the second comparison module and the second output signal output by the third comparison module.

7. The circuit of claim 6, wherein, The encoder interface counting circuit comprises a filter and edge detector, an encoder interface, a pre-frequency divider, and a counter. The first end of the filter and edge detector is electrically connected to the output end of the second comparison module, and the second end of the filter and edge detector is electrically connected to the output end of the third comparison module. The first interface of the encoder interface is electrically connected to the first output end of the filter and edge detector, and the second interface of the encoder interface is electrically connected to the second output end of the filter and edge detector. The filter and edge detector is configured to filter an input signal and capture the edge position of the input signal. The encoder interface is configured to control the counting clock of the counter through the pre-frequency divider and control the counting of the counter according to the first output signal and the second output signal.

8. A QEP module characterized by, The signal transmission circuit comprises the signal transmission circuit according to any one of claims 1-5.

9. The QEP module of claim 8, wherein, Further comprising: a programmable input unit, a quadrature encoder unit, and a position counting control unit, wherein the first end of the programmable input unit is electrically connected to the first output end of the signal transmission circuit, the second end of the programmable input unit is electrically connected to the second output end of the signal transmission circuit, the output end of the programmable input unit is electrically connected to the input end of the quadrature encoder unit, and the output end of the quadrature encoder unit is electrically connected to the position counting control unit; the programmable input unit is configured to receive the first output signal and the second output signal output by the signal transmission circuit, and convert the first output signal and the second output signal into a first encoded signal and a second encoded signal, and transmit the first encoded signal and the second encoded signal to the quadrature encoder unit; the quadrature encoder unit is configured to determine the sequence of the first encoded signal and the second encoded signal, and determine the rotation direction of the encoder and control the counting of the position counting control unit according to the sequence of the first encoded signal and the second encoded signal.

10. A microprocessing chip, characterized by The signal transmission circuit comprises the signal transmission circuit according to any one of claims 1-7 or the QEP module according to claim 8 or 9.

Images